JPH06268099A - Ceramic package for semiconductor device - Google Patents
Ceramic package for semiconductor deviceInfo
- Publication number
- JPH06268099A JPH06268099A JP5181393A JP5181393A JPH06268099A JP H06268099 A JPH06268099 A JP H06268099A JP 5181393 A JP5181393 A JP 5181393A JP 5181393 A JP5181393 A JP 5181393A JP H06268099 A JPH06268099 A JP H06268099A
- Authority
- JP
- Japan
- Prior art keywords
- thermal expansion
- semiconductor element
- heat sink
- package body
- coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置用セラミック
パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic package for semiconductor devices.
【0002】[0002]
【従来の技術】CPU等の発熱量の大きな半導体素子を
搭載するパッケージでは放熱性に優れることが要求され
る。このため図5に示すように半導体素子10を金属製
のヒートシンク11上に搭載したセラミックパッケージ
が知られている。上記のヒートシンク11は放熱性に優
れるCu−W合金、Cu−Mo合金,Cu−Ni−W合
金などが用いられている。また一方これら合金はその熱
膨張係数がパッケージ本体12のセラミックの熱膨張係
数とほぼマッチングするが、半導体素子10のSiとは
熱膨張係数の差が大きいため、Siと熱膨張係数が近い
Mo板13をヒートシンク11上にろう付けしてこのM
o板13上に半導体素子を搭載するようにしている。2. Description of the Related Art A package in which a semiconductor element such as a CPU that generates a large amount of heat is mounted is required to have excellent heat dissipation. Therefore, there is known a ceramic package in which the semiconductor element 10 is mounted on a metal heat sink 11 as shown in FIG. The heat sink 11 is made of a Cu-W alloy, a Cu-Mo alloy, a Cu-Ni-W alloy or the like, which has excellent heat dissipation. On the other hand, the thermal expansion coefficient of these alloys substantially matches the thermal expansion coefficient of the ceramic of the package body 12, but since the difference in the thermal expansion coefficient between Si of the semiconductor element 10 is large, the Mo plate having a thermal expansion coefficient close to that of Si is used. 13 is brazed on the heat sink 11
A semiconductor element is mounted on the o plate 13.
【0003】[0003]
【発明が解決しようとする課題】上記のように、ヒート
シンク11とパッケージ本体12との熱膨張係数はほぼ
マッチングし、両者間をろう材にてろう付する際熱的歪
みはほとんど生じない。またMo板13と半導体素子と
の熱膨張係数もほぼマッチングがとれているから両者間
で熱的歪みは生じない。しかしながらヒートシンク11
とMo板13との間の熱膨張係数の差が大きく、ヒート
シンク11とMo板13に反りが生じて半導体素子10
に悪影響を与える問題点がある。As described above, the thermal expansion coefficients of the heat sink 11 and the package body 12 are substantially matched with each other, and thermal brazing hardly occurs when brazing them with a brazing material. Further, since the thermal expansion coefficients of the Mo plate 13 and the semiconductor element are almost matched, thermal strain does not occur between them. However, the heat sink 11
The difference in the coefficient of thermal expansion between the Mo plate 13 and the Mo plate 13 is large, and the heat sink 11 and the Mo plate 13 are warped, and the semiconductor element 10
There is a problem that adversely affects.
【0004】そこで、本発明は上記問題点を解決すべく
なされたものであり、その目的とするところは、ヒート
シンクの反りを防止できる半導体装置用セラミックパッ
ケージを提供するにある。Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to provide a ceramic package for a semiconductor device capable of preventing the heat sink from warping.
【0005】[0005]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、セラミック製の
パッケージ本体に金属製のヒートシンクが接合され、該
ヒートシンク上に半導体素子を搭載するようにした半導
体装置用セラミックパッケージにおいて、前記ヒートシ
ンクは一体に焼結して形成され、パッケージ本体との接
合部と半導体素子の搭載部とでは熱膨張係数が異なり、
パッケージ本体との接合部の熱膨張係数がパッケージ本
体と同程度の熱膨張係数を有し、半導体素子搭載部の熱
膨張係数が搭載する半導体素子と同程度の熱膨張係数を
有することを特徴としている。前記ヒートシンクは、パ
ッケージ本体との接合部がCu−W、Cu−Moまたは
Cu−Ni−W系の焼結金属でCuの含有量が10〜15%
であり、半導体素子搭載部がCuの含有量が0 〜10%の
W−Cu系またはCuの含有量が0〜10%のMo−C
u系の焼結金属であるようにすると好適である。The present invention has the following constitution in order to achieve the above object. That is, in a ceramic package for a semiconductor device, in which a metal heat sink is joined to a ceramic package body, and a semiconductor element is mounted on the heat sink, the heat sink is formed by being integrally sintered, The thermal expansion coefficient is different between the joint part and the mounting part of the semiconductor element,
The thermal expansion coefficient of the joint portion with the package body has a thermal expansion coefficient similar to that of the package body, and the thermal expansion coefficient of the semiconductor element mounting portion has a thermal expansion coefficient similar to that of the mounted semiconductor element. There is. The heat sink has a Cu-W, Cu-Mo, or Cu-Ni-W-based sintered metal bonded to the package body and has a Cu content of 10 to 15%.
The content of Cu in the semiconductor element mounting portion is 0 to 10% W-Cu system or the content of Cu is 0 to 10% Mo-C.
It is preferable to use a u-based sintered metal.
【0006】[0006]
【作用】本発明に係る半導体装置用セラミックパッケー
ジによれば、表裏で熱膨張係数が異なる一体の焼結金属
であって、パッケージ本体への接合部の熱膨張係数がパ
ッケージ本体と同程度の熱膨張係数を有し、半導体素子
搭載部の熱膨張係数が半導体素子と同程度の熱膨張係数
を有するヒートシンクを用いたので、ヒートシンクに反
りが発生しない。According to the ceramic package for a semiconductor device of the present invention, it is an integral sintered metal having different thermal expansion coefficients on the front and back sides, and the thermal expansion coefficient of the joint portion to the package body is similar to that of the package body. Since the heat sink having the coefficient of expansion and the coefficient of thermal expansion of the semiconductor element mounting portion is the same as that of the semiconductor element is used, the heat sink does not warp.
【0007】[0007]
【実施例】以下、本発明の好適な実施例を添付図面に基
づいて詳細に説明する。図1は半導体装置用のセラミッ
クパッケージ10の一例を示す断面図である。20はパ
ッケージ本体であり、グリーンシートを積層して焼成さ
れて形成されており、内部に配線パターンが形成されて
いる(図示せず)。21は内部配線パターンと接続され
てパッケージ本体20にろう付けされている外部接続用
のピンである。内部配線パターンはパッケージ本体20
の内部段差上に露出され、この露出パターンとヒートシ
ンク22上に搭載された半導体素子23との間でワイヤ
により接続されるようになっている。ヒートシンク22
はパッケージ本体20の中央貫通孔を覆ってパッケージ
本体20にろう付けされる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a sectional view showing an example of a ceramic package 10 for a semiconductor device. Reference numeral 20 denotes a package body, which is formed by stacking and firing green sheets and has a wiring pattern formed therein (not shown). Reference numeral 21 denotes an external connection pin that is connected to the internal wiring pattern and is brazed to the package body 20. The internal wiring pattern is the package body 20
The exposed pattern is exposed on the internal step, and a wire is connected between the exposed pattern and the semiconductor element 23 mounted on the heat sink 22. Heat sink 22
Is brazed to the package body 20 while covering the central through hole of the package body 20.
【0008】ヒートシンク22は図2に示されるよう
に、半導体素子の搭載部とパッケージ本体への接合部で
熱膨張係数が異なる焼結金属で一体に形成され、パッケ
ージ本体20とろう付けされる部分の熱膨張係数がパッ
ケージ本体20のセラミックの熱膨張係数に近い熱膨張
係数(7.0 〜8.0 ×10-6/℃)の焼結金属Aに形成さ
れ、また半導体素子23が搭載される部分の熱膨張係数
が半導体素子23のSiの熱膨張係数(3.4 ×10-6/
℃)に近い熱膨張係数(3.5 〜6.0 ×10-6/℃)の焼結
金属Bに形成されている。ヒートシンク22の素材構成
は次の構成によるのが好適である。すなわち、パッケー
ジ本体への接合側となる焼結金属AをCu−W、Cu−
MoまたはCu−Ni−W系の焼結金属であって、Cu
の含有量が10〜15%のものとする。また、半導体素子搭
載側となる焼結金属BをCuの含有量が0 〜10%のW−
Cu系またはCuの含有量が0 〜10%のMo−Cu系の
ものとする。上記の素材構成とすることにより、前記し
たような熱膨張係数のマッチングをとることができる。As shown in FIG. 2, the heat sink 22 is integrally formed of a sintered metal having a different thermal expansion coefficient at the mounting portion of the semiconductor element and the joint portion to the package body, and is brazed to the package body 20. Is formed in the sintered metal A having a coefficient of thermal expansion (7.0 to 8.0 × 10 −6 / ° C.) close to that of the ceramic of the package body 20, and the heat of the portion where the semiconductor element 23 is mounted. The thermal expansion coefficient of the semiconductor element 23 is Si (3.4 × 10 -6 /
C) and the thermal expansion coefficient (3.5 to 6.0 × 10 −6 / ° C.) of the sintered metal B. The material configuration of the heat sink 22 is preferably the following configuration. That is, the sintered metal A that is to be bonded to the package body is Cu-W, Cu-
Mo or Cu-Ni-W system sintered metal, Cu
Content of 10 to 15%. In addition, the sintered metal B on the semiconductor element mounting side has a W content of Cu of 0 to 10%.
A Cu-based or Mo-Cu-based material having a Cu content of 0 to 10% is used. By adopting the above-mentioned material configuration, the matching of the thermal expansion coefficient as described above can be achieved.
【0009】上記のように一体構造のもので部分的に熱
膨張係数の相違する焼結金属は次のようにして製造し
た。図3に示すように、銅粉とタングステン粉の割合の
異なる粉末成形板A層、C層、B層を積層し、これを焼
結して一体化した。A層はW:Cuが85:15 、C層は9
0:10 、B層は95:5となるように調整して板状に圧縮成
形した粉末成形板である。このように積層して焼結する
ことにより互いの界面も結着され一体構造の焼結金属が
形成された。こうしてあらかじめ配合割合の異なる粉末
成形板を形成し、これを積層して焼結することにより、
層間の多少の金属の移動はあるが、ほぼ当初の割合を維
持し、表裏面で段階的に配合割合のことなる焼結金属が
得られた。銅粉の多いA層の熱膨張係数はセラミックの
パッケージ本体20の熱膨張係数に近い熱膨張係数を有
しており、また銅粉の少ないB層が半導体素子の熱膨張
係数に近い熱膨張係数を有している。このようにして形
成した焼結体を切削加工して図2に示す形状のヒートシ
ンクに形成し、これを別途形成してあるパッケージ本体
20にろう付けしてパッケージに形成した。ヒートシン
ク22上に半導体素子23を搭載し、半導体装置に完成
した。ヒートシンク22に反りは見られず、また各部に
クラックの発生などもなかった。The above-mentioned sintered metal having a one-piece structure and partially different in coefficient of thermal expansion was manufactured as follows. As shown in FIG. 3, powder molding plates A layer, C layer, and B layer having different ratios of copper powder and tungsten powder were laminated and sintered to be integrated. A: 85:15 W: Cu, C: 9
It is a powder molded plate which is compressed into a plate shape by adjusting the layer B at 0:10 and 95: 5. By laminating and sintering in this way, the interfaces between them were also bound to form a sintered metal having an integral structure. In this way, by forming powder molding plates with different mixing ratios in advance, and stacking and sintering this,
Although there was some migration of the metal between the layers, a sintered metal was obtained in which the original ratio was maintained and the compounding ratio was gradually changed on the front and back surfaces. The thermal expansion coefficient of the A layer having a large amount of copper powder has a thermal expansion coefficient close to that of the ceramic package body 20, and the thermal expansion coefficient of the B layer having a small amount of copper powder close to that of the semiconductor element. have. The sintered body thus formed was cut to form a heat sink having the shape shown in FIG. 2, and this was brazed to the separately formed package body 20 to form a package. The semiconductor element 23 is mounted on the heat sink 22 to complete a semiconductor device. No warp was found in the heat sink 22 and no crack was generated in each part.
【0010】上記の実施例では配合割合のことなる粉末
成形板を3層にして焼結したが、配合割合が段階的に異
なる4層以上の多層にした方がさらに良好な結果が得ら
れた。また上記実施例ではW−Cu系のものを示した
が、W−Mo系のものも同様の結果が得られた。またW
−Ni−Cu系のものも良好であった。この場合半導体
素子搭載部は必要な熱膨張係数に調整するため、W−C
u系のものにした。In the above-mentioned examples, the powder molding plates having different compounding ratios were sintered into three layers. However, better results were obtained by using four or more layers having different compounding ratios in stages. . Further, although the W-Cu type is shown in the above-mentioned examples, similar results were obtained also with the W-Mo type. See also W
The -Ni-Cu system was also good. In this case, since the semiconductor element mounting part is adjusted to the required coefficient of thermal expansion, WC
I made it u type.
【0011】上記の実施例ではパッケージ本体に貫通孔
を有するタイプのものを示したが、図4に示すように、
ヒートシンク22がパッケージ本体20の素子収納孔上
にろう付けされるタイプのものであってもよい。また本
実施例ではPGA(ピングリッドアレイ)タイプで説明
したが、PGA以外のヒートシンクを有するセラミック
パッケージに広く適用できることはもちろんである。In the above-mentioned embodiment, the type having the through hole in the package body is shown, but as shown in FIG.
The heat sink 22 may be of a type that is brazed onto the element housing hole of the package body 20. Although the PGA (pin grid array) type is described in this embodiment, it is needless to say that the present invention can be widely applied to a ceramic package having a heat sink other than PGA.
【0012】[0012]
【発明の効果】本発明に係る半導体装置用セラミックパ
ッケージによれば、ヒートシンクに、表裏で熱膨張係数
が異なる一体の焼結金属であって、パッケージ本体への
接合部の熱膨張係数がパッケージ本体のセラミックと同
程度の熱膨張係数を有し、半導体素子搭載部の熱膨張係
数が半導体素子と同程度の熱膨張係数を有するものを用
いたので、ヒートシンクに反りが生じず、搭載される半
導体素子に悪影響を与えないパッケージを提供できる。According to the ceramic package for a semiconductor device of the present invention, the heat sink is an integral sintered metal having different thermal expansion coefficients on the front and back sides, and the thermal expansion coefficient of the joint portion to the package body is the package body. Since the one having a thermal expansion coefficient similar to that of the above-mentioned ceramics and the thermal expansion coefficient of the semiconductor element mounting portion similar to that of the semiconductor element is used, the heat sink does not warp and the mounted semiconductor is mounted. A package that does not adversely affect the device can be provided.
【図1】本発明に係る半導体装置用セラミックパッケー
ジの一例を示す断面図である。FIG. 1 is a cross-sectional view showing an example of a semiconductor device ceramic package according to the present invention.
【図2】そのヒートシンクの断面図である。FIG. 2 is a sectional view of the heat sink.
【図3】ヒートシンクの製造例を示す断面図である。FIG. 3 is a cross-sectional view showing a manufacturing example of a heat sink.
【図4】他の実施例を示す断面図である。FIG. 4 is a sectional view showing another embodiment.
【図5】従来の半導体装置用パッケージの一例を示す断
面図である。FIG. 5 is a cross-sectional view showing an example of a conventional semiconductor device package.
20 パッケージ本体 21 ピン 22 ヒートシンク 23 半導体素子 20 Package Body 21 Pin 22 Heat Sink 23 Semiconductor Element
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/373 9355−4M H01L 23/12 F 23/36 M Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/373 9355-4M H01L 23/12 F 23/36 M
Claims (2)
のヒートシンクが接合され、該ヒートシンク上に半導体
素子を搭載するようにした半導体装置用セラミックパッ
ケージにおいて、 前記ヒートシンクは一体に焼結して形成され、パッケー
ジ本体との接合部と半導体素子の搭載部とでは熱膨張係
数が異なり、パッケージ本体との接合部の熱膨張係数が
パッケージ本体と同程度の熱膨張係数を有し、半導体素
子搭載部の熱膨張係数が搭載する半導体素子と同程度の
熱膨張係数を有することを特徴とする半導体装置用セラ
ミックパッケージ。1. A ceramic package for a semiconductor device, wherein a metal heat sink is joined to a ceramic package body, and a semiconductor element is mounted on the heat sink, wherein the heat sink is formed by integrally sintering. The coefficient of thermal expansion differs between the junction with the package body and the mounting area of the semiconductor element, and the thermal expansion coefficient of the junction with the package body is about the same as that of the package body. A ceramic package for a semiconductor device, which has a thermal expansion coefficient similar to that of a mounted semiconductor element.
の接合部がCu−W、Cu−MoまたはCu−Ni−W
系の焼結金属でCuの含有量が10〜15%であり、半導体
素子搭載部がCuの含有量が0 〜10%のW−Cu系また
はCuの含有量が0〜10%のMo−Cu系の焼結金属
であることを特徴とする請求項1記載の半導体装置用セ
ラミックパッケージ。2. The heat sink has a Cu-W, Cu-Mo or Cu-Ni-W joint portion with a package body.
System sintered metal with a Cu content of 10 to 15%, and the semiconductor element mounting portion has a Cu content of 0 to 10% W-Cu system or a Cu content of 0 to 10% Mo-. The ceramic package for a semiconductor device according to claim 1, wherein the ceramic package is a Cu-based sintered metal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5181393A JPH06268099A (en) | 1993-03-12 | 1993-03-12 | Ceramic package for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5181393A JPH06268099A (en) | 1993-03-12 | 1993-03-12 | Ceramic package for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06268099A true JPH06268099A (en) | 1994-09-22 |
Family
ID=12897356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5181393A Pending JPH06268099A (en) | 1993-03-12 | 1993-03-12 | Ceramic package for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06268099A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003007940A (en) * | 2001-06-25 | 2003-01-10 | Kyocera Corp | Heat radiation member and package for housing semiconductor element |
JP2003007891A (en) * | 2001-06-26 | 2003-01-10 | Kyocera Corp | Package for storing semiconductor element |
JP2008041910A (en) * | 2006-08-04 | 2008-02-21 | Ngk Spark Plug Co Ltd | Wiring substrate and multicavity wiring substrate |
JP2016200432A (en) * | 2015-04-08 | 2016-12-01 | 株式会社デンソー | Semiconductor device |
-
1993
- 1993-03-12 JP JP5181393A patent/JPH06268099A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003007940A (en) * | 2001-06-25 | 2003-01-10 | Kyocera Corp | Heat radiation member and package for housing semiconductor element |
JP4574071B2 (en) * | 2001-06-25 | 2010-11-04 | 京セラ株式会社 | Package for housing heat dissipation member and semiconductor element |
JP2003007891A (en) * | 2001-06-26 | 2003-01-10 | Kyocera Corp | Package for storing semiconductor element |
JP4548978B2 (en) * | 2001-06-26 | 2010-09-22 | 京セラ株式会社 | Package for storing semiconductor elements |
JP2008041910A (en) * | 2006-08-04 | 2008-02-21 | Ngk Spark Plug Co Ltd | Wiring substrate and multicavity wiring substrate |
JP2016200432A (en) * | 2015-04-08 | 2016-12-01 | 株式会社デンソー | Semiconductor device |
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