JPH06261205A - Picture element density converter of plain paper facsimile - Google Patents

Abstract

PURPOSE:To reduce the capacity of a page memory and to smoothen the contour of a character and a graphic by transferring the interpolation image data of the interpolation line generated by a picture element density conversion circuit in addition to image data transferred from the page memory to a printer unit. CONSTITUTION:The image data ak of the line >=0 of a line memory 31 is transferred as 3-bit image data an an-1, an-2 to an interpolation logic circuit 36 via a shift register 37. The image data (a) of the line #1 is transferred as 3-bit image data am, am-1, am-2 to the circuit 36 via a shift register 29. The circuit 36 generates the interpolation image data ap (it becomes full-white data.) of an interpolation line LP from 6-bit image data an, an-1, an-2, am, am-1, am-2 in accordance with an interpolation logic. The data ap is transferred as image data ax to a printer unit 13 via an AND gate 42 and an OR gate 44. A CPU defines an enable signal (b) as a logical high level, closes AND gates 30 and 42, opens an AND gate 43 and stops the transfer of image data a from a page memory 1 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel density conversion device for a plain paper facsimile.

[0002]

2. Description of the Related Art Conventionally, in a plain paper facsimile,
A printer interface is provided between the facsimile main body and the printer unit, and image data from the facsimile main body is temporarily stored in the page memory of the printer interface, read out, and transferred to the printer unit.

FIG. 2 is a block diagram of a conventional plain paper facsimile. In the figure, reference numeral 11 denotes a facsimile main body, and the facsimile main body 11 is composed of an original reading unit, a modulation / demodulation circuit, a communication line control circuit, etc., which are not shown. Further, reference numeral 12 is a printer interface, and the printer interface 12 acts as an intermediary between the facsimile main body 11 and the printer unit 13.

FIG. 3 is a block diagram of a conventional printer interface. In the figure, reference numeral 12 is a printer interface, and the printer interface 12 is a command interface 15 for controlling commands and responses with the facsimile main body 11 and the facsimile main body 1.
Image data input unit 1 for controlling input of image data a from 1
6, a page memory 17 that temporarily stores the input image data a, a memory control unit 19 that controls input / output of the page memory 17, and an image data output unit 20 that outputs the image data a to the printer unit 13. , And the command interface 15 and the memory control unit 19
It is formed by the CPU 21 that controls the above.

In the case of printing with the plain paper facsimile having the above-mentioned structure, when the image data a generated by communication, reading an original, etc. is transferred from the facsimile main body 11 to the image data input section 16 of the printer interface 12, the CPU 21 transfers the data. Page data 1
Write to 7. On the other hand, when the facsimile main body 11 transfers a certain amount of the image data a, the command interface 1
A print start command is output to the device 5. As a result, the CPU 21 reads the image data a from the page memory 17 and transfers it to the printer unit 13.

That is, the printer interface 12 mainly writes and reads the image data a to and from the page memory 17.

[0007]

However, in the conventional plain paper facsimile, the printer interface 12 directly outputs the input image data a one-to-one without performing image processing. , The capacity of the page memory 17 is determined by the pixel density and the print area, and conversely, the achievable pixel density and the maximum print area are determined by the capacity of the page memory 17.

Therefore, when printing is performed using the image data a having a low pixel density, the outline of the character or figure becomes a step. Therefore, it is conceivable that a smoothing process is performed to smooth the outline of a character or a figure, and printing is performed with a high pixel density.
It becomes necessary to perform density conversion of the image data in advance and transfer it to the printer interface 12.

However, if the pixel density is increased, it is necessary to increase the capacity of the page memory 17, which increases the cost of the plain paper facsimile. The present invention solves the problems of the conventional plain paper facsimile and needs to increase the pixel density and increase the page memory capacity inside the printer interface when transferring image data from the printer interface to the printer unit. It is an object of the present invention to provide a pixel density conversion device for a plain paper facsimile capable of smoothing the contours of characters and figures without the above.

[0010]

Therefore, in the pixel density conversion apparatus for a plain paper facsimile of the present invention, a facsimile main body, a page memory for temporarily storing image data transferred from the facsimile main body, and A pixel density that receives the image data transferred from the page memory, generates the interpolation image data of the interpolation line based on the image data of at least two lines, and outputs the image data and the interpolation image data to the printer unit. It has a conversion circuit.

Then, the frequency of the transfer clock for transferring the image data from the page memory to the pixel density conversion circuit is made higher than the frequency of the transfer clock for transferring the image data from the facsimile body to the page memory.

[0012]

According to the present invention, as described above, in the pixel density conversion device for the plain paper facsimile, the facsimile main body, the page memory for temporarily storing the image data transferred from the facsimile main body, and the page memory. Receives the image data transferred from, and generates the interpolation image data of the interpolation line based on the image data of at least two lines,
It has a pixel density conversion circuit for outputting the image data and the interpolated image data to the printer unit.

Therefore, in addition to the image data transferred from the page memory, the interpolation image data of the interpolation line generated by the pixel density conversion circuit is transferred to the printer unit, so that the pixel density in the sub-scanning direction is increased. You can In that case, the frequency of the transfer clock for transferring the image data from the page memory to the pixel density conversion circuit is made higher than the frequency of the transfer clock for transferring the image data from the facsimile body to the page memory. Therefore, it is possible to print a plurality of lines in the conventional one-line printing cycle.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a block diagram of a pixel density conversion device for a plain paper facsimile showing an embodiment of the present invention, FIG. 4 is a block diagram of a printer interface to which the embodiment of the present invention is applied, and FIG. 5 is an enable in the embodiment of the present invention. Time charts of signals and transfer clocks, and FIG. 6 is a diagram for explaining the operation of the interpolation logic circuit in the embodiment of the present invention.

In FIG. 4, reference numeral 12 is a printer interface, and the printer interface 12 is a command interface 15 for controlling commands and responses with the facsimile main body 11 and the facsimile main body 11.
Image data input unit 1 for controlling input of image data a from
6, a page memory 17 that temporarily stores the input image data a, a memory control unit 19 that controls input / output of the page memory 17, an image data output unit 20 that outputs the image data a, and an image data output unit It is formed by a pixel density conversion circuit 25 that receives the image data a from 20 and converts the pixel density and outputs the pixel density to the printer unit 13, and a CPU 21 that controls the command interface 15, the memory control unit 19, and the like.

When printing, when the image data a generated by communication, reading an original, or the like is transferred from the facsimile main body 11 to the image data input unit 16 of the printer interface 12, the CPU 21 transfers the transferred image data a to a page. Write to memory 17. On the other hand, the facsimile main body 11 outputs a print start command to the command interface 15 when the image data a is transferred by a certain amount. As a result, the CPU 21 reads out the image data a from the page memory 17, performs image processing in the pixel density conversion circuit 25, and then transfers it to the printer unit 13.

Next, the pixel density conversion circuit 25 will be described. In FIG. 1, reference numeral 25 is a pixel density conversion circuit, which is arranged between the image data output section 20 and the printer unit 13 and performs pixel density conversion as image processing. In this case, the reading and transfer of the image data a from the page memory 17 is performed only in the section where the enable signal b is at the logic low level. A transfer clock generation circuit 28 is provided, and the page memory 1
A transfer clock c for transferring the image data a from 7 to the pixel density conversion circuit 25 is generated. The frequency of the transfer clock c is from the facsimile main body 11 to the page memory 1
7 is twice the frequency of the transfer clock for transferring the image data a.

Further, as shown in FIG. 5, the page memory 1
The transfer time t _a for transferring the image data a from 7 to the pixel density conversion circuit 25 is the transfer time t _b for transferring the image data a from the facsimile main body 11 to the page memory 17.
It will be half of that. The image data a from the image data output unit 20 is input to the shift register 29 and the line memory 31 via the AND gate 30. An enable signal b is also input to the AND gate 30 via an inverter 32,
Writing of the image data a into the line memory 31 is controlled by the state of the enable signal b.

[0019] The shift register 29 is the current image data a _m,該画data a _m pixels before 1 bit pixel d _m corresponding to the d _m-1 of the image data a _m-1 and 2-bit pixels before d
generates image data a _m-2 of the _m-2, and outputs them against interpolation (smoothing) the logic circuit 36. On the other hand, the line memory 31 outputs the image data a _k of the line one line before (hereinafter referred to as “previous line”) L _{n to} the shift register 37, and the shift register 37 outputs the current image data a _k . image data a _n pixels d _n of the previous line L _n in the same position in the pixel d _m in the main scanning direction of _m, the image data a _n-1 of said 1 bit before the pixel d _n pixels d _n-1 and It generates two bits before the pixel d _n-2 of the image data a _n-2, and outputs them against interpolation logic circuit 36.

In FIG. 6, L _m is the current line, L _n
Is a previous line, L _p is an interpolation line interpolated by the interpolation logic circuit 36 (FIG. 4), d _m is a pixel corresponding to the current image data a _m , and d _m-1 is a pixel one bit before the pixel d _m , D
2 bits before the pixels of _m-2 pixel d _m, the pixel of the previous line L _n is d _n in the same position in the main scanning direction and the pixel d _m,
1 bit before the pixels d _n-1 pixel d _n, d _n-2 is the pixel d
It is a pixel 2 bits before _n . Further, d _p is an interpolation pixel generated by the interpolation logic circuit 36.

In the interpolation logic circuit 36,
If the interpolation logic by the bullying algorithm is set,
6 image data a by interpolation logic_m, A_m-1，
a_m-2, A _n, A_n-1, A_n-2Interpolated image data based on
a_pIs generated. And the interpolation
Interpolated image data a generated by the logic circuit 36_pas well as
Image data a from the shift register 37_n-1Is the switching circuit 4
0 depending on the state of the enable signal b
Either one is selected and the image data a_xAs printer
It is output to the unit 13.

Therefore, the switching circuit 40 includes an inverter 41 that inverts the enable signal b, an AND gate 42 that receives the output of the inverter 41 and the interpolated image data a _p , the enable signal b and the image data a.
_The AND gate 43 receives _n-1 as an input, and the output of the AND gate 42 and the OR gate 44 receives the output of the AND gate 43.

Next, the pixel density variation in the embodiment of the present invention will be described.
The operation of the conversion circuit 25 will be described. FIG. 7 illustrates the present invention.
An example of a plain paper facsimile pixel density conversion device
It is an im chart. First, the line before printing
Clear memory 31 (Fig. 1) and print only white pixels
All white data and enable signal b is logically
It is a level. In this state, the facsimile main body 11 (Fig.
The command interface 15 sends a print start command from 4).
When receiving, the CPU 21 outputs the enable signal b to the logic low level.
Open the AND gates 30 and 42 as a bell and
The pixel density conversion circuit 25 is closed by this.
The image data a of IN # 1 is received. At this time, the line memory
31 is the image data a of line # 0_kOutput (all white data)
On the other hand, the image data a of line # 1 is input.
By this operation, the image data a of the line memory 31 _kIs in order
The image data a of the next line # 1 is rewritten. line#
Image data 0_kVia the shift register 37
Image data a_n, A_n-1, A_n-2As interpolation logic times
It is transferred to the road 36.

On the other hand, the image data a on the line # 1 is transmitted through the shift register 29 to the 3-bit image data a _m ,
It is transferred to the interpolation logic circuit 36 as a _m-1 and a _m-2 .
The interpolation logic circuit 36 uses the 6-bit image data a _n , a _n-1 , a _n-2 , a _m , a _m-1 , a _m-2 to interpolate image data a of the interpolation line L _P according to the interpolation logic. Generate _P (here, all white data). Generated interpolation image data a
_P is transferred to the printer unit 13 as image data a _x via the AND gate 42 and the OR gate 44.

Next, the CPU 21 sets the enable signal b to a logic high level, closes the AND gates 30 and 42, opens the AND gate 43, and stops the transfer of the image data a from the page memory 17. At this time, the image data a _k of the line # 1 is output from the line memory 31 and new image data a is not written. The output image data a _k of the line # 1 is output from the shift register 37 as image data a _n , a _n-1 , and a _n-2 , but the position of the interpolation image data a _P in the main scanning direction is adjusted. Therefore, the image data a _n-1 is transferred to the printer unit 13 as the image data a _x via the AND gate 43 and the OR gate 44. While the enable signal b is at the logic high level, the interpolation logic circuit 36 generates unnecessary line image data as the interpolation image data a _P , but it is discarded because the AND gate 42 is closed.

Further, the enable signal b is set to a logical low level to receive the image data a of the line # 2 from the image data output unit 20, and the interpolated image data a _P is generated from the image data a of the lines # 1 and # 2. Transfer to the printer unit 13. Thereafter, the printing of one page is completed in the same manner. In the image data a _x output to the printer unit 13, the transfer clock c has a frequency twice as high as the transfer clock in the conventional printer interface 12, and the pixel density in the sub-scanning direction doubles. Two lines can be printed in the conventional one line printing cycle. Therefore, the printing time for one page is the same as that of the conventional plain paper facsimile.

FIG. 8 is a diagram showing a dot matrix before pixel density conversion in the embodiment of the present invention, and FIG. 9 is a diagram showing a dot matrix after pixel density conversion in the embodiment of the present invention. As shown in the figure, the interpolation line L _p has an interpolation pixel d _p generated by the interpolation logic circuit 36 (FIG. 1).
Is printed.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention, and they are not excluded from the scope of the present invention.

[0029]

As described above in detail, according to the present invention, in the pixel density conversion device for the plain paper facsimile, the page for temporarily storing the facsimile main body and the image data transferred from the facsimile main body. The memory and the image data transferred from the page memory are received, the interpolation image data of the interpolation line is generated based on the image data of at least two lines, and the image data and the interpolation image data are sent to the printer unit. It has an output pixel density conversion circuit.

Therefore, in addition to the image data transferred from the page memory, the interpolation image data of the interpolation line generated by the pixel density conversion circuit is transferred to the printer unit, so that the pixel density in the sub-scanning direction is increased. This makes it possible to smooth the contours of characters and figures.
Moreover, since only the image data transferred from the facsimile main body is stored in the page memory, the processing of the facsimile main body is not complicated, the capacity of the page memory can be reduced, and the cost can be reduced. it can.

The frequency of the transfer clock for transferring the image data from the page memory to the pixel density conversion circuit is made higher than the frequency of the transfer clock for transferring the image data from the facsimile body to the page memory. Therefore, a plurality of lines can be printed in the conventional one-line printing cycle, and the printing time does not become long.

[Brief description of drawings]

FIG. 1 is a block diagram of a pixel density conversion device for a plain paper facsimile showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional plain paper facsimile.

FIG. 3 is a block diagram of a conventional printer interface.

FIG. 4 is a block diagram of a printer interface to which an embodiment of the present invention is applied.

FIG. 5 is a time chart of an enable signal and a transfer clock in the embodiment of the invention.

FIG. 6 is a diagram for explaining the operation of the interpolation logic circuit in the embodiment of the present invention.

FIG. 7 is a time chart of a pixel density conversion device for a plain paper facsimile showing an embodiment of the present invention.

FIG. 8 is a diagram showing a dot matrix before pixel density conversion according to the embodiment of the present invention.

FIG. 9 is a diagram showing a dot matrix after pixel density conversion according to the embodiment of the present invention.

[Explanation of symbols]

11 Facsimile main body 13 Printer unit 17 Page memory 25 Pixel density conversion circuit a Image data a _P Interpolation image data c Transfer clock L _P Interpolation line

Claims (1)

[Claims] 1. A facsimile main body, (b) a page memory for temporarily storing image data transferred from the facsimile main body, and (c) image data transferred from the page memory,
A pixel density conversion circuit that generates interpolation image data of an interpolation line based on image data of at least two lines and outputs the image data and the interpolation image data to a printer unit; (d) from the page memory A plain paper facsimile pixel characterized in that the frequency of the transfer clock for transferring the image data to the pixel density conversion circuit is made higher than the frequency of the transfer clock for transferring the image data from the facsimile body to the page memory. Density converter.