JPH05124263A - Recording device - Google Patents

Abstract

PURPOSE:To simplify a structure of interpolation processing and reduce the cost of a device. CONSTITUTION:A printer controller 1 sends out an image data 8 with resolution of 300 dpi in horizontal and vertical scans synchronizing with a clock 22. A memory 2 receives the image data 8 and stores the image data for 7 lines of the vertical scan, and outputs a signal 9 of 7 bits to a window 3. At the window 3, each image data of 7 bits is developed to 7 bits of the horizontal scan so as to constitute a window of 49 bits in total, which is sent to an input/ output switch 23. When the input/output switch 23 switches the data in accordance with selection signal so as to send it to a smoothing section 4, an interpolation processing is performed at the smoothing section 4 where the number of logic gates is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording apparatus which outputs binary image data by smoothing or interpolating input image data.

[0002]

2. Description of the Related Art In recent years, in printing output by a printer or the like, a higher resolution and a higher gradation have been advanced due to the progress of a printing mechanism. Therefore, in accordance with these advances, it is necessary to increase the capacity of the memory for storing the image. However, the current situation is that the cost reduction of the memory cannot compensate for the increase in the capacity corresponding to the printing mechanism. Therefore, in order to fill the gap of an image image with a small memory and the printing mechanism capable of high-quality output, conventionally, a method of performing processing such as interpolation of the image image to bring out the performance of the printing mechanism has been devised. .. Then, in this type of interpolation processing, the gradation of the pixel of interest is determined based on the pixel information around the pixel of interest in order to generate the gradation of one pixel. Hereinafter, a general example will be described.

FIG. 9 is a block diagram showing the structure of a conventional recording apparatus. In the figure, the printer controller 1
Sends image data (8) having a resolution of 300 dpi in both main scanning and sub scanning in synchronization with the clock (22). Then, the memory unit 2 receives the image data (8), stores the image data for the sub-scanning 7 lines, and stores the image data in the window unit 3.
The bit signal (9) is output. In this window section 3, each 7-bit image data is expanded to 7 bits in the main scanning to form a window of 49 bits in total, which is sent to the smoothing section 4.

The smoothing section 4 receives the 49-bit data (10) from the window section 3, performs smoothing based on the logical expression shown in FIG. 10, and outputs 4-bit data as a result. The selector 5 selects an optimum signal from these four signals a (11), b (12), c (13), d (14), and 600 dp for both main scanning and sub scanning.
The image data (15) of i is output, and the printer engine unit 6 prints it. Note that FIG. 11 shows the relationship between the 300 dpi original image data and the interpolated 600 dpi image data.

As a result of the above-mentioned processing, the unprocessed image data shown in FIG. 12 (a) is improved after the processing, as shown in FIG. 12 (b). In FIG. 9, the device control circuit 7 is a circuit that controls the entire apparatus, and sends a plurality of signals to each block described above.

[0006]

However, the above-mentioned conventional recording apparatus performs interpolation processing in order to convert one pixel into four pixels and convert the image data of the original pixel 300 dpi into the data of 600 dpi. At this time, for each of the four dots (pixels), a front-rear, left-right symmetric logical expression is required in the smoothing section. Therefore, many logic circuits are required, which is a factor that hinders the cost reduction of the entire recording apparatus.

[0007]

The present invention has been made for the purpose of solving the above-mentioned problems, and has the following structure as one means for solving the above-mentioned problems. That is, in a recording apparatus that interpolates input data and outputs it as binary data, means for storing bit information of input data including recording density information, and a plurality of bit information within a predetermined area of the bit information. Means for extracting
A switching means for selectively switching and outputting the extracted bit information according to a predetermined signal, and a recording density of the bit information output from the switching means, a recording density included in the bit information of the input data. And a conversion means for converting to a recording density exceeding the above. Preferably, the switching means performs switching in accordance with a clock synchronized with the bit information of the input data and a signal counting the horizontal synchronizing signal sent from the external device.

[0008]

With the above construction, the construction of the interpolation processing is simplified and the cost of the apparatus is reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of a recording apparatus according to an embodiment of the present invention. In addition,
In the recording apparatus shown in the figure, the same components as those of the conventional recording apparatus shown in FIG. 9 are designated by the same reference numerals, and the description thereof will be omitted, but the main difference between the present recording apparatus and the conventional recording apparatus. The point is that the input / output switching unit 23 is disposed between the window unit 3 and the smoothing unit 4 in this recording apparatus.

The recording apparatus according to this embodiment will be described in detail below. FIG. 2 is a circuit diagram showing a detailed configuration of the device control circuit 7. The device control circuit shown in FIG.
The horizontal synchronizing signal EBD (30) from the printer engine unit 6 (hereinafter referred to as the engine unit) is frequency-divided, and the horizontal synchronizing signal CBD (31) is sent to the printer controller 1 (hereinafter referred to as the controller). This is because the engine unit 6 is compatible with a print density of 600 dpi, whereas the controller 1 is compatible with a print density of 300 dpi, and here, the adjustment between the two is taken.

The device control circuit 7 includes a SRAM 43 and a 3-state buffer 4 in the memory unit 2 which will be described later.
4, latch 45, FIFO 46, address counter 47
Control signals (OE32, WE34), (LCT33, O
C35), (TOG36, HTESET37), VCL
Send K38a. FIG. 3 and FIG. 4 are time charts of the above signals, and the schematic operation thereof will be described here.

In FIG. 3, VRESET39, HRE
SET38 is a vertical synchronization signal VSYNC46,
The rising edge of the horizontal synchronizing signal EBD30 is cut out, the TOG 36 is a signal obtained by dividing the HRESET 38 by two, and the ODL 41 is a sub-scanning address signal that toggles each time the EBD 30 is input. Further, SCLK 38b and VCLK 38a in FIG.
The image clock of FIG. 2 and the clock of 1/2 thereof are obtained by dividing the system clock CLK42 generated by the oscillation unit 100 of FIG. 2 by 4 and 8 respectively. And OE32, LCT33, WE34, OC
35 are times t1 to t3, t2 to t6, and t of the eight states defined during one cycle of VCLK38.
True during the states of 4 to t6 and t4 to t7
Is the signal. These signals are sent to the memory unit 2, the window unit 3, and the input / output switching unit 23, respectively.

FIG. 5 is a diagram showing a detailed circuit configuration of the memory section 2. In the figure, a horizontal synchronizing signal CBD31 is taken out from a controller (not shown), and a clock CCLK is output.
The 300 dpi image data VDO8 sent in synchronism with No. 22 is written to the FIFO 46 at the clock. The FIFO 46 is composed of two buffers each having a storage capacity for storing one line or more of 300 dpi image data, and the TOG signal 36 alternately switches between the read mode and the write mode.

Here, while data is being written in one of the two buffers, the VCL from the other buffer is written.
Data is read at the timing of K38. HTES
Since the ET signal 37 is connected to the reset terminal of the address counter inside the FIFO 46, the address counter of the FIFO is reset twice while the data from the controller is being written. Therefore, since the same data is read twice, the print density of the image data in the sub-scanning direction becomes 600 dpi when it is output from the FIFO.

The VCLK 38 is connected to the clock terminal of the address counter 47 composed of four 16-bit synchronous counters, and the address signal of the SRAM 43 (total 13 bits).
Signals). The image data output from the FIFO 46 is stored in the SRAM 43 for 7 lines. FIG. 4 shows the time chart at that time. FIF
The image data output from O46 is input to one input terminal of the D latch 45 having an 8-bit configuration, and the D latch 45
It is latched at time t2 by the LCT 33 connected to the clock terminal of. Similarly, the output signal OE32 from the data input / output terminals D1 to D6 of the SRAM 43 is tr.
During the time t1 to t3 when it becomes ue, the data is output and is latched by the D latch 45 at the time t2. In addition, SRAM
The data input / output terminals D1 to D6 of 43 are also connected to the output terminals Y1 to Y6 of the 3-state buffer 44, but are connected to the gate terminals of the 3-state buffer 44 during times t1 to t4. Since the OC signal 35 is false, the 3-state buffer is in a high impedance state, and data collision does not occur.

At time t3, the OE signal 32 is false.
Then, the data bus of the SRAM 43 enters the floating state. Further, at time t4, the OC signal 35 and the SRA
The WE signal 34, which is the write signal of M43, becomes true, the image data LINEO from the FIFO latched by the D latch 45 is sent to the D1 terminal of the SRAM 43, and the output image data from the D1 terminal is sent to the D2 terminal.
It is written in the SRAM 43 at the falling edge of the WE signal.

In this way, the image data for several lines can be stored by performing the operation of reading the data of a certain address of the SRAM 43 and writing the new data to the same address within one cycle of VCLK38. it can. Further, the same line data is read twice from the FIFO 46 during one cycle of the horizontal synchronizing signal CBD 31, but only the latter half of the line data is written to the SRAM 43. Then, the stored 7 lines of data are sent to the window unit 3.

FIG. 6 is a block diagram showing the internal structure of the window section 3. As shown in the figure, the window section 3 is composed of seven shift registers, and is expanded into seven main scanning lines to output 49-bit data. Then, these 49-bit data are sent to the input / output switching unit 23. FIG. 7 is a block diagram showing the internal configuration of the input / output switching unit 23. As shown in the figure, this circuit includes 36 4-TO-1 selectors 48 to 83 and 12 2-T selectors.
It is composed of O-1 selectors 84 to 95. A0, G0, A6, G6 are input to the selectors 48 to 51,
Switching is performed according to the logical values of VCLK and ODL which are select signals.

For example, both VCLK and ODL are logic "H".
In case of, selector 48, selector 49, selector 5
0, A0 and G from the output end of the selector 51, respectively.
When 0, A6, G6 are output and both VCLK and ODL are logic "L", the selector 48, the selector 49, the selector 50, and the selector 51 respectively output G6, A6, G.
0 and A0 are output. When VCLK is logic "H", the output of the selector 90 is A3 and the output of the selector 91 is G3. When VCLK is logic "L", the output of the selector 90 is G3 and the output of the selector 91 is A3. ..

As described above, the group of image data of four or two pixels located point-symmetrically with respect to the pixel of interest (corresponding to the pixel D4 in FIG. 11) is the value of VCLK and ODL which are select signals. The output is switched and output to the smoothing unit 4. This smoothing unit 4 is composed only of the logic for generating the output of a in FIG. 11, and the logic for generating b, c, d is a symmetrical form of that of a, and the logic of 49
It becomes unnecessary by switching the bit data between VCLK and ODL. The data thus smoothed is sent to the engine unit and printed.

As described above, according to this embodiment,
At the time of interpolation processing for pixel density conversion, by paying attention to the symmetry of the conversion logical expression with respect to the peripheral pixel that is in a front-back and left-right symmetrical positional relationship with the target pixel, by switching the image data input to the smoothing unit, The number of logic gates in the smoothing section can be reduced, and the cost of the device can be reduced.

In the above embodiment, smoothing was performed assuming characters and images, but as shown in FIG.
A selector 5 is provided between the smoothing unit 4 and the engine unit 6 and either the smoothing is selected by the selector 5 or the image data SD3 of 600 dpi simply quadrupled is selected in accordance with the instruction signal 16 from the controller 1. You may do so. By doing so, it is possible to prevent the print sample from being adversely affected when the dither image or the like is sent. The present invention may be applied to a system including a plurality of devices or an apparatus including a single device.

[0023]

As described above, according to the present invention,
By switching and inputting image data to the interpolation processing unit for input data, the number of logic gates in the interpolation processing unit can be reduced, and as a result, the cost of the device can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a recording apparatus according to an embodiment of the present invention,

FIG. 2 is a diagram showing a detailed configuration of a device control circuit in the embodiment,

[Figure 3]

FIG. 4 is an operation timing chart of a device control circuit,

FIG. 5 is a diagram showing a detailed circuit configuration of a memory unit in the embodiment;

FIG. 6 is a block diagram showing the internal structure of the window section in the embodiment.

FIG. 7 is a block diagram showing the internal configuration of the input / output switching unit in the embodiment.

FIG. 8 is a block diagram showing a configuration of a recording apparatus according to a modified example of the embodiment.

FIG. 9 is a block diagram showing the configuration of a conventional recording device,

FIG. 10 is a logical expression when smoothing is performed in a conventional recording device,

FIG. 11 is a diagram showing a relationship between original image data and image data after interpolation in a conventional recording apparatus,

FIG. 12 is a diagram showing a smoothing effect in a conventional recording apparatus.

[Explanation of symbols]

 1 Printer Controller 2 Memory Section 3 Window Section 4 Smoothing Section 6 Printer Engine Section 7 Device Control Circuit 22 Input / Output Switching Section 43 SRAM 44 3 State Buffer 45 D Flip Flop 46 FIFO 47 Address Counter 48-83 4-TO-1 Selector 84 ~ 95 2-TO-1 selector

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location // G09G 5/36 8121-5G (72) Inventor Takashi Kawana 3-30-2 Shimomaruko, Ota-ku, Tokyo Kya Non non corporation

Claims (3)

[Claims] 1. An interpolation process is applied to input data to obtain 2
In a recording device for outputting as value data, a unit for storing bit information of input data including recording density information, a unit for extracting a plurality of bit information within a predetermined area of the bit information, and the extracted bit information. Switching means for selectively switching and outputting according to a predetermined signal, and a recording density of the bit information output from the switching means,
A recording device, comprising: a conversion unit that converts the recording density to a recording density exceeding the recording density included in the bit information of the input data. 2. The switching means performs switching in accordance with a clock synchronized with the bit information of the input data and a signal counting the horizontal synchronizing signal sent from an external device. The recording device according to 1. 3. The recording apparatus according to claim 1, further comprising means for switching the output from the conversion means in response to an instruction signal sent from an external device. Recording device.