JPH06261028A - Clock distribution system for synchronization communications equipment - Google Patents

Abstract

PURPOSE:To reduce the scale of hardware of an equipment common section by directly applying a clock from a network synchronization device from a clock reception section to plural distributed sections. CONSTITUTION:Two clock reception sections 100, 110 adopt a redundant configuration and receive a clock from a network synchronization device to provide an output after applying a predetermined processing to the clock. Plural clock distributed sections 300-1, 300-2 select either of the clocks received from the clock reception sections 100, 110 to generate a clock required for communication processing. Then the clock generated by clock distributed sections 300-1 to 300-n is distributed to a circuit in each clock distributed section. The clock from the network synchronization device is directly applied to the clock distributed sections 300-1 to 300-n to reduce the scale of the hardware of the equipment common section and number of wiring for the clock to each of the clock distributed sections 300-1 to 300-n is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a clock distribution system for a communication device or the like in a synchronous network.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional synchronous communication apparatus. FIG. 6 is a configuration diagram of a clock receiving unit and a clock generating / distributing unit of a conventional example.

FIG. 7 is a block diagram of a clock receiving / generating unit (hereinafter referred to as CREC & GEN) in a conventional clock distributed package (hereinafter referred to as clock distributed PKG). In FIG. 5, the synchronous communication device comprises a device common part and clock distributed PKG3-1 to 3-n. The device common part consists of clock receivers (CREC) 1-1 and 1-2 and clock generators / distributors (GEN & DIS) 2-1 and 2-2.
It has a 1-system redundant configuration. Clock receiver 1-1, 1-
2 receives the clock sent from the network synchronizer (DCS, not shown).

The clock generation / distribution units 2-1 and 2-2 are clock generation units that generate clocks necessary for generating a clock in the apparatus by the clocks input from the clock reception units 1-1 and 1-2. And a distribution unit that creates various clocks from the clocks generated by the clock generation unit and distributes them to each unit of the device. Also, clock distributed PKG3-1 to 3-
n is equipped with CREC & GEN4.

In FIG. 6, a clock receiver (CREC) 1-
1 and 1-2 are bipolar / unipolar converters (hereinafter B
/ U) 5 from DCS (not shown) to 64
Input a KHz bipolar clock and an 8KHz bipolar clock that is bit violated every 8KHz, convert it to a unipolar clock, and add the output to a bipolar violence detection unit (hereinafter referred to as BV DET) 6 and a 64KHz It outputs a unipolar clock and adds it to the clock generator / distributor (GEN & DIS) 2-1 and 2-2.
The clock loss detector 7 detects a clock loss.

The BV DET 6 detects the bipolar violation portion and outputs it as an 8 KHz unipolar clock, which is added to the clock generation / distribution units 2-1 and 2-2. still,
In the selection unit (hereinafter referred to as SEL) 8, the output clock of the resonance circuit (TANK) 11 of the 0-system clock generation / distribution unit 2-1 described later and the 0-system clock generation / distribution unit 2- 1
When the failure occurs, the output clock of the resonance circuit (TANK) 11 of the 1-system clock generation / distribution unit 2-2 is selected by the control signal and added to the BV DET 6 as the timing clock.

In the clock generation / distribution units 2-1, 2-2, S
In EL9, usually from 0 system clock receiver 1-1,
When the system clock receiver 1-1 fails, the 8 KHz clock input from the system 1 clock receiver 1-2 is selected by the control signal and output. Similarly, SEL10 selects and outputs a 64 KHz clock. By passing the output clock of SEL10 to the resonance circuit (TANK) 11, the output of 64KH
The output frequency is kept stable even if the z clock fluctuates by several bits.

The output of the resonance circuit 11 is applied to a phase locked loop (hereinafter referred to as PLL) 13 to output a clock of a predetermined frequency that is phase-locked with the input clock. On the other hand, the frequency divider 12
The output clock of the resonance circuit 11 is divided into, for example, 1/8,
A pulse generator (hereinafter referred to as PG) 14 divides the output clock of the PLL 13 into an arbitrary frequency according to the output timing of the frequency dividing circuit 12 and outputs the frequency. The output clock of PG14 is distributed by a distribution circuit (DIS) 15 to a plurality of clock distribution target PKG3-1 to 3-n.

Next, the clock distributed PKG3-1 to 3-n will be described with reference to FIG. Clock distributed P shown in FIG.
In CREC & GEN4 in KG3-1 to 3-n, clock type 1 sent from 0-system clock generation / distribution unit 2-1
~ N clocks CLK1 (0) to CLKn (0) and clock types 1 to n sent from the 1-system clock generation / distribution unit 2-2
Clocks CLK1 (1) to CLKn (1) of SEL16-1
~ Input to SEL16-n.

Normally, the above-mentioned clock generation / distribution unit 2-1
, 2-2 from CONT22 via control signal (ACT
(0) and ACT (1)) select and output the 0-system clock in SEL16-1 to SEL16-n, and selectively output the 1-system clock when the 0-system fails. This output clock is set to PLL17 and P
The frequency is divided only through G18 or PG18 and supplied to other circuits in this PKG.

Further, when the clock input from the 0-system or 1-system clock generation / distribution section 2-1 or 2-2 is interrupted, the interruption detection section 19-1 to 19-n or 20-1 to 20-n detects this. Detect the OR circuit
Alarm (ALM (0) or ALM (2) via 21-1 or 21-2
Output as (1)).

[0012]

In the conventional clock distribution system described above, if the type or quantity of clocks required in the device increases, the hardware scale of the clock generation / distribution unit increases, and the clock generation / distribution unit is increased. This may cause an increase in the number of PKGs equipped with this circuit. Further, when the number of clocks distributed to each clock distributed PKG increases, the clock distributed PKG is distributed from the clock generation / distribution unit.
There is also a problem that the number of clock wirings to the circuit is increased, and the layout of the clock wirings becomes difficult.

Further, although the clock distribution system of the common part of the device has a redundant configuration, the phases of the output clocks of the 0-system and 1-system PLLs are usually set when the clock generator / distributor is forcibly switched due to maintenance or the like. There is a problem that a momentary interruption occurs in communication data due to the deviation.

Further, even in the switching of the clock generation / distribution unit due to the clock break in the clock generation / distribution unit or the clock distribution PKG, the clock distribution is performed until the clock disconnection is detected and the switching of the clock generation / distribution unit is completed. Since the data processing unit (not shown) of the PKG is in the clock disconnected state, there is a problem that the communication data is instantaneously interrupted.

Therefore, according to the present invention, the hardware scale of the clock distribution unit of the apparatus common unit can be reduced and the number of clock wirings can be reduced, and even when the apparatus common unit is switched, the synchronization for preventing the instantaneous interruption of the data in the clock distributed PKG. An object of the present invention is to provide a clock distribution system for a communication device.

[0016]

The above problems can be solved by the structure of the apparatus shown in FIG. In FIG. 1, (Claim 1) 100 and 110 are two clock receiving units which have a redundant configuration and receive a clock from the network synchronizer, perform a predetermined process, and output.

300-1 to 300-n select one of the clocks input from the two clock receivers,
It is a plurality of clock distributed parts that create clocks necessary for communication processing.

Then, the clocks created by the plurality of clock distributed parts are distributed to the circuits in the plurality of clock distributed parts. (Claim 2) The plurality of clock distributed parts (300-1 to 30)
0-n) is a resonance circuit 290 that passes the resonance component of the clock selected from the clocks input from the two clock receiving units (100, 110), and the output frequency of the resonance circuit as it is or at a predetermined frequency. And a frequency conversion circuit 320 that outputs the converted signal.

[0019]

In FIG. 1, the clocks from the network synchronizer are transferred from the clock receiving units 100 and 110 to a plurality of clock distributed units 30.
By directly adding to 0-1 to 300-n, the hardware scale of the common part of the device can be reduced and the number of clock wiring to each clock distributed part 300-1 to 300-n can be reduced. it can.

Further, a plurality of clock distributed parts 300-1 to 300-n
Since the resonance circuit 290 is installed in the
This resonant circuit can absorb the clock fluctuation that occurs when either 00 or 110 is switched to the other, and the instantaneous interruption of data in the plurality of clock distributed units 300-1 to 300-n can be prevented. It becomes possible to prevent it.

[0021]

FIG. 2 is a block diagram of a synchronous communication device according to an embodiment of the present invention. FIG. 3 is a configuration diagram of CREC & GEN in the clock receiving unit and the clock distributed PKG of the embodiment.

FIG. 4 is a diagram for explaining a data transfer method between PKGs according to the present invention. As shown in FIG. 2, the present invention is different from the conventional example, as shown in FIG.
Clocks (usually 8KHz and 64KHz) received from 1'-1 and 1'-2 from the network synchronizer (DCS) are directly distributed from CREC1'-1 and 1'-2 to each clock distribution PKG3'-1 ~ Each PK in the device that was distributed to 3'-n and performed by the clock generation / distribution unit of the conventional device common unit
This is because each clock distributed PKG 3'-1 to 3'-n has a function of generating various clocks (timing pulse, etc.) used in G. The details will be described below.

In FIG. 3, clock receiving sections 1'-1, 1'-2 are shown.
In B / U5, from DCS (not shown)
The point that a 64 KHz bipolar clock and an 8 KHz bipolar clock that is bit-violated every 8 KHz are input, converted into a unipolar clock and the output is added to the BV DET 6 is the same as described in the conventional example. This B
V DET6 detects the bipolar violation part and outputs it as a 8 KHz unipolar clock, and in addition to the distribution circuit (DIS) 25, the DIS 25 generates a plurality of 8 KHz clocks to distribute the clock PKG3'-1 to 3 ' Output to -n.

In addition, the 64 KHz unipolar clock output of the B / U 5 described above is passed through the delay circuit 26 to the BV DET described above.
7 as a timing clock and DIS
In addition to 27, the DIS 27 generates a plurality of 64 KHz clocks and outputs the clocks to the clock distributed PKGs 3'-1 to 3'-n.

Next, each clock distributed PKG 3'-1 to 3'-n
CREC & GEN 4'in the SEL16-1, 8KHz input from 0's and 1's clock receivers 1'-1 and 1'-2
Of the clocks, the 0-system is normally selected, and the 1-system is selected and outputted by the control signal from the CONT 22 'when the 0-system clock receiver 1'-1 fails. For the 64KHz clock input from the 0-system and 1-system clock receivers 1'-1 and 1'-2, similarly, the SEL16-2 is normally the 0-system, and the 0-system is the 1-system when a failure occurs. Select and output.

Next, the 64 KHz output clock of the SEL 16-2 is passed through the resonance circuit (TANK) 29 to keep the output frequency stable even if the 64 KHz clock fluctuates by several bits. The output of the resonance circuit 29 is applied to the PLL 30, and a clock having a predetermined frequency that is phase-synchronized with the input clock is output. On the other hand, the frequency of the output clock of the resonance circuit 29 is divided into 1 / N by the frequency dividing circuit 31, and the output clock of the PLL 30 is frequency-divided or multiplied by the output timing of the frequency dividing circuit 31 by the PG 32. And output.

Among the input clocks to the clock-distributed PKGs 3'-1 to 3'-n, the disconnection detecting unit 19-1 or 19 when the 0 system is disconnected.
-2, and in case of disconnection of 1 system, detected by 20-1 or 20-2, OR
An alarm is output via the circuit 21-1 or 21-2 and added to the CONT 28 of the 0-system and 1-system clock receivers 1'-1 and 1'-2, respectively. In CONT28 of 0 system and 1 system, these disconnection signals and B
The logical sum of the input disconnection signals to / U5 is taken and sent to the above-mentioned CONT22 'as a switching control signal due to the clock disconnection.

Next, a method of passing data between clock distributed PKGs will be described with reference to FIG. This figure shows a case where each clock distributed PKG has a redundant configuration of PKGs for 0 system and 1 system. In the same figure, for example, clock distributed PKGs 3'-M for 0 system and 1 system are shown.
(0), 3'-M (1) to 0 system and 1 system clock distributed P
Data DATAm (0), DA for KG3'-N (0), 3'-N (1)
TAm (1) and clock CLKm for these data frames
01, CLKm11, and bit clocks CLKm02, CLKm12 shall be added.

Clock distributed PKGs 3'-N (0) and 3'-N
(1) In PG33-1, the above-mentioned 0-system frame clock CL
An enable signal for storing the data DATAm (0) in the memory 34-1 is generated from Km01 and the bit clock CLKm02, and the data m (0) is stored in the memory 34-1.
Similarly, for the 1-system, an enable signal for storing the data m (1) in the memory 34-2 is generated from the frame clock CLKm11 and the bit clock CLKm12 of the 1-system by the PG 33-2, and this data m ( 1) is stored in the memory 34-2.

This clock distributed PKG3'-N (0) and
CREC & GEN4 'in 3'-N (1) is the CREC & GEN in Fig. 3 described above.
This is the same as GEN4 ', and the data m (0) and m (1) are read from the memories 34-1 and 34-2 by the output clock of this CREC &GEN4'. And S
In EL35, normally, the 0-system is selected and the data m (0) is selected. When the 0-system clock system fails, the 1-system is selected and the data m (1) is added to the data processing unit 36.

In the data processing unit 36, the input data m (0) or the data m (1) is subjected to multiplexing processing or the like by the output clock of CREC &GEN3'-n, and the 0 system clock distributed PKG.
Data DATAn (0), frame clock CLKn01 and bit clock CLKn02 are output from 3'-N (0), and data DATAn from 1-system clock distributed PKG3'-N (1).
(1) Output the frame clock CLKn11 and the bit clock CLKn12.

As a result, the clock from the network synchronizer is distributed from the clock receiving unit 1'-1 or 1'-2 to a plurality of clock distributed P.
By directly adding to KG3'-1 to 3'-n, the hardware scale of the device common part can be reduced and the number of clock wiring to each clock distributed PKG3'-1 to 3'-n can be reduced. I can finish it.

A plurality of clock distributed PKGs 3'-1 to 3 '
-By providing the resonance circuit (TANK) 29 in CREC & GEN4 'in-n, the clock disconnection that occurs when either one of the clock receiver 1'-1 or 1'-2 is switched to the other This can be absorbed by the resonance circuit, and it becomes possible to prevent instantaneous interruption of data in a plurality of clock distributed PKG3'-1 to 3'-n.

[0034]

As described above, according to the present invention, since the clock distribution system in the device can be configured without providing the conventional clock generation / distribution unit in the device common unit, the hardware scale of the device common unit can be reduced. can do. Also, since the clocks required by each clock distributed unit 300-1 to 300-n are generated in each clock distributed unit, the number of clock wirings to each clock distributed unit is only the clock line received from the network synchronizer. Therefore, even if the type or number of clocks required in the device increases, it does not change.

Further, each clock distributed part 300-1 to 300-n
Since the resonance circuit 290 is provided in the
, Or 110, the clock fluctuation that occurs when one of them is switched to the other can be absorbed by this resonant circuit, and the instantaneous interruption of data in the plurality of clock distributed units 300-1 to 300-n can be prevented. It becomes possible.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention,

FIG. 2 is a configuration diagram of a synchronous communication device according to an embodiment of the present invention,

FIG. 3 is a block diagram of CREC & GEN in the clock receiving unit and clock distributed PKG of the embodiment,

FIG. 4 is a diagram for explaining a data transfer method between PKGs according to the present invention;

FIG. 5 is a block diagram of a conventional synchronous communication device,

FIG. 6 is a block diagram of a conventional clock receiving section and clock generating / distributing section;

FIG. 7 shows CREC & G in the clock distributed PKG of the conventional example.
It is a block diagram of EN.

[Explanation of symbols]

100 and 110 are clock receivers, 290 is a resonance circuit, and 300-1
~ 300-n is a clock distributed part, and 320 is a frequency conversion circuit.

Claims (2)

[Claims] 1. Two clock receiving units (100, 110) having a redundant configuration, receiving a clock from a network synchronization device, performing a predetermined process, and outputting, and inputting from the two clock receiving units. It has a plurality of clock distributed parts (300-1 to 300-n) for creating a clock required for communication processing by selecting any one of the generated clocks and created by the plurality of clock distributed parts. The clock distribution system of the synchronous communication device, wherein the clocks are distributed to the circuits in the plurality of clock distributed parts. 2. The plurality of clock distributed parts (300-1 to 30)
0-n) is a resonance circuit (290) that passes the resonance component of a clock selected from the clocks input from the two clock reception units (100, 110), and the output frequency of the resonance circuit as it is or 2. The clock distribution system for a synchronous communication device according to claim 1, further comprising a frequency conversion circuit (320) for converting to a predetermined frequency and outputting it.