JPH0625789U - Analog clock pointer correction circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Determine forward or reverse rotation depending on the position of the pointer and perform feed correction and return correction of the pointer, so that quick return and accurate return can be performed. . [Arrangement] Zero return detection circuit 110 for detecting the zero position of the pointer
Further, a distance discriminating circuit 100 for always detecting the pointer position is provided, and the distance discriminating circuit 10 is provided when the operation switch is operated.
A direction indicating circuit 80 that outputs a direction determining signal that determines the rotation direction of the motor based on the determination signal that is output by 0 is provided, and a zero-reset signal from when the operation switch is operated until the end signal is input. And the zero return circuit 50 that outputs the zero point and the detection signal output from the zero return detection circuit 110 when the pointer rotates forward and the distance determination circuit 10 when the pointer rotates in the reverse direction.
Zero return stop circuit 16 that uses a zero signal output by 0 as an end signal
0 is set.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a time correction mechanism for an analog timepiece, and more particularly to a pointer correction circuit that electronically resets the pointer to zero.

[0002]

[Prior art]

 Today, when correcting the display time of a clock, a digital clock counts the number of pulses of a reference signal by adding a high-frequency pulse signal for correction to a counter that counts the clock and switching the counter to up-count or down-count. There is a method in which the contents of the counter are changed to correct the display time when the contents of the counter are displayed via the recorder (for example, JP-A-57-133376 and JP-A-83-283491). Regarding the second display, the one that resets the second counter to zero by inputting a reset signal to the counter and resets the second display via the recorder to 00 seconds is used.

Further, even in an analog timepiece, the return position of the second hand or the minute hand is detected by using a photocoupler or the like as a position detecting means, and a correction signal of a high frequency pulse is supplied to a pointer driving motor. There is a device (for example, Japanese Examined Patent Publication No. 55-47834) that causes the second hand or the like to advance by adding the second hand or the minute hand to detect the zeroing of the second hand or the minute hand by the position detecting means and stop the correction signal.

[0004]

[Problems to be solved by the device]

 Analog clocks also require clocks with a correction mechanism that can quickly reset the second hand and minute hand to the hour position.However, analog clocks have a pointer driving motor to correct the displayed time. However, providing a separate correction motor complicates the mechanical structure, and in order to simplify the mechanical structure, a single motor is used for normal movement and zero return. If the pointer is moved forward or backward for quick zeroing, and the position of the pointer is detected using a position detector such as a photocoupler, the position detector has a detection width. Therefore, when the motor is operated at high speed as in the case of correction, a vibration occurs on the pointer, and the vibration of the pointer reduces the detection accuracy. There is a possibility that the deviation of Becomes accurately detected control child and is difficult to stop position of the pointer when the needle is zero-reset, disadvantages causing error there during the time table after zeroing.

[0005]

[Means for Solving the Problems]

 The present invention counts the number of pulses of a driving signal in an analog timepiece provided with a detection element for detecting the position of a pointer, determines whether the count is larger than a predetermined value, and outputs a determination signal, Further, a distance discrimination circuit that outputs a zero signal when the count number is 0, and a direction indicator circuit that outputs a direction determination signal based on the discrimination signal output from the distance discrimination circuit when the switch is operated, From the zero return instruction circuit that outputs the zero return signal when the switch is operated, and stops the output of the zero return signal when the end signal is input, and the reference signal generation circuit when the zero return signal is not input. Based on the drive signal, the gate drive circuit that passes the reference drive pulse signal of 1) as the drive signal and the correction pulse signal from the reference signal generation circuit when the zero return signal is input is used as the drive signal. Turn the motor And a display circuit for controlling the rotation direction of the motor based on the direction determination signal, and when the zero-return signal and the drive signal are input, the detection element is activated in synchronization with the drive signal to detect A zero-zero detection circuit that outputs a detection signal when the element detects the 0 position of the pointer, and passes the detection signal when the motor is in the normal rotation to be the end signal, and outputs a zero signal when the motor is in the reverse rotation. A zero-stop circuit that passes the signal and uses it as a termination signal is provided.

[0006]

[Work]

 The present invention has a zero return instruction circuit which outputs a zero return signal when the operation switch is operated, and the gate circuit corrects the frequency higher than the reference drive pulse signal when the zero return signal is input. Since the pulse signal is passed, the pointer can be corrected and rotated at high speed by the zero-return signal.

Since the zero-reset detection circuit outputs a detection command pulse synchronized with the drive signal when the zero-reset signal is input, after the pointer is corrected and moved by the drive signal, the detection element is moved after the movement. It is possible to detect whether or not the pointer has returned to the 0 position. Further, the distance discriminating circuit outputs a zero signal indicating the 0 position of the pointer and also outputs a discriminating signal indicating whether or not the value indicated by the pointer is larger than a predetermined value, and the direction indicating circuit outputs based on the discriminating signal. Since the direction determination signal is determined, when the value indicated by the pointer is less than a certain value, reverse correction is performed, and when the value indicated by the pointer is equal to or more than the certain value, forward correction is performed.

Further, since the zero-reset stop circuit uses either the detection signal or the zero signal as the end signal according to the direction determination signal, the zero-reset detection circuit detects the pointer only when the rotation direction of the pointer is one direction. It is possible to detect the resetting of the pointer to zero by the distance discriminating circuit during correction rotation in the opposite direction.

[0009]

【Example】

 As shown in FIG. 1, the embodiment of the timepiece having the pointer correction circuit for performing the zero-reset operation according to the present invention outputs the reference signal φ4 from the reference signal generating circuit 10 which outputs a plurality of reference signals having different frequencies. The reference drive pulse signal is used, and the φ4 reference signal is output as the drive signal from the gate circuit 70 to the I signal, the drive signal is input to the display circuit 90, and the display circuit 90 references the motor 98. A timepiece that advances a pointer by rotating it at a constant speed based on a drive pulse signal, and a switch circuit 20 having two operation switches, a first operation switch for reverse rotation and a second operation switch for forward rotation, When an H level signal is output to the A signal or B signal output from the switch circuit 20, the operation detection signal is output to the C signal, and the hold signal is output during the operation detection signal is being output. Output to E signal and update When the reverse rotation signal output to the A signal or the normal rotation signal output to the B signal is extremely short, a switch detection circuit 30 that outputs the operation detection pulse signal to the D signal is provided, and the operation detection pulse signal is input. And a zero-return instruction circuit 50 for outputting a zero-return signal. The φ3 reference signal from the reference signal generation circuit 10 is inputted to the gate circuit 70 as a correction pulse signal and is passed through the correction instruction circuit 60. A distance discriminating circuit 100 to which the zero return signal and the direction determination signal which are correction signals are input, and a zero return detection circuit 110 to which the zero return signal and the drive signal are input are provided, and the pointer is at the position of 0 second. It is also possible to incorporate a detection element such as a photocoupler for detecting the fact at a predetermined position.

The reference signal generation circuit 10 divides the output signal of the oscillation circuit 12 by the first frequency divider 12 to generate a φ1 reference signal, a φ2 reference signal, and a φ3 reference signal from the reference signal generation circuit 10. The output of the first frequency divider 14 is further divided by the second frequency divider 16 to output a reference signal φ4 of 1 Hz. As shown in FIG. 2, the switch circuit 20 is formed by providing two sets of operation switches and chattering prevention circuits in series. One end of the first operation switch 22 is a power source and the other end is a resistor. Is connected to the direction indicator circuit 80 and the switch detection circuit 30 via the first chattering prevention circuit 26, and similarly, one end of the second operation switch 24 is used as a power source and the other end is connected via a resistor. It is connected to the direction indicating circuit 80 and the switch detecting circuit 30 via the second chattering prevention circuit 28 while being grounded.

Therefore, the switch circuit 20 outputs the H level reverse rotation signal to the A signal when the first operation switch 22 is operated, and outputs the H level normal rotation signal to the B signal when the second operation switch 24 is operated. It will output a signal. The switch detection circuit 30 is composed of one D flip-flop, an OR circuit, two pulse counters, and three AND circuits. The switch circuit 20 includes a first chattering prevention circuit 26 and a second chattering prevention circuit. The output terminal of the circuit 28 is connected to the clock input terminal of the first D flip-flop 34 through the first OR circuit 32, the D input terminal of the first D flip-flop 34 is used as the power supply, and the Q output terminal is used for the first AND circuit 36. To the φ input terminal of the first pulse counter 38, and the output terminal of the first OR circuit 32 is the clock input terminal of the first D flip-flop 34, the reset terminal of the second pulse counter 48, and the third input terminal. It is connected to one input terminal of the AND circuit 42, and is connected to the reset terminal and the zero return terminal of the second frequency divider 16 in the reference signal generation circuit 10. Also connected to the 示回 path 50.

Furthermore, the Qn output terminal of the second pulse counter 48 is connected to the negative input terminal of the second AND circuit 46 and the reset terminal of the first pulse counter 38, and the first frequency divider in the reference signal generation circuit 10 is connected. The φ 2 reference signal output terminal from 14 is connected to each input terminal of the first AND circuit 36 and the second AND circuit 46, and the output terminal of the second AND circuit 46 is connected to the φ input terminal of the second pulse counter 48. .

Further, the Qm output terminal of the first pulse counter 38 is connected to the input terminal of the third AND circuit 42 and the reset terminal of the first D flip-flop 34, and the output of the third AND circuit 42 is used as an operation detection signal. Further, the output terminal of the third AND circuit 42 is connected to the correction instruction circuit 60, and the Qm output terminal of the first pulse counter 38 is connected to the zero return instruction circuit 50 to make the Qm output the operation detection pulse signal.

Therefore, in the switch detection circuit 30, when the H-level reverse signal is output to the A signal or the H-level normal rotation signal is output to the B signal, the first D flip-flop 34 sets the Q output to the H level, The first pulse counter 38 counts the φ2 reference signal and outputs an H level signal to Qm. The H level Qm signal resets the first D flip-flop 34, and the first AND circuit 36 closes to output Qm. Is maintained at the H level.

When the reverse rotation signal or the normal rotation signal is continuously output from the switch circuit 20, the H level signal output from Qm of the second pulse counter 48 passes through the third AND circuit 42. The C signal output from the switch detection circuit 30 is output as an H level operation detection signal, and the reverse rotation signal or the normal rotation signal is shorter than the set time defined by Qm of the first pulse counter 38. When it is output for a short period of time, after the Qm output of the first pulse counter 38 becomes H level, the Qn output of the second pulse counter 48 which started counting from the output stop of the reverse rotation signal or the forward rotation signal is at H level. Then, the first pulse counter 38 is reset, and the Qm output of the first pulse counter 38 continues until the Qn output of the second pulse counter 48 is output. Is pulsed.

When the Qm output of the first pulse counter 38 is pulsed, the output of the first OR circuit 32 becomes L level by stopping the output of the forward rotation signal or the reverse rotation signal and the third AND circuit 42. Therefore, the operation detection signal for the C signal is not output, and the operation detection pulse signal for the H pulse is output for the D signal from the switch detection circuit 30. As described above, the switch detection circuit 30 has the operation switch longer than the set time of the first pulse counter 38 when either the first operation switch 22 or the second operation switch 24 in the switch circuit 20 is operated. When pressed, it outputs the H-level operation detection signal to the C signal for the operation time of the operation switch, and outputs it to the D signal as the operation detection pulse signal when the operation time of the operation switch is momentarily shorter than the set time. However, the two operation switches in the switch circuit 20 are used as a reverse rotation switch and a forward rotation switch, and can also be used as a zero return switch.

As shown in FIG. 3, the zero-reset instruction circuit 50 to which the operation detection pulse signal is input is composed of one D flip-flop and an OR circuit, and the first pulse in the switch detection circuit 30. The Qm output terminal of the counter 38 is the clock input terminal of the second D flip-flop 52, and the D input terminal of the second D flip-flop 52 is the inverted output of Q in the second D flip-flop 52 (hereinafter referred to as -Q output) terminal. The Q output terminal of the second D flip-flop 52 is connected to the gate circuit 70 via the third OR circuit 62 as the correction instruction circuit 60 so that the Q output of the second D flip-flop 52 becomes a zero return signal. It is connected to the direction indicating circuit 80, the zero return detection circuit 110, and the zero return stop circuit 160 described above.

Further, the output terminal of the first OR circuit 32 in the switch detection circuit 30 is connected to the reset terminal of the second D flip-flop 52 via the second OR circuit 54 in the zero-return instruction circuit 50, and the second The other input terminal of the OR circuit 54 is connected to a zero return stop circuit 160 described later so that the second D flip-flop 52 can be reset by an end signal.

Therefore, the zero-resetting instruction circuit 50 outputs the E signal which is the output of the first OR circuit 32 when the first operation switch 22 or the second operation switch 24 is in the ON state for a long time. Although the reset state is maintained by the H-level hold signal, the operation switch is turned off when the first operation switch 22 or the second operation switch 24 is turned on for a short time. After the output of the negative signal is stopped, the Q output of the second D flip-flop 52 is set to H level by the operation detection pulse signal output from the first pulse counter 38, and the zero return signal is output.

The other input terminal of the third OR circuit which is the correction instruction circuit 60 is connected to the output terminal of the third AND circuit 42 in the switch detection circuit 30, and the correction instruction circuit 60 is connected to the switch detection circuit 30. The operation detection signal output by the controller and the zero return signal output by the zero return instruction circuit 50 are passed and sent to the gate circuit 70 and the direction instruction circuit 80 as a correction signal.

The gate circuit 70 to which the correction signal such as the zero-reset signal is input is composed of two AND circuits and one OR, and the output terminal of the third OR circuit 62 which is the correction instruction circuit 60. The child is connected to the negative input terminal of the sixth AND circuit 72 and the normal input terminal of the seventh AND circuit 74, and the other input terminal of the sixth AND circuit 72 is connected to the φ4 reference signal output terminal of the reference signal generation circuit 10. , The other input terminal of the seventh AND circuit 74 is connected to the φ3 reference signal output terminal of the reference signal generation circuit 10, and the output terminal of the sixth AND circuit 72 and the output terminal of the seventh AND circuit 74 are connected to the sixth OR circuit. It is connected to the input terminal of 76 and the output terminal of the sixth OR circuit 76 is connected to a display circuit 90, a distance determining circuit 100 and a zero-reset detecting circuit 110 described later.

Therefore, if the φ4 reference signal is used as a reference drive pulse signal of 1 Hz and the φ3 reference signal is used as a correction pulse signal of several Hertz, when a correction signal such as a zero return signal is not input from the switch detection circuit 30, When the sixth AND circuit 72 opens and the reference drive pulse signal is output as the drive signal to the I signal which is the output of the gate circuit 70, and the correction pulse signal is input when the correction signal such as the zero return signal is input. The signal is output to the I signal after passing through the 7 AND circuit 74, and the frequency of the drive signal is increased when the correction signal is input.

The direction indicating circuit 80 is composed of two AND circuits and an OR circuit, and one RS flip-flop, an inverter and a pulse generator, and is included in the comparator 104 in the distance discriminating circuit 100 described later. The output terminal is connected to the input terminal of the fourth AND circuit 81 and the negative input terminal of the fifth AND circuit 82, and the Q output terminal of the 2D flip-flop 52 in the zero return instruction circuit 50 is connected to the fourth AND circuit. 81 and the other input terminal of the fifth AND circuit 82, and the output terminal of the fourth AND circuit 81 is connected to the set end of the RS flip-flop 85 via the fourth OR circuit 83. The output terminal of the fifth AND circuit 82 is connected to the reset terminal of the RS flip-flop 85 via the fifth OR circuit 84, and the other input terminal of the fourth OR circuit 83 is switched. In the output circuit of the first chattering prevention circuit 26 in the H circuit 20, the fifth OR circuit 84 uses a three-input type OR circuit and the output terminal of the pulse generator 87 and the second chattering prevention circuit 28 in the switch circuit 20. The output terminal of the pulse generator 87 is connected to the output terminal of the third OR circuit 62 which is the correction instruction circuit 60 through the inverter 86, and the -Q output terminal of the RS flip-flop 85 is connected. Is connected to a display circuit 90 and a distance determination circuit 100 described later.

Therefore, the direction designating circuit 80 normally outputs the H level direction determining signal to the J signal which is the -Q output of the RS flip-flop 85, but the first operating switch 22 or the second operating switch 24 Is turned on for a short period of time, and the H level reverse signal is output to the A signal for a short period of time, or the H level normal rotation signal is output to the B signal for a short period of time, the reverse rotation signal or the normal rotation signal is stopped. Immediately after that, the zero return signal based on the operation detection pulse signal output from the switch detection circuit 30 opens the fourth AND circuit 81 and the fifth AND circuit 82, and the determination signal from the distance determination circuit 100 is at the H level or the L level. Accordingly, the RS flip-flop 85 is set or reset, and the direction determination signal is set to H level or L level.

Since the forward rotation signal and the reverse rotation signal from the switch circuit 20 are also directly input to the direction indicating circuit 80, when the H level reverse rotation signal is output to the A signal for a long time, or When the H level normal rotation signal is output to the B signal for a long time, the H level or the reverse rotation signal is output based on the normal rotation signal or the reverse rotation signal in accordance with the operation in which the switch detection circuit 30 outputs the operation detection signal to the C signal. An L level direction determination signal can be output.

As shown in FIG. 4, the display circuit 90 is composed of a shift register 92 and a motor drive circuit 94, and the φ input terminal of the shift register 92 is connected to the gate circuit 70. The output terminal of the 6-OR circuit 76 and the shift direction control terminal are connected to the -Q output terminal of the RS flip-flop 85 of the direction indicating circuit 80, and the output terminal of the shift register 92 is connected to the motor driving circuit 94. Since the connection is made, the shift direction of the shift register 92 can be inverted by the direction determining signal, and the phase of the drive control signal to the motor drive circuit 94 can be changed. The motor 98 is rotated by the motor driving circuit 94 in accordance with the frequency of the drive signal output to the I signal, and the rotation direction of the motor 98 is rotated normally or reversely depending on whether the direction determination signal is at the H level or not. It will be rolling.

Therefore, when the first operation switch 22 or the second operation switch 24 is turned on for a long time, the H level reverse rotation signal output to the A signal or the H level normal rotation output to the B signal is output. Based on the signal, the direction determination signal is determined to be at the H level or the L level to determine the rotation direction of the motor 98, and the operation detection signal output from the switch detection circuit 30 causes the gate circuit 70 to output the seventh AND signal. The circuit 74 is opened to send the correction pulse signal to the display circuit 90, and the rotation of the motor 98 can be sped up. When the first operation switch 22 is turned on for a long time, the pointer is quickly returned. It is also possible to perform reverse rotation correction and forward rotation correction in which the pointer is fast-forwarded when the second operation switch 24 is on for a long time, and the first operation switch 22 or the second operation switch 24 is turned on for a short time. In this state, the zero return signal output from the zero return instruction circuit 50 causes the gate circuit 70 to pass the correction pulse signal to speed up the rotation of the motor 98. The direction of rotation is the distance determination circuit. It is determined by the discrimination signal output by 100.

The distance discriminating circuit 100 used in this embodiment is composed of an up / down counter, a comparator, a 0 detection circuit, and an AND circuit, and the φ input terminal of the up / down counter 102 is a gate circuit. The output terminal of the sixth OR circuit 76 in 70, the up-down switching control terminal of the up-down counter 102 and one input terminal of the eighth AND circuit 108 are connected to the -Q output of the RS flip-flop 85 of the direction indicating circuit 80. The output terminal of the 8th AND circuit 108 is connected to the reset terminal of the up / down counter 102, and the Q output terminal of the up / down counter 102 is connected to the comparator 104 and the 0 detection circuit 106. The other input terminal of the eighth AND circuit 108 is connected to a zero return detection circuit 110 described later.

When the output value of the up / down counter 102 is less than 30, the comparator 104 outputs an H level determination signal as a K signal, and when the output value is 30 or more and 59 or less, an L level determination signal as a K signal. When the timepiece is set to output as a signal and the timepiece incorporating the pointer correction circuit has three hands, the up / down counter 102 increments the output count number by 1 every 1 second and carries it to 60, and the timepiece moves to 2 In the case of a needle, the output count number is incremented by 1 every 1 minute, and the carry is set to 60 for carrying.

Therefore, the distance discrimination circuit 100 outputs an H level discrimination signal when the minute hand indicates up to 29 minutes when the timepiece has two hands, and L when the minute hand indicates 30 minutes or more. A level discrimination signal is output, and in the case of a three-handed watch, similarly, a H level or L level discrimination signal is output depending on whether the second hand is less than 30 or more than 30, and when the count value is 0, the 0 detection circuit 106 The zero signal is output, and the up / down counter 102 is reset when the detection signal is output from the zero-reset detection circuit 110 when the direction determination signal is at the H level.

The zero-restoring detection circuit 110 is composed of a timing control circuit 115, a pulse counter circuit 120, a pulse output circuit 130, a detection element circuit 140, and a detection counter circuit 150. The negative input terminal of the circuit 117 is the output terminal of the sixth OR circuit 76 in the gate circuit 70, and the normal input terminal of the ninth AND circuit 117 is the Q output terminal of the second D flip-flop 52 in the zero return instruction circuit 50. Then, the output terminal of the ninth AND circuit 117 is connected to the reset terminal of the third pulse counter 124 in the pulse counter circuit 120 and the reset terminal of the fourth pulse counter 138 in the pulse output circuit 130.

The pulse counter circuit 120 is composed of an AND circuit and a pulse counter. One input terminal of the tenth AND circuit 122 is the φ1 reference signal output terminal of the first frequency divider 14 in the reference signal generation circuit 10. The other input terminal, the negative input terminal, is connected to the Qn output terminal of the third pulse counter 124, and the output terminal of the tenth AND circuit 122 is connected to the φ input terminal of the third pulse counter 124. The Qn output terminal is connected to the negative input terminal of the tenth AND circuit 122 and the clock input terminal of the third D flip-flop 132 in the pulse output circuit 130.

Therefore, the timing circuit 115 outputs a reset signal obtained by inverting the drive signal output by the gate circuit 70 when the zero return signal from the zero return instruction circuit 50 is output to the pulse counter circuit 120 and the pulse counter circuit 120. The pulse signal is output to the output circuit 130. In the pulse counter circuit 120, the reset signal resets the third pulse counter 124, and the third pulse counter 124 counts the φ1 reference signal in synchronization with the drive signal. The output of the H-level synchronizing signal to the O signal is repeated after a predetermined time elapses from the rising edge of.

The pulse output circuit 130 is formed by a D flip-flop, an AND circuit, an inverter, and a pulse counter, and the φ input terminal of the third D flip-flop 132 is connected to the Qn of the third pulse counter 124 as described above. While being connected to the output terminal, the D input terminal of the third D flip-flop 132 is used as a power source, the Q output terminal is used as an input terminal of the 11th AND circuit 134, and the reset terminal is used as a carry signal of the fourth pulse counter 138. The output terminal of the eleventh AND circuit 134 is connected to the switching transistor 146 in the detection element circuit 140 so that the detection element circuit 140 outputs a detection command pulse, and the second inverter 136 is connected. To the φ input terminal of the fourth pulse counter 138. The other input terminal of the eleventh AND circuit 134 is connected to the φ1 reference signal output terminal of the reference signal generation circuit 10, and the carry signal output terminal of the fourth pulse counter 138 is connected to the detection counter circuit 150. Is.

Therefore, when the synchronizing signal is input from the pulse counter circuit 120, the pulse output circuit 130 sets the Q output of the third D flip-flop 132 to the H level, opens the eleventh AND circuit 134, and outputs φ 1 reference from the pulse output circuit 130. The signal is output to the detection element circuit 140 as a detection command pulse, and when the required number of detection command pulses is counted by the fourth pulse counter 138, an H level regulation signal is output as a P signal from the carry signal output terminal. Then, the third D flip-flop 132 is reset, the detection command pulse output from the pulse output circuit 130 is stopped, and the H level regulation signal is output to the detection counter circuit 150.

Further, the detection counter circuit 150 has a plurality of D flip-flops in series, the clock input terminal of each D flip-flop is the output terminal of the detection element circuit 140, and the reset terminal of each D flip-flop is the pulse output circuit. Connected to the carry signal output terminal of the fourth pulse counter 138 in 130, the D input terminal of the first-stage D flip-flop 152 is used as a power source, and the Q output terminal of the final-stage D flip-flop 158 is used in the distance determination circuit 100. It is connected to the eighth AND circuit 108 and the zero return stopping circuit 160.

As a detection element in the detection element circuit 140, for example, an element such as a photocoupler is used, and when the second hand or the minute hand is located at the position of 0 second or 0 minute, the light of the light emitting diode 142 is used as a phototransistor. If it is arranged so that 144 receives light, the light emitting diode 142 blinks at high speed by the detection command pulse output from the zero-zero detection circuit 110, and this pulse signal is detected by receiving light by the phototransistor 144. The element circuit 140 sends a detection pulse to the detection counter circuit 150, and when the detection counter circuit 150 counts a required number of pulses, the detection counter circuit 150 sends the detection signal to the distance determination circuit 100 and the zero return stop circuit 160. It is something to send.

The zero-restoring circuit 160 is composed of one inverter and an OR circuit, and two three-input AND circuits, and as shown in FIG. 3, one input of the twelfth AND circuit 162. The terminal and one input terminal of the thirteenth AND circuit 164 are connected to the Q output terminal of the second D flip-flop 52 in the zero-restoring instruction circuit 50, and one input terminal of the twelfth AND circuit 162 is detected by the zero-restoring detection circuit. The input terminal of the 13th AND circuit 164 is connected to the Q output terminal of the final stage D flip-flop 158, which is the output terminal of the counter circuit 150, and the output terminal of the 0 detection circuit 106 in the distance determination circuit 100, and the 12th AND circuit is connected. The remaining input terminal of the circuit 162 is directly connected to the -Q output terminal of the RS flip-flop 85 in the direction indicating circuit 80, and the remaining input terminal of the thirteenth AND circuit 164 is directly connected to the third input terminal. The output terminal of the twelfth AND circuit 162 and the output terminal of the thirteenth AND circuit 164 are connected to the -Q output terminal of the RS flip-flop 85 via the inverter 166, and the zero return instruction circuit is provided via the eighth OR circuit 168. It is connected to the input terminal of the second OR circuit 54 in 50.

Therefore, the zero return stop circuit 160, when the zero return signal of H level is output from the zero return instruction circuit 50, the direction determination signal output to the J signal is at H level, that is, the needle is fast forwarded. When the motor 98 rotates in the direction indicated by the arrow, when the H-level detection signal is output from the zero-reset detection circuit 110 to the T signal, the output of the twelfth AND circuit 162 is set to the H level and the end signal is instructed to zero When the direction determination signal is sent to the circuit 50 and the motor 98 rotates in the direction of L level, that is, the direction in which the needle is reversed, when the distance determination circuit 100 outputs a zero signal of H level to the M signal, the 13th AND signal is output. The output of the circuit 164 is set to H level, an end signal is sent to the zero return instruction circuit 50, and the second D flip-flop 52 is reset to stop the output of the zero return signal.

Therefore, in this embodiment, when the first operation switch 22 in the switch circuit 20 is continuously turned on, the pointer is moved backward to correct the reverse rotation, and the second operation switch 24 is continuously turned on. The forward rotation correction that advances the pointer is possible, and when the first operation switch 22 or the second operation switch 24 is turned on for a time shorter than the set time set by the first pulse counter 38, the switch is detected. The operation detection pulse signal is output from the circuit 30, the zero return instruction circuit 50 outputs the zero return signal, and the zero return operation is started.

In the zero-return operation, the zero-return signal output from the zero-return instruction circuit 50 is input to the gate circuit 70 via the third OR circuit 62 in the correction instruction circuit 60, and the seventh AND circuit is provided. By opening 74, the correction pulse signal φ3 reference signal is sent to the display circuit 90 to speed up the rotation of the motor 98, and the zero return signal is input to the direction indicating circuit 80, thereby turning the direction indicating circuit. The fourth AND circuit 81 and the fifth AND circuit 82 in 80 are opened, and the RS flip-flop 85 is set or reset by the determination signal output from the distance determination circuit 100 to set the direction determination signal to the H level or the L level. The fourth AND circuit is used when the distance discrimination circuit 100 outputs the H level discrimination signal to the K signal, that is, when the second hand indicates up to 29 seconds. The output of 81 becomes the H level and the RS flip-flop 85 is set to the set state, and the direction indicating circuit 80 can output the direction determining signal of the L level to reverse the motor 98. When 100 is outputting the L level discrimination signal, that is, when the second hand is pointing from 30 seconds to 59 seconds, the direction designating circuit 80 outputs the H level direction determining signal to the J signal. The second hand can be rotated in the advancing direction, enabling quick zeroing.

When the second hand makes reverse rotation or forward rotation based on the φ3 reference signal which is the correction pulse signal as described above, the zero-reset detection circuit 110 makes the H pulse of the φ3 reference signal which is the drive signal. In synchronization with, the number of pulses of the φ1 reference signal set by the fourth pulse counter 138 in the pulse output circuit 130 is output as a detection command pulse during the H level of the φ3 reference signal, and the second hand sets 1 by the correction pulse signal φ3. The light emitting diode 142 in the detection element circuit 140 is caused to blink each time the step movement is performed based on the φ1 reference signal to detect the position of the second hand.

When the second hand returns to the 0 position, the phototransistor 144 in the detection element circuit 140 receives the blinking light of the light emitting diode 142, and the detection counter circuit 150 in the zero-reset detection circuit 110 detects the detection pulse. When the detection counter circuit 150 receives the required number of detection pulses, a detection signal is output from the zero return detection circuit 110, and the detection signal is sent to the distance determination circuit 100 and the zero return stop circuit 160. .

Further, by setting the count number of the detection pulse for the detection counter circuit 150 to output the detection signal to be smaller than the pulse number of the detection command pulse output from the pulse output circuit 130, the second hand Every time the pulse output circuit 130 outputs a regulation signal, the signal from the detection element circuit 140 is inspected, and the detection signal is output only when a plurality of pulses are input within a predetermined period. Therefore, the detection signal is prevented from being output due to a malfunction, and when the second hand is correctly returned to the 0 position, the detection signal is output and the switch detection circuit 30 and the like are returned to the normal state.

Further, in this embodiment, since the direction determination signal is input to the twelfth AND circuit 162 and the thirteenth AND circuit 164 via the third inverter 166 in the zero-rest stop circuit 160, the direction determination signal is determined. When the signal is at the H level, that is, when the forward rotation is corrected, the zero return of the pointer is detected by the detection element in the zero-reset detection circuit 110, and when the direction determination signal is at the L level, that is, when the reverse correction is performed, the distance determination is performed. When the count value of the up / down counter 102 in the circuit 100 becomes 0, the 0 detection circuit 106 detects and the pointer returns to zero. Therefore, the detection element always detects the pointer only when the pointer rotates from a certain direction. Therefore, the error due to the detection width of the detection element can be eliminated and the detection element can always be stopped at a fixed position. Since the down counter 102 counts the φ3 reference signal and φ4 reference signal that determine the rotation of the motor 98, it always has a numerical value corresponding to the time indicated by the pointer, and it can be reduced to 0 by correcting the pointer in the normal direction. When the count value of the up / down counter 102 becomes 0 during the zero return operation in the reverse rotation correction because the error is corrected by the zero reset by the detection signal output from the zero return detection circuit 110 when returning to the position. , The pointer is located in the position detected by the detection element when it rotates in the forward rotation direction, and it is the same whether the pointer is rotated in the forward rotation direction or in the reverse rotation direction as a zero return operation. It can be stopped at a position, which enables quick and accurate zeroing.

In the above-described embodiment, the zero return of the second hand is mainly described. However, when the zero return of the minute hand in the two-hand clock is performed, the output value of the up / down counter 102 is set as described above. If the minute hand indicates less than 30 minutes by counting 1 per minute or changing the threshold value of the comparator 104, return zero by return correction, and if 30 minutes or more are instructed, send zero. By carrying out the zero-reset by the correction, the quick and accurate zero-reset can be performed similarly to the above.

Further, in the above embodiment, the switch detection circuit 30 is provided in order to perform the zero return operation together with the feed correction and the return correction of the pointer by the two operation switches, but the zero return operation is performed. If a third operation switch is provided for this purpose, the output of the third operation switch should be an H pulse via the chattering prevention circuit and pulse generator, and the H pulse should be input to the zero-resetting instruction circuit. In this case, the second OR circuit 54 in the zero return instruction circuit 50 is omitted, and the end signal from the zero return stop circuit 160 is directly input to the reset terminal of the second D flip-flop 52, and By directly inputting the A signal and the B signal from the switch circuit 20 provided with the operation switch 22 and the second operation switch 24 to the third OR circuit 62 which is the correction instruction circuit 60, the switch is performed. The chi detection circuit 30 is removed.

[0048]

[Effect of device]

 The pointer correction circuit of the analog timepiece according to the present invention has a zero-reset circuit that outputs a zero-reset signal until an end signal is input, based on the operation detection pulse output when the operation switch is turned on. , The direction determination circuit outputs a direction determination signal of H level or L level based on the determination signal output by the distance determination circuit when the zero return circuit outputs the zero return signal. In (2), a discrimination signal that determines the direction of zeroing is output depending on whether or not a time exceeding 30 seconds is displayed, and in a 2-hand clock, the minute hand indicates whether or not a time exceeding 30 minutes is displayed. Therefore, it is possible to make a quick zero correction.

Further, the zero-reset detection circuit detects whether or not the pointer has returned to zero in synchronization with the drive signal and outputs a detection signal. Therefore, malfunction is prevented, and whether or not the pointer is correctly returned to zero is determined. It is possible to detect and control the zero return of the pointer. Further, since the zero-reset stop circuit uses the zero signal output from the distance determination circuit based on the direction determination signal or the detection signal output from the zero-reset detection circuit as the end signal, the pointer is detected by the detecting element depending on the rotation direction of the pointer. The position detection is enabled and the position of the pointer is always detected by the zero-reset detection circuit only when the direction of rotation of the pointer is constant. In the case of reverse rotation, the zero position of the pointer is detected by the distance determination circuit. By this, the stop position of the pointer can be prevented from shifting, the pointer can always be reset to the same position, and accurate zeroing can be performed to display the time without error.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a pointer correction circuit according to the present invention.

FIG. 2 is a diagram showing an embodiment of a reference signal generation circuit, a switch circuit, and a switch detection circuit of an analog timepiece according to the invention.

FIG. 3 is a diagram showing an embodiment of a correction instruction circuit, a zero return instruction circuit, a gate circuit, a direction instruction circuit, and a zero return stop circuit of an analog timepiece according to the invention.

FIG. 4 is a diagram showing an embodiment of a display circuit, a distance determination circuit, and a zero return detection circuit of an analog timepiece according to the invention.

[Explanation of symbols]

10 Reference Signal Generation Circuit 20 Switch Circuit 30 Switch Detection Circuit 80 Direction Indicator Circuit 70 Gate Circuit 90 Display Circuit 100 Distance Discrimination Circuit 110 Zero-Reset Detection Circuit 160 Zero-Reset Stop Circuit

Claims (1)

[Scope of utility model registration request] 1. A reference signal generating circuit for outputting reference pulse signals of different frequencies, wherein a drive signal, which is a reference pulse signal from the reference signal generating circuit, is counted to count the time and to be corrected by the display circuit. In an analog timepiece that drives a reversible or reversible motor to display time, the number of pulses of the drive signal is counted, and it is determined whether or not the number of counts is larger than a predetermined value and a determination signal is output. A distance determining circuit that outputs a zero signal when the count number is 0, a direction indicating circuit that outputs a direction determining signal based on the determining signal output from the distance determining circuit when the switch is operated, and a switch A zero return signal that outputs a zero return signal when is operated, and stops the output of the zero return signal when an end signal is input, and normally a reference drive pulse signal from a reference signal generation circuit. To drive the drive signal,
A gate circuit for receiving the correction pulse signal from the reference signal generation circuit as the drive signal when the zero-reset signal is input, and a motor for rotating the motor based on the drive signal, and a direction determining signal. Based on the display circuit for controlling the rotation direction of the motor, when the zero return signal is input and the drive signal is input, the detection element is operated in synchronization with the drive signal, and the detection element is at the 0 position of the pointer. A zero-reset detection circuit that outputs a detection signal when it detects, and when the direction determination signal causes the motor to rotate normally, the detection signal output from the zero-reset detection circuit is output as an end signal, and the direction determination signal is output. And a zero return stop circuit that outputs a zero signal output from the position discriminating circuit as an end signal when the motor is rotated in the reverse direction.