JPH06252755A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To stably operate the oscillation circuit and to allow the circuit to sufficiently cover a variable range of a low frequency oscillation output by reducing a frequency vibration width when a PLL loop is locked up in which a frequency division ratio of a PLL circuit is set to vary the oscillating frequency. CONSTITUTION:A 1st PLL circuit 1 and a 2nd PLL circuit 2 are provided and a reference signal is applied from a reference signal source 3 to phase comparators 1a, 2a of the 1st and 2nd PLL circuits 1, 2 and frequency division ratio data are fed to frequency dividers 1d, 2d from a frequency division ratio data controller 4 to allow 1st and 2nd VCOs 1c, 2c to oscillate different oscillating frequency signals based on a different frequency division ratio, the frequencies are varied in the same increasing/decreasing direction, a mixer circuit 5 mixes the different oscillating output signals to provide an output via an LPF 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit using a PLL synthesizer, and more particularly, to an oscillator circuit having a variable oscillation frequency.
The present invention relates to an oscillator circuit suitable for obtaining a low-frequency oscillation output signal with excellent amplitude characteristics from an LL synthesizer.

[0002]

2. Description of the Related Art Conventionally, many oscillation circuits for obtaining a variable low-frequency oscillation output signal using a PLL synthesizer have been provided in the block diagrams shown in FIGS. Figure 5
In the above, 10 is a PLL circuit, and this PLL circuit 10 is composed of a phase comparator 10a, a loop filter 10b, a voltage controlled oscillator (VCO) 10c, and a frequency divider 10d, as is well known. The reference signal is supplied from the reference signal source 3, and the error signal is supplied to the voltage controlled oscillator 10c via the loop filter 10b by phase comparison processing with the divided signal from the frequency divider 10d.

Reference numeral 11 denotes a frequency division ratio data controller. The frequency division ratio data from the frequency division ratio data controller 11 is applied to the frequency divider 10d.
To set the frequency division ratio of the frequency divider 10d. Reference numeral 5 is a mixer circuit, and 12 is a fixed oscillator. The mixer circuit 5 is supplied with the oscillation output signal of the PLL circuit 10 and the oscillation output signal from the fixed oscillator 12 for mixing processing, and a low pass filter 6 (hereinafter , Which is simply referred to as LPF6).

In the thus constructed oscillator circuit, the frequency of the PLL synthesizer system can be varied by setting the frequency division ratio of the frequency divider 10d of the PLL circuit 10 by the frequency division ratio data controller 11. That is, the oscillation output subjected to the phase comparison processing is output from the voltage controlled oscillator 10c of the PLL circuit 10 by the arbitrary division ratio data set by the division ratio data controller 11 and supplied to the mixer circuit 5.

On the other hand, the oscillation output signal from the fixed oscillator 12 is supplied to the mixer circuit 5, and is mixed with the oscillation output signal from the PLL synthesizer to extract the difference signal by the LPF 6. That is, since the LPF 6 is set to a frequency band in which only the difference signal between the PLL synthesizer oscillation output signal and the oscillation output signal of the fixed oscillator 12 is passed, the difference signal of the low frequency component of the mixed output mixed in the mixer circuit 5 is set. Was output from the output terminal 7.

As described above, an arbitrary low frequency signal is produced by the heterodyne system from the variable high frequency oscillation output of the PLL synthesizer system.

FIG. 6 is a block diagram showing another conventional example. In FIG. 6, the same parts as those of the conventional example of FIG. Reference numeral 13 is a fixed frequency divider, which supplies the high frequency oscillation output signal from the PLL synthesizer to the fixed frequency divider 13 and divides the low frequency oscillation output signal via the LPF 6 by a predetermined division ratio. It was output to the output terminal 7.

That is, the frequency divider 10d of the PLL circuit 10 is similar to the above.
Is set by the dividing ratio data controller 11 and the phase is compared, and the PLL synthesizer oscillation output signal that has voltage-controlled the voltage controlled oscillator 10c is set by performing the dividing process set by the fixed divider 13. It was possible to obtain a low frequency oscillation output signal.

In this way, the low frequency oscillation output signal of the PLL synthesizer system is obtained from the high frequency oscillation output signal of the PLL synthesizer system to form the low frequency oscillation circuit of the PLL synthesizer system.

[0010]

However, the conventional low-frequency oscillator circuit of the heterodyne type PLL synthesizer of FIG. 5 described above uses the PLL circuit 10 when the variable frequency is switched.
The lockup time of the loop becomes long, and the oscillation frequency oscillation width at the time of this lockup becomes large relative to the output frequency. Especially, when the oscillation output frequency is low frequency, the oscillation frequency oscillation width becomes large. It was Further, there is a drawback that a large overshoot of the amplitude characteristic of the oscillation frequency is output when the PLL loop is locked up as described above.

Further, in the oscillation circuit using the low frequency conversion system of the oscillation output signal by the fixed frequency divider 13 of FIG. 6, the variable range of the oscillation frequency is narrow in inverse proportion to the frequency division ratio of the fixed frequency divider 13. However, it is difficult to secure the frequency division ratio for obtaining the low frequency oscillation output and the variable range of the variable frequency in a balanced manner.

The present invention has been made in view of the above points, and an object of the present invention is to eliminate the drawbacks of the conventional example, and to perform a mixing process in a mixer circuit using two PLL circuits, thereby making a PLL loop. The present invention provides an oscillator circuit that reduces the frequency oscillation width until the lock-up operation is stabilized and sufficiently covers the variable range of the low-frequency oscillation output.

[0013]

An oscillator circuit according to the present invention includes first and second PLL synthesizers and the first and second PLL synthesizers.
A frequency division ratio data controller that sets a frequency division ratio of a frequency divider of the PLL synthesizer, and a mixer circuit that mixes the oscillation output signals of the first and second PLL synthesizers, and the frequency division ratio data. A configuration in which a low frequency oscillation output signal having a variable frequency is obtained from the mixer circuit by varying the oscillation frequencies of the first and second PLL synthesizers with different oscillation frequencies in the same direction by a controller. Is.

The reference signal for phase comparison of the first and second PLL synthesizers may be supplied from one reference signal source.

[0015]

According to the present invention, the PLL circuit composed of the phase comparator, the loop filter, the voltage controlled oscillator and the frequency divider has two components.
The frequency division ratio data controller supplies frequency division ratio data to the respective frequency dividers of the first PLL circuit and the second PLL circuit. The first and second PLLs are provided by providing a reference signal from a reference signal source.
Form a synthesizer.

The oscillation output signals of the first and second PLL synthesizers configured as described above are set by the frequency division ratio data supplied to the frequency divider, and the frequency division ratio data is variable. The oscillation frequency can be changed by.

That is, when the frequency division ratio data are different frequency division ratio data, the oscillation frequencies of the first and second PLL synthesizers can be oscillated at different frequencies, and the frequency division ratio can be increased. The variable step of the data can be changed at the different oscillation frequencies of the oscillation output signals of the first and second PLL synthesizers by the frequency division ratio data different between the first and second PLL synthesizers.

Further, by varying the variable direction of the frequency division ratio data in the same direction at different variable steps, the oscillation output signals of the first and second PLL synthesizers are also changed in frequency in different variable steps in the same direction. It can be changed.

As described above, the first Ps having different oscillation frequencies are
The oscillation frequency f ₁ of the LL synthesizer, by signal mixing process the output of the oscillation frequency f ₂ of the second PLL synthesizer is supplied to a mixer circuit, the output frequency f ₃ of the mixer circuit
Becomes an output frequency f ₃ = f ₁ −f ₂ via the LPF and becomes a low-frequency output signal of each frequency difference.

As described above, it is possible to output a low-frequency oscillation signal of the PLL synthesizer system, and moreover, it is possible to accurately secure the variable range and vary the frequency.

In this PLL synthesizer low frequency oscillation circuit, the frequency oscillation width and amplitude error such as overshoot of lock-up operation at the time of frequency switching of the PLL circuit are made the same as the constituent elements constituting the PLL circuit. Therefore, the oscillating frequencies f ₁ , f
The frequency oscillation error of ₂ can be canceled and the overshoot can be greatly reduced, and stable lock-up operation of the PLL circuit can be performed.

[0022] That is, a small value to an extent such as error and amplitude error a _n of error and damping factor ζ of the angular frequency ω of each of the oscillation output signal by the respective different frequency division ratios of the first and second PLL circuits are to be disregarded Therefore, the frequency oscillation width of the low-frequency oscillation signal obtained by the mixing process can be extremely reduced and reduced.

As described above, the stable lock-up operation can be performed, and at the same time, the variable range depending on the frequency division ratio of the oscillation frequency can be made sufficiently large, and the problems such as narrowing of the variable range as in the conventional example can be solved. You can

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of an oscillator circuit according to the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of an embodiment, and FIGS. 2 to 4 are characteristic diagrams showing characteristics at the time of lockup of an oscillation frequency. The same parts as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 1, reference numeral 1 is a first PLL circuit, and this first PLL circuit 1 is a phase comparator 1 as in the conventional case.
a, a loop filter 1b, a voltage-controlled oscillator (VCO) 1c, and a frequency divider 1d, 2 is a second PLL circuit, and the second PLL circuit 2 also has a phase comparator 2a and a loop similarly to the above. It is composed of a filter 2b, a voltage controlled oscillator (VCO) 2c and a frequency divider 2d.

The reference signals from the reference signal source 3 are supplied to the phase comparators 1a and 2a of the first and second PLL circuits 1 and 2 thus configured, and the first and second PLL circuits are also supplied. The frequency division ratio data from the frequency division ratio data controller 4 is supplied to the frequency dividers 1d and 2d of the circuits 1 and 2, and the first and second PLL circuits 1 are set by variably setting the frequency division ratio. , 2 VCO 1c, 2c oscillation frequency can be controlled by voltage control. That is, the first and second PLL circuits 1 and 2 have the same configuration, respectively, and constitute first and second PLL synthesizer type oscillation circuits.

That is, by using the same parts for the constituent elements of the first and second PLL circuits 1 and 2, for example, PLL
Damping factor ζ that represents the operating characteristics of the loop
And the angular frequency ω have the same oscillation frequency when the division ratios are the same, and one input signal of the phase comparison processing of the phase comparators 1a and 2a is supplied from one reference signal source 3, 1
Also, the oscillation frequency signals of the second PLL circuits 1 and 2 become coherent.

The oscillation output signals of the first and second PLL circuits 1 and 2 are mixed in the mixer circuit 5 and output to the output terminal 7 via the LPF 6.

Now, the frequency divider of the first and second PLL circuits 1 and 2
The frequency division ratio data from the frequency division ratio data controller 4 supplied to 1d and 2d are set to M ₁ and M _2, and the different frequency division ratios M ₁ and M ₂ are simultaneously supplied, so that VCO 1c and 2c The respective oscillating oscillation frequencies f ₁ and f ₂ are simultaneously oscillated and supplied to the mixer circuit 5.

The output frequency f ₃ of the mixer circuit 5 supplied with the oscillation frequencies f ₁ and f ₂ is passed through the LPF 6 and the difference signal of the oscillation frequencies f ₁ and f ₂ is: f ₃ = f ₁ -f ₂ Will be output. That is, the LPF 6 blocks the frequencies f ₁ and f ₂ and outputs the difference signal: f ₃ = f ₁
Only -f ₂ is passed and output from output terminal 7.

For example, the phase comparison frequency of the first and second PLL circuits 1 and 2 is 50 kHz, and the loop filters 1b and 2b are 2
In the case of the next system, the oscillation frequencies f ₁ and f ₂ of the first and second PLL circuits ₁ and ₂ have the relationship shown in "Table 1".

[0032]

[Table 1]

[0033] above, in "Table 1", the frequency division ratio M ₁ of the first PLL circuit 1 2 step by step changes, since the frequency dividing ratio M ₂ of the second PLL circuit 2 changes one by one step Output The oscillation frequency f ₃ becomes the oscillation frequency f ₁ -f ₂ and changes step by step.

Further, by simultaneously changing the oscillation frequencies f ₁ and f ₂ of the first and second PLL circuits 1 and 2 up and down respectively, the output oscillation frequency f ₃ also changes up and down at the same time. That is, for example, when the oscillation frequency f ₁ is rapidly changed from a low frequency to the oscillation frequency of the variable step 20: f ₁ = 102.0 MHz, the output frequency oscillation width of the oscillation frequency f ₁ has a damping factor ζ of “ζ <1. In the case of “”, a large frequency vibration width is generated at the moment when the frequency changes as shown in FIG. 2, and as time t elapses, the frequency vibration width is vibrationally attenuated as is well known.

Similarly, when the oscillation frequency f ₂ of the second PLL circuit 2 changes, a large frequency oscillation width is generated at the moment when the frequency changes as shown in FIG. The vibration width is decreasing.

In this way, from the oscillation frequencies f ₁ and f ₂ having a large frequency oscillation width when the frequency changes, the output oscillation frequency: f ₃
= f ₁ -f ₂ can obtain the frequency vibration width characteristic of FIG. 4 by subtracting the frequency vibration width characteristic of FIG. 3 from the frequency vibration width characteristic of FIG. 2. That is, FIG. 2 and FIG.
The frequency vibration width of FIG. 4 is canceled by the change of the above, and a characteristic in which the frequency vibration width is extremely reduced can be obtained.

However, the frequency oscillation width characteristic of FIG. 4 has the frequency division ratio M ₁ at lockup, even though the first and second PLL circuits 1 and 2 are composed of the same constituent elements. Strictly speaking, since the waveforms of the oscillating portions of the frequency oscillation width characteristics of FIG. 2 and FIG. 3 are not the same because M ₂ is different, the output oscillation frequency of the mixer circuit 5: f ₃ = f ₁ -f ₂ The frequency vibration component remains without being offset.

The residual frequency oscillation width of the output oscillation frequency: f ₃ = f ₁ -f ₂ will be described below. Generally, in a PLL circuit having a second-order loop filter, the oscillation angular frequency ω _n of the PLL circuit is ω _n = [(Kφ · K _V ) / {N · C (R ₁ + R ₂ )}] ^{1 / 2} ……… (1) formula. Where Kφ is the sensitivity of the phase comparator, K _V is the sensitivity of the VCO, N is the division ratio, and C, R ₁ and R ₂ are the constants of the loop filter.

First and second of variable step 20 of "Table 1"
In the PLL circuit 1, a first angular frequency omega _n = omega ₁ of the PLL circuit 1, when the angular frequency omega _n = omega ₂ of the second PLL circuit 2, each of the angular frequency omega _1, omega ₂ is From the above equation (1), ω ₁ = [(Kφ ・ K _V ) / {M ₁・ C (R ₁ + R ₂ )}] ^1/2 ……… (2) Equation ω ₂ = [(Kφ ・ K _V ) / {M ₂ · C (R ₁ + R ₂ )}] ^1/2 ……… (3)

In order to extract the error from the respective angular frequencies ω ₁ and ω ₂ , the respective angular frequency ratios: ω ₁ / ω ₂ are
Calculating from Eqs. (2) and (3), ω ₁ / ω ₂ = [Kφ ・ K _V・ M ₂・ C ・ (R ₁ + R ₂ ) / K φ ・ K _V・ M ₁・ C ・ (R ₁ + R ₂ )] ^1/2 = [M ₂ / M ₁ ] ^1/2 ……… (4), and in variable step 20, M ₁ = 2.040, M ₂ = 2.020, so (4 ) The formula is ω ₁ = 0.995 ω ₂ ……… (5). That is, it is understood from the equation (5) that the error between the angular frequencies ω ₁ and ω ₂ of the first and second PLL circuits 1 and 2 is 0.5% in the period of one cycle.

Generally, since the normal PLL circuit is designed so that the vibration converges in several cycles of the angular frequency ω _n , the error of 0.5% between the angular frequencies ω ₁ and ω ₂ is a negligible value, and the mixer It does not greatly affect the output oscillation frequency f ₃ of the circuit 5.

Next, the error in the vibration direction when the PLL circuit is locked up will be described below. Generally, in a PLL circuit having a secondary loop filter, a damping factor ζ
Is given by, ζ = (N + Kφ · K V · C · R 2) / 2 [N · Kφ · K V · C · (R 1 + R 2)] 1/2 ...
…… (6) becomes the formula.

First and second of variable step 20 of "Table 1"
In the state of the PLL circuit 1, the damping factor zeta = zeta ₁ of the first PLL circuit 1, if the damping factor zeta = zeta ₂ of the second PLL circuit 2, each of the damping factor zeta _1, zeta ₂ is equation (6) _{than, ζ 1 = (M 1 +} Kφ · K V · C · R 2) / 2 [M 1 · Kφ · K V · C · (R 1 + R 2)] 1/2 ...... ... (7) _{ζ 2 = (M 2 + Kφ} · K V · C · R 2) / 2 [M 2 · Kφ · K V · C · (R 1 + R 2)] 1/2 ......... ( 8) It becomes a formula.

Similar to the above, each damping factor ζ
₁ and ζ ₂ ratio: ζ ₁ / ζ ₂ is calculated from the above equations (7) and (8), ζ ₁ / ζ ₂ = [(M ₁ + Kφ · K _V · C · R ₂ ) * 2 [M ₂・ Kφ ・ K _V・ C ・ (R ₁ + R ₂ )] ^1/2 ] / [(M ₂ + Kφ ・ K _V・ C ・ R ₂ ) * 2 [M ₁・ Kφ ・ K _V・ C ・(R ₁ + R ₂ )] ^1/2 ] = [M ₂ / M ₁ ] ^1/2 * [(M ₁ + Kφ ・ K _V・ C ・ R ₂ ) / (M ₂ + Kφ ・ K _V・ C・ R ₂ )] ……… (9). In this equation (9), if Kφ · K _V · C · R ₂ = A, then equation (9) yields ζ ₁ / ζ ₂ = [M ₂ / M ₁ ] ^1/2 * [(1+ M ₁ / A) / (1 + M ₂ / A)] ……
… Equation (10) becomes.

Generally, in the first and second PLL circuits 1 and 2, the frequency division ratios M ₁ and M ₂ are designed in the region of “M ₁ and M ₂ << A”. , Ζ ₁ / ζ ₂ = [M ₂ / M ₁ ] ^1/2 ……… (11) Equation becomes, and when M ₁ = 2.040, M ₂ = 2.020 of variable step 20, Equation (11) becomes ₁ = 0.995 ζ ₂ ………… (12) It becomes clear that the damping factors ζ ₁ and ζ ₂ have a difference of 0.5%. That is, the first and second PLL circuits 1 and 2
The error of the damping factor: 0.5% at which the frequency oscillation at the time of lock-up converges is almost negligible.

Next, the convergence value of vibration in the indicial response of the PLL loop having the second-order loop filters 1b and 2b and the amplitude error a _n at the n-th vibration pole are obtained below. In general, the amplitude error a _n of the vibration waveform is given by a _n = exp [(-nζπ) / (1-ζ ² ) ^1/2 ] ... (13).

Now, the amplitude error of the first PLL circuit 1: a _n =
a ₁ , the amplitude error of the second PLL circuit 2: a _n = a ₂ ,
When the ratio of the respective amplitude errors a ₁₁ and a ₁₂ in the case _where the absolute value of the amplitude error an is n = 1 is calculated, a ₁₁ / a ₁₂ = exp [(-ζ ₁ · π) / (1− ζ ₁ ² ) ^1/2 ] / exp [(-ζ ₂ · π) / (1−ζ ₂ ² ) ^1/2 ] = exp [{(− ζ ₁ · π) / (1−ζ ₁ ² ) ^{1 / 2} }-{(− ζ ₂ · π) / (1−ζ ₂ ² ) ^1/2 }] ・ ・ ・ Equation (14).

Generally, the damping factor ζ is: ζ = 0.
Since a value of about 7 is set, assuming that ζ ₁ = 0.7 now, from the above formula (12), ζ ₂ = 0.995 * 0.7 = 0.6965 ... (15) Formula, and above ζ ₁ = 0.7 , The value of ζ ₂ = 0.6965 is given in (14) above.
Substituting into the equation, amplitude error: a ₁₁ = 1.03 * a ₁₂ (16).

That is, it is found that the error between the amplitude error a ₁₁ and the amplitude error a ₁₂ is 3%, and the first and second P
The output oscillation frequency f ₃ = f ₁ -f ₂ of the mixer circuit 5 at the time of lockup of the LL circuits 1 and ₂ is the maximum frequency oscillation width. Amplitude error ratio of frequency fluctuation width of PLL circuits 1 and 2: a ₁₁ / a ₁₂ = 3%
And will be reduced.

As described above, the angular frequencies ω ₁ and ω ₂ during the lockup of the PLL loop due to the difference between the frequency division ratios M ₁ and M ₂ of the first and second PLL circuits ₁ and ₂ , the damping factor ζ ₁ , zeta ₂ and amplitude errors a _1, the error ratio of a _2, which, as explained above, is significantly reduced in the output oscillation frequency f ₃ = f ₁ -f ₂ of the mixer circuit 5, the output oscillation frequency f ₃ = f ₁ The output oscillation signal of -f ₂ has almost no influence on the output characteristics.

Further, the smaller the frequency division ratios M ₁ and M _{2 of} the first and second PLL circuits 1 and 2, the smaller the frequency oscillation amount at lockup, and the output oscillation frequency of the mixer circuit 5. The frequency oscillation width at f ₃ can be greatly improved as shown in FIG.

[0052]

As described above, the oscillation circuit according to the present invention forms a PLL synthesizer type oscillator by using two first and second PLL circuits 1 and 2, and outputs each PLL synthesizer output to a mixer circuit. Since the low-frequency oscillation signal is mixed by 5 and is output, the oscillation frequency is switched at the same time by different division ratios of the division ratios M ₁ and M ₂ of the first and second PLL circuits 1 and 2. The oscillation frequency range of overshoot during lockup of the first and second PLL circuits 1 and 2 can be made extremely small, and sufficient stability during lockup of the PLL synthesizer oscillator circuit is secured. There is an effect that can be done.

That is, the output oscillation frequency f ₃ = f ₁ -f ₂ at which the oscillation output signals of the first and second PLL circuits 1 and 2 are mixed in the mixer circuit 5 is equal to the first and second PLL circuits. Error ratio of angular frequency ω caused by different division ratios M ₁ and M _{2 of} circuits 1 and 2: ω ₁ / ω ₂ = 0.5% and error ratio of damping factor ζ: ζ
₁ / ζ ₂ = 0.5%, or the maximum amplitude (n = 1) a ₁ error ratio: a ₁₁ /
a ₁₂ = 3% and the output characteristic of the output oscillation frequency f ₃ is P
The LL synthesizer output oscillation frequencies f ₁ and f ₂ can be reduced to almost negligible values.

Further, by setting the frequency division ratios M ₁ and M ₂ of the first and second PLL circuits ₁ and ₂ arbitrarily, a sufficient variable range can be achieved without narrowing the frequency variable range of the original PLL circuit. There is also an effect that the frequency can be varied by holding.

In this way, by improving the vibration characteristic at the time of lockup, the P of the oscillation circuit configured as described above is
This also shortens the lockup time of the LL loop, and has the effect that the oscillation frequency of the VCOs 1c and 2c can be stabilized by the phase comparison processing operation of the PLL circuit and voltage control.

Moreover, it has an excellent feature that the structure is simple, the constituent elements are the same as those of the oscillation circuit of the conventional example, and the structure can be constructed at low cost, so that the implementation is easy.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an oscillator circuit according to the present invention.

FIG. 2 is a characteristic diagram showing an output characteristic of a first PLL circuit.

FIG. 3 is a characteristic diagram showing an output characteristic of a second PLL circuit.

FIG. 4 is a characteristic diagram showing output characteristics of a mixer circuit.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a block diagram showing another conventional example.

[Explanation of symbols]

 1 1st PLL circuit 1a Phase comparator 1b Loop filter 1c Voltage controlled oscillator 1d Frequency divider 2 2nd PLL circuit 3 Reference signal source 4 Dividing ratio data controller 5 Mixer circuit 6 Low pass filter (LPF) 7 Output terminal

Claims (2)

[Claims] 1. A first and a second PLL synthesizer,
A frequency division ratio data controller for setting a frequency division ratio of the frequency dividers of the first and second PLL synthesizers, and the first and second frequency dividers.
A mixer circuit for mixing the oscillation output signals of the respective PLL synthesizers, and the first and second PLLs are controlled by the frequency division ratio data controller.
An oscillation circuit configured to obtain a variable frequency low-frequency oscillation output signal from the mixer circuit by varying the oscillation frequencies of the synthesizer at different oscillation frequencies and in the same direction. 2. The oscillator circuit according to claim 1, wherein a reference signal for phase comparison of the first and second PLL synthesizers is supplied from one reference signal source.