JPH06252704A - Active filter - Google Patents

Abstract

PURPOSE:To improve the stability of a frequency characteristic against an environmental change and a secular change. CONSTITUTION:The filter is formed by externally mounting required resistors R3-R6 and a capacitor C3 to a filter forming IC 21 having a state variable type filter circuit section formed by connecting a summing amplifier circuit and a switched capacitor filter circuit in cascade. The frequency characteristic is decided by a clock pulse executing switching control of the switched capacitor filter circuit. The clock pulse is generated by frequency-dividing a reference pulse generated by a crystal oscillator 3 at a preset frequency division ratio at a frequency divider 4 to improve the stability of a frequency characteristic against an environmental change and a secular change.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an active filter, and more particularly to a structure of a switched capacitor filter using a switched capacitor.

[0002]

2. Description of the Related Art FIG. 8 is a circuit diagram of a conventional active filter. The active filter shown in the figure is a bandpass filter configured by connecting a lowpass filter 11 and a highpass filter 12 in cascade. The low-pass filter 11 is configured by externally connecting a predetermined fixed resistor R5, semi-fixed resistors R4 and R6, a capacitor C3, and a pulse generation circuit 14 to an IC 13 for forming an active filter using a switched capacitor. .
The resistor R3 is an input resistor.

The pulse generation circuit 14 includes an inverter 14
1, a variable resistor R1 and a capacitor C5, and a time constant τ1 = R1 determined by the variable resistor R1 and the capacitor C5.
The frequency f1 of the output pulse is determined by C5.

The filter configuration IC 13 has three types of output terminals LP, HP and BP, and low-pass output, high-pass output and band-pass output can be obtained from the respective output terminals. The cutoff frequency and center frequency of each output are the clock frequency f externally input from the CLK terminal.
1 [Hz] and the external resistors R4, R6, R8, R10, etc., and the cutoff frequency F1 of the low-pass filter 11 is determined.
Is expressed by F1 = f1√ (R4 / R6) / 100 [Hz].

Like the low-pass filter 11, the high-pass filter 12 is also constructed by externally connecting a predetermined fixed resistor R9, semi-fixed resistors R8 and R10, a capacitor C4, and a pulse generation circuit 15 to the filter constituting IC 13. . The low-pass output of the low-pass filter 11 is input to the input terminal INV of the high-pass filter 12 via the resistor R7.
Has been entered in.

The pulse generation circuit 15 is also an inverter 151,
The variable resistor R2 and the capacitor C6 have the same configuration as the pulse circuit 13, and the frequency f2 of the output pulse is determined by the time constant τ2 = R2 · C6 determined by the variable resistor R2 and the capacitor C6. The cut-off frequency F2 of the high-pass filter 12 is expressed by F2 = f2√ (R8 / R10) / 100 [Hz], and the filter characteristic of the band-pass filter is that the cut-off frequencies F1 and F2 are set by the variable resistors R1 and R2. It is being coordinated.

[0007]

In the above conventional active filter, the filter characteristic is determined by the time constant τ1 determined by the variable resistor R1 and the capacitor C5 and the time constant τ2 determined by the variable resistor R2 and the capacitor C6. However, there is a drawback that the filter characteristics are greatly affected by the variations of the variable resistors R1 and R2 and the capacitors C5 and C62, and the variations in the characteristics between the filters become large. Also, the variable resistors R1 and R2 and the capacitor C
It is difficult to obtain high reliability because the filter characteristics easily change due to the changes of 5 and C6 with time.

It is also possible to adjust the filter characteristic or change to a different filter characteristic by adjusting the variable resistor R1 or R2, but another device for adjustment is required and the adjustment for a long time is required. It takes time and is not practical.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an active filter having stable and highly accurate filter characteristics.

[0010]

The invention according to claim 1 is
A state variable type filter unit in which a summing amplifier circuit and a switched capacitor filter circuit are connected in series, a crystal oscillation unit that generates a reference pulse, and a reference pulse generated by the crystal oscillation unit is preset. And a frequency division section for generating a clock pulse for performing switching control of the above-mentioned switched capacitor filter circuit by frequency division by a frequency division ratio.

According to the second aspect of the present invention, the active filter is provided with frequency division ratio setting means for setting the frequency division ratio.

The frequency division ratio setting means sets the input information and the information converting means for converting the input information into information having a digit number larger than the input information based on a preset logical expression and outputting the information. It may be composed of a plurality of switches.

[0013]

According to the first aspect of the present invention, the cutoff frequency of the filter circuit formed by the state variable filter section is determined by the frequency of the clock pulse for performing the switching control of the switched capacitor filter circuit. .
The clock pulse is generated by dividing the reference pulse generated in the crystal oscillating unit by a predetermined division ratio, has a stable frequency characteristic with respect to environmental characteristics and aging, and has a frequency characteristic of the filter circuit. Accuracy and stability are also improved.

According to the second aspect of the invention, the frequency of the clock pulse is determined by the set frequency division ratio, and thus the frequency characteristic of the filter circuit is also determined.

According to the third aspect of the present invention, the input information set and input by the state setting switch is converted into information having a larger number of digits than the input information based on the logical expression preset by the information converting means. Is output. This output information is input to the frequency division unit as frequency division ratio information, and a desired frequency division ratio can be set with a small amount of information.

[0016]

1 is a circuit configuration diagram of a first embodiment of an active filter according to the present invention. 2 is a diagram showing an equivalent circuit of a general-purpose filter IC applied to the active filter.

The active filter 1 shown in the figure uses a general-purpose filter section 2 whose filter characteristics can be controlled by a clock pulse input externally and a crystal oscillator which generates a reference pulse for generating the clock pulse. It is a bandpass filter composed of a crystal oscillator 3 and a frequency divider 4 that divides a reference pulse output from the crystal oscillator 3 to generate a desired clock pulse.

The general-purpose filter section 2 is a general-purpose filter IC (Integrated Circu) using a switched capacitor.
It) 21 is formed by externally connecting required resistors R3 to R6 and a capacitor C3. General-purpose filter IC21
Has a configuration circuit of a state variable type filter in which an adder 211 and integrators 212 and 213 using switched capacitors are connected in series, and three basic filter functions of low pass, high pass and band pass are provided. Output LP, H
P and BP can be output. Reference numerals 214 and 215 denote switched capacitors, which form equivalent resistances for determining the time constants of the integrators 212 and 213.

The switched capacitor 214 is a FET
The switch S1 is composed of a pair of switching elements S1a and S1b and the capacitor C1. The switching elements S1a and S1b are turned on / off so that they are in mutually opposite states by a clock pulse externally input from the CLK terminal. It is controlled. By this switching control, the switching element S1
The charge charged in the capacitor C1 during the ON period of a (the switching element S1b is the OFF period) is discharged to the inverting input of the operational amplifier OP1 during the OFF period of the switching element S1a (the ON period of the switching element S1b), and this charge / discharge is performed. Is performed in the cycle of the clock pulse, the input signal is input to the operational amplifier OP1. The switched capacitor 215 includes a switch S2 including a pair of switching elements S2a and S2b including FETs and a capacitor C2.
The same operation and function as 14 are performed.

The center frequency F0 of the bandpass filter 1 directly depends on the frequency f1 of the clock pulse and is represented by F0 = f1 / 100.

The resistor R3 is an input resistor, the resistor R5 connected between the INV terminal and the BP terminal and the capacitor C3 connected between the INV terminal and the LP terminal are the Q of the filter.
It is for adjusting characteristics such as (sharpness) and gain.

The frequency divider 4 is composed of an 8-digit programmable down counter 41. Down counter 4
The input terminals J0 to J7 of 1 are input terminals for setting the count value, which are pulled up through the resistor array 42 and the state is inverted by the switch 43. The frequency division ratio N is input by converting it into a binary number N _B and operating the switch 43. For example, when N = 64, N
_B = 1,000,000, so J2 corresponding to "0"
The count value N = 64 is set when the switches for the digits J7 to J7 are turned on.

The switch 43 is preferably D
It may be configured by an IP switch or a DIP type rotary switch. However, when the frequency division ratio N is fixed, for example, a jumper pin is provided at a portion corresponding to the switch 43 on the printed circuit board so that the down counter 41 has a predetermined set value N. _B may be set.

The down counter 41 counts down the reference pulse input from the crystal oscillator 3, and when the count value becomes 0, outputs a pulse signal and sets the count value to an initial setting value. Then, by repeating this operation, the frequency f0 of the reference pulse is divided by the division ratio N to output the clock pulse of the divided frequency f0 / N (= f1). This clock pulse is input to the CLK terminal of the general-purpose filter IC 21. As a result, the center frequency F0 of the bandpass filter 1 is F0 = f0 / (1
00N), the bandpass filter having desired filter characteristics can be easily obtained by changing the frequency division ratio N.

For example, in a burner flame monitoring device for a boiler or an industrial furnace, there is known a method of monitoring combustion state by extracting combustion sound of 150 to 960 Hz. When applying, the crystal oscillator 3 with an oscillation frequency of 6.144 MHz is used and the frequency divider 4
It is advisable to change the frequency division ratio N in the range of 1/64 to 1/410.

As described above, since the clock pulse for controlling the filter characteristic of the general-purpose filter unit 2 using the switched capacitor is generated by the crystal oscillator 3 and the frequency divider 4, the conventional RC oscillator is used. It is possible to significantly improve the accuracy of the filter characteristics and the stability against environmental changes, as compared with the case of using the clock pulse generated in Step 1.

FIG. 3 is a circuit configuration diagram of a second embodiment of the active filter according to the present invention. In the second embodiment, a bandpass filter is constructed by combining a lowpass filter and a highpass filter. And FIG.
In FIG. 1, the general-purpose filter unit 2 for bandpass filter is replaced with the general-purpose filter unit 5 for bandpass filter.

The general-purpose filter unit 5 is the general-purpose filter unit 2 described above.
General-purpose filter unit 51 for low-pass filter having the same configuration as
And a general-purpose filter section 52 for high-pass filter are connected in cascade. The low-pass output output from the LP terminal of the general-purpose filter unit 51 is input to the INV terminal of the general-purpose filter unit 52 via the resistor R7, and the general-purpose filter unit 52
The filter output is taken out from the HP terminal of. The clock pulse output from the frequency divider 4 is input to the CLK terminal of the general-purpose filter unit 5152.

The resistance R in the general-purpose filter section 52 is
8, R9, R10 and the capacitor C4 are the resistors R
It corresponds to 4, R5, R6 and capacitor C3,
Predetermined resistance values and capacitance values are set according to the filter characteristics of the high-pass filter.

In the second embodiment, the clock pulses of the low-pass filter and the high-pass filter are shared, and the cut-off frequency F0 _L of the low-pass filter and the cut-off frequency F0 _{H of the} high-pass filter are set by the same clock pulse. , F0 _L ≈F0 _H , and a narrow band pass filter can be obtained.

Further, since the two-stage configuration is adopted, the damping characteristic is improved as compared with the first embodiment having the one-stage configuration. For example, if the Q value is 1, and the attenuation characteristic of the filter of the one-stage configuration is -20 dB per octave, the attenuation characteristic of -40 dB per octave can be obtained with the filter of the two-stage configuration.

FIG. 4 is a circuit configuration diagram of a third embodiment of the active filter according to the present invention. In the third embodiment, the cutoff frequency F0 _H of the high pass filter in the second embodiment is used.
And the cut-off frequency F0 _{L of the} low-pass filter are made different,
This is to obtain a desired band. And
4 is the same as FIG. 3 except that the frequency divider 6 is added.
Instead of the frequency divider 4, the clock pulse output from the frequency divider 6 is input to the general-purpose filter unit 52 for high-pass filter. The reference pulse output from the crystal oscillator 3 is also input to the frequency divider 6.

The frequency division ratios of the frequency dividers 4 and 6 are respectively set to N1,
N2 and the frequencies of the output signals are f1 and f2,
The cutoff frequencies F0 _L and F0 _H are F0 _L = f0 / (100N
1), F0 _H = f0 / (100N2), and a bandpass filter with a pass band ΔF = (F0 _H −F0 _L ) can be easily obtained.

FIG. 5 is a circuit configuration diagram of a fourth embodiment of the active filter according to the present invention. In FIG. 5, the programmable logic device 7, the resistor array 71 and the switch 72 in place of the resistor array 42 and the switch 43 in FIG. 1 constitute a count value setting means of the programmable down counter 41. The switch 7 is a DIP switch or a DIP switch, like the switch 43.
Type rotary switch is recommended.

The programmable logic device 7 includes
A logic circuit for converting 4-bit information into predetermined 8-bit information is provided, and the 4-bit information set by the switch 72 is converted into predetermined 8-bit information (according to the logical expression programmed in the logic circuit). It is converted into a count value) and output to the data input terminals J0 to J7 of the programmable down counter 41. As described above, the programmable down counter 41 frequency-divides the reference pulse input from the crystal oscillator 3 based on the set count value and outputs the divided reference pulse to the CLK terminal of the general-purpose filter unit 2.

In the fourth embodiment, the user can arbitrarily configure a logic circuit that realizes a desired logical expression. Therefore, the center frequency F0 of the filter can be easily changed by changing only the logic circuit. There are advantages.

By the way, in the above embodiment, the frequency division ratio N of the frequency divider 4 is set by the switches 43 and 72. However, as shown in FIGS. 4 bits or 8 output from the section
It may be performed by a bit control signal. In this way, the center frequency F0 of the active filter 1 can be freely controlled in real time, and more complicated filter characteristics can be controlled.

[0038]

As described above, according to the present invention,
Generate a clock pulse that determines the cutoff frequency or center frequency of the filter circuit that is composed of the state variable type filter section using the switched capacitor filter circuit by dividing the reference pulse generated in the crystal oscillation section. As a result, an extremely stable cook pulse can be obtained, and the stability of the filter characteristics against environmental changes and changes over time is improved.

Since the frequency division ratio setting means is provided, a filter circuit having desired filter characteristics can be easily constructed. In particular, the dividing ratio setting means converts the input information into information having a digit number larger than that of the input information based on a preset logical expression and outputs the information, and a plurality of status settings for setting the input information. Since it is composed of a switch, it is possible to easily and surely construct a filter circuit having a desired filter characteristic with a small amount of information.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of an active filter according to the present invention.

FIG. 2 is a diagram showing an equivalent circuit of a general-purpose filter IC applied to an active filter according to the present invention.

FIG. 3 is a circuit configuration diagram of a second embodiment of an active filter according to the present invention.

FIG. 4 is a circuit configuration diagram of a third embodiment of an active filter according to the present invention.

FIG. 5 is a circuit configuration diagram of a fourth embodiment of an active filter according to the present invention.

FIG. 6 is a circuit configuration diagram of a fifth embodiment of an active filter according to the present invention.

FIG. 7 is a circuit configuration diagram of a sixth embodiment of an active filter according to the present invention.

FIG. 8 is a circuit configuration diagram of a conventional active filter.

[Explanation of symbols]

 1 Active Filter 2, 5, 51, 52 General-purpose Filter Unit 211 Summing Amplifier 212, 213 Integrator 214, 215 Switched Capacitor 3 Crystal Oscillator 4, 6 Divider 41 Programmable Down Counter 42, 71 Resistor Array 43, 72 , S1, S2 switches 7 programmable logic devices R3 to R10 resistors C1 to C4 capacitors OP1, OP2 operational amplifiers S1a, S1b, S2, S2b switching elements

Claims (3)

[Claims] 1. A state variable filter section comprising a summing amplifier circuit and a switched capacitor filter circuit connected in cascade, a crystal oscillator section for generating a reference pulse, and a reference pulse generated by the crystal oscillator section. Is divided by a preset dividing ratio to generate a clock pulse for performing switching control of the switched capacitor filter circuit, and an active filter. 2. The active filter according to claim 1, further comprising frequency division ratio setting means for setting the frequency division ratio. 3. The frequency division ratio setting means sets the input information, and information conversion means for converting the input information into information having a digit number larger than that of the input information based on a preset logical expression and outputting the information. 3. The active filter according to claim 2, comprising a plurality of switches.