JPH06252445A - Manufacture of light emitting diode array chip - Google Patents

Abstract

PURPOSE:To manufacture a light emitting diode array chip high in yield preventing an insulating layer from separating off at dicing. CONSTITUTION:The surface of an epitaxial wafer 10 is etched with N2 plasma, then an insulating layer 13 is formed, and light emitting devices each composed of a light emitting section 14 and an electrode section 15 are arranged on the surface of the epitaxial wafer 10. Therefore, the insulating film 13 is formed on the surface of the epitaxial wafer 10 activated by N2 plasma, so that the insulating layer 13 is enhanced in adhesion. When the epitaxial wafer 10 is divided into unit chips by dicing after the light emitting devices 16 are formed, a light emitting diode array chip can be manufactured high in yield without making an P-N junction exposed due to the separation of the insulating layer 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a light emitting diode array chip incorporated in an LED printer or the like with a high yield.

[0002]

2. Description of the Related Art An electrophotographic printer uses a light emitting diode array in which a plurality of light emitting elements are formed on a substrate at a constant pitch as a light source. Usually, 64-256 light emitting diodes are integrated on one chip substrate. As the light emitting diode material, GaAs _1-x P _x / GaAs is used in consideration of the ease of forming a long high-density array, the wavelength matching between the light emission output and the photoconductor sensitivity, and the like.
Is widely used. The light emitting diode array chip uses, as a semiconductor substrate, an epitaxial wafer 10 in which an epitaxial layer 12 of GaAsP is grown on the surface of a single crystal substrate 11 such as a Si wafer as shown in FIG. A light emitting portion 14 and an electrode portion 15 are provided on the epitaxial layer 12 via an insulating layer 13. Light emitting part 14
One light emitting element 16 is formed by the electrode portion 15.
The individual light emitting elements 16 are arranged on the epitaxial wafer 10 at a constant pitch.

In order to reduce the size and increase the functionality of light emitting diode array chips, the degree of integration of light emitting diodes is rapidly increasing. Recently, a chip in which the distance between adjacent light emitting elements 16 is set to about several μm has also been used. In this case, since it is necessary to arrange the light emitting elements 16 on the epitaxial wafer 10 in a uniform distribution, the distance L from the outermost light emitting element 16a (hereinafter, referred to as the outermost light emitting element) to the chip end surface 10a is L.
Has an extremely small gap of 10 μm or less.

[0004]

When producing a chip in which a large number of light emitting elements 16 are arranged up to the vicinity of the chip end surface 10a with an extremely small gap L, individual chips are formed from the epitaxial wafer 10 in which the light emitting elements 16 are built. The quality of the dicing work for cutting out the wafers has a great impact on the yield and productivity. Defects due to the dicing work are likely to appear on the outermost light emitting element 16a and its peripheral portion. That is,
Insulating layer 13 formed on epitaxial wafer 10
Has a low adhesiveness and is easily peeled off from the epitaxial wafer 10 due to the stress during dicing. In particular, the smaller the distance L from the outermost light emitting element 16a to the chip end surface 10a, the more remarkable the peeling of the insulating layer 13. When the insulating layer 13 is peeled off from the epitaxial wafer 10, as shown in FIG. 2, the pn junction 17 near the outermost light emitting element 16a is exposed. Exposed pn junction 1
7 causes a failure or malfunction.

In order to prevent peeling of the insulating layer 13, it is necessary to improve the adhesion of the insulating layer 13 to the epitaxial wafer 10. However, there is a limit to improving the adhesiveness by improving the insulating layer 13 itself,
In the current situation, peeling of the insulating layer 13 is unavoidable during the dicing work. As a result, defective chips are generated after dicing, and the yield is reduced. The present invention has been devised to solve such a problem, and improves the adhesion of the insulating layer to the substrate by etching the substrate surface with N ₂ plasma prior to forming the insulating layer, An object is to manufacture a light emitting diode array chip with a high yield.

[0006]

In order to achieve the object, the manufacturing method of the present invention is to etch the surface of a semiconductor substrate with N ₂ plasma, form an insulating layer on the surface, and then form a light emitting portion and an electrode. A plurality of light emitting elements each of which is formed on the surface of the semiconductor substrate.

[0007]

The reason why the insulating layer formed on the surface of the chip is easily peeled off from the semiconductor substrate such as an epitaxial wafer with a slight stress is due to the poor bonding between the insulating layer and the atoms on the surface of the substrate. Therefore, in the present invention, the substrate surface is activated by N ₂ plasma etching before forming the insulating layer. Since the inactive atoms have been removed from the etched substrate surface, it becomes a surface layer having an excellent affinity for the insulating layer formed thereon. When the pretreatment by N ₂ plasma etching is performed, the higher the output of the applied high frequency and the longer the treatment time, the more the inactive atoms existing on the substrate surface can be removed. As a result, the adhesiveness of the insulating layer to the semiconductor substrate is improved, and the peeling of the insulating layer is reliably prevented.

[0008]

EXAMPLE The epitaxial wafer 10 on which the epitaxial layer 12 was formed was subjected to etching pretreatment using N ₂ plasma generated by plasma CVD. At this time, the output of the high frequency applied to the N ₂ plasma and the processing time were changed. An insulating layer 13 was formed on the plasma-etched epitaxial wafer 10 by a conventional method, and a plurality of light emitting elements 16 including light emitting portions 14 and electrode portions 15 were formed at a pitch of 63.5 μm. In addition, when the chips are cut out from the epitaxial wafer 10, the outermost light-emitting element 16a located on the outermost side to the chip end surface 10
A plurality of light emitting elements 16 were arranged on the epitaxial wafer 10 so that the distance L to a was 18 μm.

The epitaxial wafer 10 on which a plurality of light emitting elements 16 are arranged is diced into chips of 8 mm × 0.5 mm, and the insulating layer 13 is formed on each of the cut chips.
The adhered state of was observed. When a maximum of 830 chips obtained from one wafer are cut out, the insulating layer 1
Those in which peeling was detected in No. 3 were judged as defective products, the number of defective products was converted into defective product occurrence rate, and the adhesiveness of the insulating layer 13 was evaluated. The survey results are shown in Table 1. In Table 1, No. 1 is given as a comparative example in the case where etching by N ₂ plasma is not performed. Further, the N ₂ plasma is changed within a range of high frequency output of 30 to 150 W (No. ₂ to 5) and processing time of 20 to 60 seconds (No. 4, 6, 7),
The influence of different treatment conditions on the adhesion of the insulating layer 13 was also examined.

[Table 1]

As is apparent from Table 1, in Comparative Example No. 1 in which chips were cut from a conventional substrate that was not etched by N ₂ plasma, defective products were generated at a rate of about 6.3%. . On the other hand, in the example in which the etching was performed by the N ₂ plasma, the defective product occurrence rate was about 1.9% even when the chip was cut out from the No. 2 wafer having the lowest high frequency output and the short processing time. It is falling. With the No. 5 wafer whose high-frequency output was increased to 150 W, the defective product generation rate was suppressed to about 0.5%. Further, in the wafer of No. 7 in which the processing time was set as long as 60 seconds, the defective product occurrence rate was suppressed to about 0.2%. It is speculated that these results are due to the removal of inactive atoms that adversely affect the adhesion of the insulating layer by etching the substrate surface with N ₂ plasma. Further, since the adhesion of the insulating layer is improved, the distance L from the outermost light emitting element 16a to the chip end surface 10a can be set shorter than in the past, and high resolution light emission in which a plurality of light emitting elements 16 are integrated at a higher density is achieved. It has become possible to manufacture diode arrays.

[0011]

As described above, according to the present invention, the surface of a semiconductor substrate such as an epitaxial wafer is covered with N ₂
An insulating layer is formed after plasma etching and activation. Therefore, the formed insulating layer adheres to the substrate surface with excellent adhesiveness, and is prevented from peeling from the substrate surface when cutting individual chips from the epitaxial wafer after the light emitting element is formed. It As described above, according to the present invention, a light emitting diode array chip is manufactured with a high yield, and particularly, a light emitting diode array chip in which light emitting elements are arranged at high density is efficiently manufactured.

[Brief description of drawings]

FIG. 1 is a plan view (a) and a side view (b) of a light emitting diode array.

FIG. 2 shows a state in which an insulating layer is peeled off from a substrate of a conventional diode array when dicing

[Explanation of symbols]

10: Epitaxial wafer 10a: Chip end surface
11: Single crystal substrate 12: Epitaxial layer 13: Insulating layer 13a:
Insulated layer 14 peeled off: Light emitting part 15: Electrode part
16: Light emitting element 16a: Outermost light emitting element 17: Exposed pn junction L: Distance from outermost light emitting element to chip end face

Claims (1)

[Claims] 1. A method comprising: etching a surface of a semiconductor substrate with N ₂ plasma; forming an insulating layer on the surface; A method of manufacturing a light emitting diode array chip characterized by the above.