JPH06252272A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve coverage of a barrier layer in a contact hole having large aspect ratio in which a metal plug is buried. CONSTITUTION:The title semiconductor device has a contact hole 24 whose aspect ratio is large and a contact hole 25 whose aspect ratio is small, and metal plugs 29 are buried in the contact holes. A substratum polycrystalline silicon layer 22 is selectively formed facing to the inner part of the contact hole 24 whose aspect ratio is large.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art As a semiconductor device is highly integrated and miniaturized, a method of filling a contact hole having a high aspect ratio is required. Currently, as an embedding process with high mass production feasibility, a conventional Al alloy sputter method, a high temperature Al alloy sputter method in which a substrate is heated to a high temperature, a metal film formation such as blanket tungsten CVD and full surface etching are combined to form a metal plug. And a method of selectively forming a metal plug on a contact portion such as a selective tungsten CVD method are considered promising.

The high temperature Al alloy sputtering method will be described with reference to FIG. This figure shows a case where the present invention is applied to a multilayer wiring of a semiconductor device.

First, as shown in FIG. 13A, a first layer Al alloy layer 2 serving as a lower wiring layer is formed on an insulating layer 1 of a semiconductor substrate.
(Al-1% Si), then an insulating film by a CVD method, an interlayer flattening film 3 by a coating type silicone resin (SOG), etc. are formed to correspond to the connection portion of the first Al alloy layer 2. A contact hole 4 is opened in the portion.

Next, as shown in FIG. 13B, a pure titanium film 5 is formed on the entire surface including the inside of the contact hole 4 by the sputtering method.

Next, as shown in FIG. 13C, a second layer Al alloy layer 6 to be an upper layer wiring is formed on the entire surface including the inside of the contact hole 4.
(Al-1% Si) is formed into a film by a high temperature sputtering method (film forming conditions: 0.26 Pa, 7.5 KW, Ar 100%),
The contact hole 4 is buried.

By the film formation by the high temperature sputtering, the pure titanium film 5 and the Al alloy layers 2 and 6 react with each other to form a TiAl ₃ intermetallic compound layer 7. The TiAl ₃ intermetallic compound layer 7 interposes the lower wiring. Al alloy layer 2 and upper wiring A
The l-alloy layer 6 is connected in the contact hole 4.

Next, a method of forming the metal plug will be described with reference to FIG. In this example, a contact between a required diffusion layer formed on a silicon substrate and a wiring is taken as an example.

First, as shown in FIG. 14A, the diffusion layer 10
An interlayer insulating film 12 is deposited on the silicon substrate 11 on which the contact holes 1 are formed, and contact holes 1 are formed at desired positions on the interlayer insulating film 12.
3 is formed.

Next, as shown in FIG. 14B, a Ti layer 14 and a TiON layer 15 as barrier layers 16 are deposited on the entire surface including the contact holes 13, and a tungsten layer 17 is further deposited.
Deposit.

Next, as shown in FIG. 14C, the tungsten layer 17 on the entire surface of the wafer is etched back and removed. In the figure, the TiON layer 15 and the Ti layer 14 on the interlayer insulating film 12 are shown.
Are also removed at the same time. However, the Ti layer 14 and the TiO
The N layer 15 may not be removed.

Thus, the metal plug 1 made of so-called blanket tungsten or the like is formed in the contact hole 13.
8 is formed.

Thereafter, as shown in FIG. 14D, an AlSiCu alloy layer is formed on the entire surface so as to be connected to the metal plug 18, and patterned to form a wiring layer 19.

In addition, for example, Japanese Patent Laid-Open No. 62-229959.
The publication discloses a method of forming a metal plug, which includes a step of vacuum-depositing a metal, a step of applying a resist, and a step of etching the entire surface.

Further, Japanese Laid-Open Patent Publication No. 62-186547 reports an embedding method comprising a step of selectively growing a refractory metal on a contact portion and a step of forming a metal film on the entire surface.

Further, in Japanese Unexamined Patent Publication No. 1-200648, a step of forming a metal film on the entire surface of a contact hole on a silicon substrate, a step of silicifying the metal of the contact portion by heat treatment, and a metal film of unreacted portion An embedding method consisting of a removing step has been reported.

[0017]

By the way, in the conventional example described in FIG. 13, in the step of FIG. 13C, when the wafer temperature is not sufficiently high or the aspect ratio b / a of the contact hole 4 is large. It is known that, in this case, a region where the Al alloy does not enter, that is, a void 8 is generated at the bottom of the contact hole, causing an increase in contact resistance and a decrease in yield.

Further, in the case of Japanese Patent Application Laid-Open No. 62-229959, there is a problem that the controllability and uniformity of the entire surface etching are poor and the process stability is lacking. Similarly, in the method of forming a metal CVD plug of blanket tungsten, etc., there are many problems due to the entire surface etching, the adhesion to the underlying film is poor, it is difficult to fill the contact holes with different diameters, and the unevenness of the underlying film is present. A lot of problems remain, such as the residue being easily left in the area, and if the etching amount is increased, whiskers will be generated on the plug and the barrier metal film formed to improve adhesion will be selectively etched. There is.

Further, in Japanese Patent Laid-Open No. 62-186547, there remains a problem that the selectivity of the CVD film is broken due to the state of the base film and the adhesion with the base film is poor. Further, in Japanese Patent Laid-Open No. 1-200648, it cannot be used in a contact hole between metal wirings in which silicon is not exposed.

Further, in the example shown in FIG. 14, the Ti layer 14 and the TiON layer 15 are required as the barrier 16 in order to suppress the reaction between the tungsten layer 17 and the silicon substrate 11, but the aspect ratio of the contact hole 13 is small. When it becomes larger, the coverage of the barrier layer 16 at the bottom of the contact is deteriorated, the barrier effect is lowered, and an increase in junction leak due to the tungsten alloy spike is caused. This is unavoidable especially in a device having a multi-layered polycrystalline silicon wiring layer such as a memory device and having a large aspect ratio of the contact hole.

Further, when a contact hole having a large aspect ratio and a contact hole having a small aspect ratio coexist, the metal plug is embedded only in the contact hole having a large aspect ratio as shown in FIG. .
That is, first, as shown in FIG. 15A, the conductive metal layer 20 is deposited with a sufficient thickness so as to be embedded in the contact hole 13A having a large aspect ratio. At this time, the conductive metal layer 20 is also buried in the contact hole 13B having a small aspect ratio which does not necessarily need to be buried. Next, as shown in FIG. 15B, the conductive metal layer 20 is etched back to the opening edge of the contact hole having a large aspect ratio to form the metal plug 20A only in the contact hole 13A having a large aspect ratio. However, when the etch back amount of the conductive metal layer 20 is adjusted to match the contact hole 13A having a large aspect ratio, the contact hole 13 having a small aspect ratio is formed.
The conductive metal layer 20 in B is completely removed, and further damages the underlying layer, that is, the diffusion layer 10 in the illustrated example.

On the other hand, a method of arranging the polycrystalline silicon in all the contact holes can be considered, but in that case, the process and the structure are complicated when the polycrystalline silicon is arranged in the peripheral circuit portion. .

In view of the above points, the present invention provides a semiconductor device and a method of manufacturing the same which solve the conventional problems.

[0024]

The present invention provides a semiconductor device having a contact hole 24 having a large aspect ratio and a contact hole 25 having a small aspect ratio, and a metal plug 29 provided in each of the contact holes 24, 25. The underlying semiconductor layer 22 is selectively provided so as to face the contact hole 24 having a high aspect ratio.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming an interlayer insulating film 23 after forming a base semiconductor 22 in a portion where a contact hole 24 having a large aspect ratio is to be formed, and the interlayer insulating film 23. Contact hole 24,
25, a step of forming a barrier layer 28 in the contact holes 24, 25, a step of burying a metal 29 in the contact holes 24, 25, and a step of forming an upper conductor 30 connected to the metal 29. Is to have.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a refractory metal film 45 in the contact hole 44 facing the lower conductor 42 by a sputtering method, and a refractory metal film on the bottom of the contact hole 44. It has a step of forming a compound 46 of the film 45 and the lower conductor 42, a step of selectively removing the refractory metal film 45, and a step of forming the upper conductor 47.

The method of manufacturing a semiconductor device according to the present invention is
After forming the lower conductor 51, the pad semiconductor layer 56 is formed in the region where the contact hole is to be formed, and then the contact hole 5 is formed.
4, a step of forming a refractory metal film 45 in the contact hole facing the lower conductor 51 by a sputtering method, and a compound 58 of the refractory metal film 45 and the pad semiconductor layer 56 at the bottom of the contact hole 54. , A step of selectively removing the refractory metal film 45, and an upper conductor 59.
And a step of forming.

The method of manufacturing a semiconductor device according to the present invention is
In a semiconductor device having a contact hole 75 with a large aspect ratio and a contact hole 76 with a small aspect ratio, after the first film 77 is selectively formed in the contact hole 76 with a small aspect ratio, the first conductive material film 79 is formed. And a step of etching back the first conductive material film 79 under the condition that the etching rate of the first film 77 is smaller than that of the first conductive material film 79.

An insulating film can be used as the first film 77.

A conductive film can be used as the first film 77.

The etch back can be performed by anisotropic etching.

[0032]

In the semiconductor device according to the first aspect of the present invention, the underlying semiconductor layer 22 is selectively provided at the bottom of the contact hole 24 having a large aspect ratio, and the metal plug 29 is provided on the underlying semiconductor layer 22, thereby providing the aspect ratio. It is possible to raise the bottom of the contact hole 24 with a large
The deterioration of the coverage of the barrier layer 28 in 9 is improved, and the spike between the metal plug 29 and the substrate, that is, the deterioration of the barrier ability can be suppressed.

In the method of manufacturing the semiconductor device of the second invention, first, the contact hole 24 having a large aspect ratio is formed.
By forming the base semiconductor 22 in the portion where the layer is to be formed, and then forming the interlayer insulating film 23 and forming the contact hole 24, it is possible to raise the so-called contact hole 24, and thereafter the barrier layer 28 is formed and metal is formed. In the step of embedding 29 or the like, it is possible to improve deterioration of the coverage of the barrier layer 28 and suppress deterioration of the barrier ability.

In the method for manufacturing a semiconductor device of the third invention, a refractory metal film 45 is formed in the contact hole 44 facing the lower conductor 42, a compound 46 with the lower conductor 42 is formed, and then the compound 46 is formed. By selectively removing the high-melting-point metal film 45 except for, the compound 46 substantially raises the bottom of the contact hole 44, and the aspect ratio of the contact hole 44 can be reduced. Therefore, when used together with the subsequent metal burying by high temperature sputtering, it is possible to easily bury a deeper contact hole.

A method of manufacturing a semiconductor device according to a fourth aspect of the present invention is the method of manufacturing the semiconductor device according to the third aspect, further including a contact hole 5.
By forming the pad semiconductor layer 56 in the lower portion of the contact hole 4, the bottom of the contact hole 54 can be further raised and the aspect ratio can be reduced.

In the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, after the first film 77 is selectively formed in the contact hole 76 having a small aspect ratio, the first conductive material film 79 is formed on the entire surface. Then, by etching back the first conductive material film 79 under the condition that the etching rate of the first film 77 is smaller than that of the first conductive material film 79, the first film 77 is formed in the contact hole 76 having a small aspect ratio. As a result, the etch back is completed, and the conductive plug 81 can be embedded only in the contact hole 75 having a large aspect ratio without damaging the base 73.

When an insulating film is used as the first film 77, the etching selection ratio with the first conductive material film 79 can be easily obtained.

When a conductive film is used as the first film 77, the first film is formed on the side of the contact hole 76 having a small aspect ratio.
Since conduction between the film 77 of No. 3 and the base 73 can be obtained, after that,
The step of removing the first film 77 can be omitted.

When etching back is performed by anisotropic etching, the contact hole 7 having a small aspect ratio is used.
Side wall 79A formed by the first conductive material layer 79
Are formed, and the step coverage in the contact hole 76 at the time of subsequent wiring formation becomes good.

[0040]

Embodiments of the semiconductor device and the method for manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the semiconductor device of the present invention.
This example is applied to, for example, a semiconductor memory. In FIG. 1, an area a indicates a memory section and an area b indicates a peripheral circuit section. In this example, although not shown, a required semiconductor memory is formed on the same semiconductor substrate 21, and a MOS type peripheral circuit, for example, is formed on the peripheral circuit portion.

Then, the polycrystalline silicon layer 22 is selectively formed in advance in a portion of the semiconductor substrate 21 where a contact hole having a large aspect ratio is to be formed on the memory portion side. The contact holes 24 and 25 are provided at the positions corresponding to the respective peripheral circuit parts b.
Are formed respectively. Here, although the contact hole 24 of the memory portion a originally has a larger aspect ratio than the contact hole 25 of the peripheral circuit portion b, the contact hole 24 is raised by the polycrystalline silicon layer 22. The aspect ratio of the contact hole 25 in the peripheral circuit portion b is small. Then, the Ti layer 26 and the TiO that will become the barrier layer 28 are formed in the respective contact holes 24 and 25.
An N layer 27 is formed by deposition, and a blanket tungsten metal plug 29 is embedded in each contact hole 24 and 25 so as to be connected to the metal plug 29 embedded in each contact hole 24 and 25. For example, the wiring layer 30 made of AlSiCu alloy is formed.

According to the semiconductor device 31 having such a configuration, the contact hole 2 having a large aspect ratio on the side of the memory cell portion a.
By forming the polycrystalline silicon layer 22 below the contact hole 24, the bottom of the contact hole 24 is raised, the substantial aspect ratio is reduced, the coverage of the barrier layer 28 is improved, and the barrier ability thereof is excellent. At the same time, the polycrystalline silicon layer 22 prevents tungsten spikes, and no inconvenience such as junction leak occurs.

Next, a manufacturing method for obtaining the above-mentioned semiconductor device 31 will be described with reference to FIGS.

First, as shown in FIG. 2A, the memory cell portion a
And the semiconductor substrate 21 on which the peripheral circuit section b is formed
A polycrystalline silicon layer 22 having a thickness of 100 nm, for example, is selectively formed in advance on the contact formation portion on the side of the upper memory cell portion a, and then an interlayer insulating film 23 is deposited over the entire surface to form the memory cell portion a and Contact holes 24 and 25 are formed in the peripheral circuit portion b. 32 and 33 are, for example, one diffusion layer of a MOS transistor. The contact hole 24 on the memory cell portion a side is formed so that the polycrystalline silicon is just exposed. Here, the contact hole 24 on the side of the memory cell portion a has a large aspect ratio as described above, but has a shape raised by the polycrystalline silicon layer 22. The aspect ratio of the contact hole 25 in the peripheral circuit portion b is small. Further, the width w of the contact hole 24 on the side of the memory cell portion a
The width w ₂ of the polycrystalline silicon layer 22 is formed larger than ₁ .

Next, as shown in FIG. 2B, a Ti layer 26 and a TiON layer are formed on the entire surface including the contact holes 24 and 25.
Layers 27 are sequentially deposited to form barrier layer 28, and
A blanket tungsten layer 29A is deposited to fill the contact holes 24 and 25.

Next, as shown in FIG. 3C, etch back is performed so that the tungsten layer embedded in each contact hole 24 and 25 is flush with the upper surface of the interlayer insulating film 23.
A metal plug 29 made of a tungsten layer is formed in each of the contact holes 24 and 25. At this time, the TiON layer 27 and the Ti layer 26 under the tungsten are also etched back at the same time. The Ti layer 26 and the TiON layer 27 do not have to be removed.

Next, as shown in FIG. 3D, for example, an AlSiCu alloy is deposited on the entire surface and then patterned to form a wiring layer 30 of the AlSiCu alloy to obtain the intended semiconductor device 31.

According to such a manufacturing method, the polycrystalline silicon layer 22 is arranged as a base in the contact hole 24 having a high aspect ratio, and the polycrystalline silicon layer 22 is not formed in the contact hole 25 having a small aspect ratio. As a result, it is possible to suppress the deterioration of the barrier ability due to the deterioration of the coverage of the barrier layer 28. Particularly, in the semiconductor memory device, by arranging the polycrystalline silicon layer 22 in the memory cell portion a and not arranging the polycrystalline silicon layer 22 in the peripheral circuit portion, the process and the structure can be simplified.

When applied to a semiconductor memory cell, the polycrystalline silicon film 22 formed under the contact hole having a high aspect ratio is formed simultaneously with the polycrystalline silicon film used as another conductor layer of the memory cell portion a. be able to.
Further, since the polycrystalline silicon film is not formed in the peripheral circuit section b, the density of the MOS transistors in the peripheral circuit section can be increased.

4 and 5 show another embodiment of the method for manufacturing a semiconductor device according to the present invention. In this example, first, as shown in FIG. 4A, a first lower layer wiring is formed on an insulating layer 41 on a semiconductor substrate.
After selectively forming the layer Al alloy (Al-1% Si) layer 42, for example, a CVD insulating film, a coating type silicone resin (S
A flattened interlayer insulating film 43 is formed by OG) or the like, and the interlayer insulating film 4 is exposed so that the connection portion of the first Al alloy layer 42 is exposed.
A contact hole 44 is formed in 3.

Next, as shown in FIG. 4B, a pure titanium film 45 is formed on the entire surface including the contact hole 44 by a sputtering method. At this time, the titanium film thickness is required to be sufficiently formed on the bottom of the contact hole 44, and the thicker the better.
For example, a film having a thickness of about 300 nm is formed.

Next, the semiconductor wafer is heated to a temperature of 350 ° C. or higher in a high vacuum or in an inert gas atmosphere, and the TiAl ₃ intermetallic layer is formed on the bottom of the contact hole 44 by the reaction between the pure titanium film 45 and the Al alloy layer 42. The compound layer 46 is formed. The TiAl ₃ layer 46 is formed by a diffusion reaction of the Al alloy layer 42 and the pure titanium layer 45, and has a form of Ti (AlSi) ₃ when the Al alloy is, for example, aluminum silicon. The formation of this reaction layer, that is, the TiAl ₃ layer 46 is accompanied by volume expansion.

For example, the pure titanium film 45 formed during the high temperature Al alloy sputtering for 1 minute at a wafer temperature of 475 ° C. is 100
In the case of nm, the TiAl ₃ layer 46 formed at the bottom of the contact hole 44 has a thickness of about 300 nm.

Next, as shown in FIG. 5D, since the pure titanium film 45 in contact with the interlayer insulating film 43 other than the bottom of the contact hole 44 has not reacted, it is selectively removed.
For example, it can be selectively removed by wet etching with a dilute hydrofluoric acid solution (HF + H ₂ O). The contact hole 44 that must be buried at this point is expected to have a bottom increase of 300 nm or more, and the aspect ratio will be substantially reduced.

Thereafter, as shown in FIG. 5E, a pure titanium film (not shown) is again formed on the entire surface of the interlayer insulating film 43 including the inside of the contact hole 44, and the second layer Al to be the upper wiring is formed.
The alloy wafer (Al-1% Si) layer 47 has a semiconductor wafer temperature of 3
A film is formed by a high temperature sputtering method at 50 ° C. or higher, and the contact hole 44 is embedded. At this time, the TiAl ₃ intermetallic compound layer 4 is formed by the diffusion reaction between the pure titanium film and the Al alloy 47.
Therefore, the first layer Al alloy layer 42 as the lower layer wiring and the second layer Al alloy layer 47 as the upper layer wiring are connected through the contact hole 44. Thereafter, although not shown, the upper Al alloy layer 47 is patterned to form an upper wiring. In this way, the semiconductor device 49 having a multilayer wiring is obtained.

According to this manufacturing method, even in the contact hole 44 having a high aspect ratio, the bottom of the contact hole 44 is raised by forming the TiAl ₃ intermetallic compound layer 46 in the steps of FIGS. 4B to 5D. The aspect ratio is substantially reduced. Therefore, it is possible to easily realize the deeper filling of the contact hole 44 by using it in combination with the subsequent titanium film and the Al alloy layer 47 formed by the high temperature sputtering, and the stable contact resistance, yield, and high It is possible to manufacture a highly integrated semiconductor device having reliability.

FIG. 6 shows another embodiment of the method for manufacturing a semiconductor device of the present invention. This example is a combination of the manufacturing method shown in FIG. 1 and the manufacturing method shown in FIGS. In the figure, lower conductor layers 51 and 52 are formed in a portion where a contact hole with a large aspect ratio is to be formed and a portion where a contact hole with a small aspect ratio is to be formed, respectively. For example, in a semiconductor memory device, the lower conductor layers 51 and 52
Each correspond to one diffusion region of the MOS transistor. Then, on the semiconductor substrate 53 on which the lower conductor layers 51 and 52 are formed, a polycrystalline silicon layer 56 is selectively formed in advance at a portion where a contact hole 54 having a large aspect ratio is to be formed. Then, an inter-layer insulating film 57 is deposited and formed to form respective contact holes 54 and 55. That is, the contact hole 54 having a large aspect ratio
Is formed so as to reach the polycrystalline silicon film 56 on the lower conductor layer 51 and has a small aspect ratio.
Is formed so that the lower conductor layer 53 faces.

The subsequent steps are the same as those shown in FIGS. That is, as in the case of FIG. 4B, a pure titanium film 45 including the contact holes 54 and 55 is entirely formed by the sputtering method. At this time, the titanium film is formed thick. Next, in the same manner as in FIG. 4C, the semiconductor wafer is heated to a required temperature in a high vacuum or an inert gas atmosphere,
A titanium film and a polycrystalline silicon film 5 are formed on the bottom of the contact hole 54.
A titanium silicide layer 58 is formed by the reaction with 6.
The titanium silicide reaction layer 58 is also accompanied by volume expansion.
Next, the pure titanium film 45 not reacted in the same manner as in FIG. 5D.
Are selectively removed. At this point, the titanium silicide layer 58 is expected to raise the contact hole 54 to a predetermined thickness or more, and the aspect ratio is reduced. Then, a titanium film is formed again to form an Al alloy layer 59 to be wiring by a high temperature sputtering method at a wafer temperature of, for example, 350 ° C. or higher, and the contact holes 54 and 55 are buried.
Reference numeral 60 is Ti due to the reaction between the Al alloy layer 59 and the pure titanium film.
It is an Al ₃ layer. In this way, the desired semiconductor device 61
To get The titanium silicide layer 58 also prevents spikes and helps reduce the aspect ratio.

7 to 9 show another embodiment of the method of manufacturing a semiconductor device according to the present invention. As shown in FIG. 7A, the diffusion region 7
An interlayer insulating film 74 made of, for example, SiO ₂ is formed on the main surface of the silicon semiconductor substrate 71 on which _2, 73 are formed,
Contact holes 75 and 76 facing the diffusion regions 72 and 73 are formed in the interlayer insulating film 74. One contact hole 75 has a large aspect ratio, and the other contact hole 76
Has a small aspect ratio. After forming the contact holes 75 and 76, an insulating film, for example, a SiO ₂ film 77 is deposited and formed on the entire surface including the inner surfaces of the contact holes 75 and 76. Then
A photoresist layer 78 is selectively formed so as to cover the contact hole 76 having a small contact ratio.

Next, as shown in FIG. 7B, the SiO ₂ film 7 on the side of the contact hole 75 having a large aspect ratio is formed by, for example, anisotropic etching using the photoresist layer 78 as a mask.
7 is selectively removed. That is, the SiO ₂ film 77 selectively remains only on the side of the contact hole 76 having a small aspect ratio.

Next, the photoresist layer 78 is removed, and as shown in FIG. 8C, the natural oxide film on the bottom surface of the contact hole 75 is removed by, for example, isotropic etching.
A conductive material film 79, for example, a polycrystalline silicon film is formed on the entire surface so as to be sufficiently embedded in the contact hole 75 having a large aspect ratio. At this time, the conductive material film, that is, the polycrystalline silicon film 79 grows from the side walls and bottom surfaces of the contact holes 75 and 76. Therefore, at least the polycrystalline silicon film 7
Although the film thickness of 9 requires 1/2 of the opening diameter of the contact holes 75 and 76, in reality, a concave portion of the polycrystalline silicon film 79 is formed on the center of the contact hole where the film grown from the side wall contacts. As will be described later, when the polycrystalline silicon film 79 is etched back in this state, the etching proceeds from the concave portion at the center of the contact hole, and a conical hole having an acute-angled vertex is formed after the etching back. For this reason, the polycrystalline silicon film 79 is formed with a film thickness such that the recess becomes small when the polycrystalline silicon film 79 is formed, for example, 1.2 to 1.5 times the opening radius of the contact holes 75 and 76. Can be formed.
In the state where the polycrystalline silicon film 79 is formed, the contact hole 75 having a large aspect ratio and the contact hole 76 having a small aspect ratio have different heights from the bottom surface of the contact hole to the surface of the film 79.

Next, as shown in FIG. 8D, the polycrystal silicon film 79 is etched back by isotropic etching to remove the polycrystal silicon film 79 on the side of the contact hole 76 having a small aspect ratio. The conductive plug 81 made of the polycrystalline silicon film 79 is formed only in the contact hole 75 having a large ratio. During etching back for the polycrystalline silicon film 79, because in the small contact hole 76 aspect ratio SiO ₂ film 77 having a different etching rate than the polycrystalline silicon film 79 is formed, in the SiO ₂ film 77 The etching stops, and the base, that is, the diffusion region 73 is not damaged.

Next, as shown in FIG. 9E, the inter-layer insulation film (SiO ₂ ) 74 and the SiO ₂ film 77 are isotropically etched back to the whole surface, and a conductive plug is formed on the side of the contact hole 75 having a large aspect ratio. 81 and the interlayer insulating film 74 are substantially flush with each other, and the SiO ₂ film 77 on the inner surface of the contact hole 76 having a small aspect ratio is removed so that the diffusion region 73 is exposed.

Next, as shown in FIG. 9F, a barrier metal layer (for example, TiN, TiN / Ti, etc.) 82 is formed in the contact hole 76 having a small aspect ratio, and the barrier metal layer 82 is interposed therebetween. A wiring layer 83 made of Al or the like is formed as an upper layer. Then, the wiring layer 83 and the barrier metal layer 82 are patterned into a predetermined pattern.
In this way, the target semiconductor device is obtained.

According to this manufacturing method, in the semiconductor device having the contact hole 75 having a large aspect ratio and the contact hole 76 having a small aspect ratio, the conductive plug 81 is provided only in the contact hole 75 having a large aspect ratio.
Can be formed, and respective contact holes 75, 76 can be formed.
The wiring layer 83 having good coverage can be formed.

In particular, in the step of FIG. 7B, the SiO ₂ film 77 is selectively formed in the contact hole 76 having a small aspect ratio, and then the polycrystalline silicon film 79 for forming the conductive plug 81 is formed. When etching back, Si is formed in the contact hole 76 having a small aspect ratio.
Since the etching is stopped by the O ₂ film 77 and further etching does not proceed, the conductive plug 81 is formed only in the contact hole 75 having a large aspect ratio without causing unnecessary damage to the base, that is, the diffusion region 73 in the illustrated example. Can be formed.

10 to 12 show still another embodiment of the method of manufacturing a semiconductor device according to the present invention. As shown in FIG. 10A,
An interlayer insulating film 74 made of, for example, SiO _{2 is} formed on the main surface of the silicon semiconductor substrate 71 having the diffusion regions 72 and 73, and contacts having a large aspect ratio, in which the diffusion regions 72 and 73 face the interlayer insulating film 74, respectively. The hole 75 and the contact 76 having a small aspect ratio are formed. After forming the contact holes 75 and 76, an insulating film, for example, a SiO ₂ film 77 is formed on the entire surface including the inner surfaces of the contact holes 75 and 76.
Next, a photoresist layer 78 is selectively formed so as to cover the contact hole 76 having a small contact ratio.

Next, as shown in FIG. 10B, the SiO ₂ film 7 on the side of the contact hole 75 having a large aspect ratio is anisotropically etched by using the photoresist layer 78 as a mask.
7 is selectively removed. At this time, a side wall portion (so-called side wall) 77A made of the SiO ₂ film 77 is formed on the side surface of the contact hole 75. In this process, the SiO ₂ film 7 is selectively formed on the contact hole 76 side having a small aspect ratio.
7 remains. Reference numeral 80 is a natural oxide film formed on the bottom surface of the contact hole 75.

Next, the photoresist layer 78 is removed, and as shown in FIG. 11C, the natural oxide film 80 on the bottom surface of the contact 75 is removed by, for example, isotropic etching. A conductive material film, for example, a polycrystalline silicon film 79 is formed on the entire surface so as to be sufficiently embedded in the contact hole 75 having a large aspect ratio.

Next, as shown in FIG. 11D, the polycrystalline silicon film 79 is etched back by anisotropic etching to remove the polycrystalline silicon film 79 on the side of the contact hole 76 having a small aspect ratio, and the aspect ratio. The conductive plug 81 made of the polycrystalline silicon film 79 is formed only in the contact hole 75 having a large ratio. By this anisotropic etching, a sidewall portion (so-called sidewall) 79A of the polycrystalline silicon film 79 is formed on the inner surface of the contact hole 76 having a small aspect ratio.

Next, as shown in FIG. 12E, the interlayer insulating film (SiO ₂ ) 74 and the SiO ₂ film 77 are etched back by isotropic etching to form SiO _{2 on} the bottom surface of the contact hole 76 having a small aspect ratio. The film 77 is removed.

Next, the natural oxide film on the bottom surface of the contact hole 76 having a small aspect ratio is removed to form a barrier metal layer 82 including the inside of the contact hole 76 having a small aspect ratio, as shown in FIG. 12F. Barrier metal layer 82
A wiring layer 83 made of Al or the like is formed thereon. Then, the wiring layer 83 and the barrier metal layer 82 are patterned into a predetermined pattern. In this way, the desired semiconductor device is obtained.

Also in this manufacturing method, the SiO ₂ film 77 is selectively formed in the contact hole 76 having a small aspect ratio, so that the SiO ₂ film 77 is protected by the aspect ratio when the polycrystalline silicon film 79 is etched back. The base of the contact hole 76 having a small ratio (that is, the diffusion region 7
The conductive plug 81 made of polycrystalline silicon is formed only in the contact hole 75 having a large aspect ratio without damaging 3). be able to.

Moreover, since the side wall portion 77A of the SiO ₂ film 77 is formed on the inner surface of the contact hole 75 having a large aspect ratio in the step of FIG. 10B, the side surface of the contact hole 75 is inclined, and therefore the step of FIG. 11C is performed. When the polycrystalline silicon film 79 is formed by
Is not formed in an overhang shape at the opening of the contact hole 75 and is formed with good coverage. Even in the step of FIG. 11D, the sidewall portion 79A made of the polycrystalline silicon film is formed on the side surface of the contact hole 76 having a small aspect ratio to form an inclined surface, whereby good coverage of the wiring layer 83 can be obtained.

Although FIGS. 7 to 12 of the above example show the case where the diffusion regions are formed as the bases of the contact holes 75 and 76, other conductors such as the lower wiring layer may be used. Further, as a film to be an etching stopper formed on the inner surface of the contact hole 76 having a small aspect ratio, SiO _{2 is used.}
Although the insulating film 77 such as the above is formed, a conductive film (for example, polycrystalline silicon or the like) that can have an etching selection ratio with respect to the conductive material film 79 can be used. This conductive film is required to have no alloy spike when the base is a silicon semiconductor region. When such a conductive film is used, ohmic contact can be obtained between the conductive film and the base semiconductor layer, so that it is not necessary to remove the conductive film as an etching stopper thereafter.

[0077]

According to the semiconductor device of the present invention, the contact hole having a high aspect ratio can be substantially raised by forming the contact hole so as to have the polycrystalline silicon film, and the stable contact resistance can be obtained. A semiconductor integrated circuit having a high yield or high reliability can be obtained. Therefore, it is suitable to be applied to a semiconductor device which is required for high integration and miniaturization.

Further, according to the manufacturing method of the present invention, a contact hole having a high aspect ratio can be easily filled,
The coverage of the barrier layer formed in the contact hole is also good, and a highly reliable and highly integrated semiconductor device can be manufactured.

Further, according to the manufacturing method of the present invention, it is possible to easily fill only the contact hole having the high aspect ratio without damaging the base of the contact hole having the low aspect ratio, and the coverage of the wiring is provided. It is possible to manufacture a highly integrated and highly integrated semiconductor device having high reliability.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an example of a semiconductor device of the present invention.

FIG. 2A is a process drawing showing the manufacturing method of the semiconductor device in FIG. B is a process drawing showing the manufacturing method of the semiconductor device of FIG. 1. FIG.

3C is a process drawing showing the manufacturing method of the semiconductor device in FIG. 1. FIG. D is a process drawing showing the manufacturing method of the semiconductor device of FIG. 1.

FIG. 4A is a process drawing showing another example of the method for manufacturing the semiconductor device according to the invention. B is a process drawing showing another example of the method for manufacturing a semiconductor device according to the present invention. FIG. C is a process drawing showing another example of the method for manufacturing the semiconductor device according to the invention. FIG.

FIG. 5D is a process drawing showing another example of the method for manufacturing the semiconductor device according to the invention. E is a process drawing showing another example of the method for manufacturing the semiconductor device according to the invention.

FIG. 6 is a cross-sectional view showing still another example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 7A is a process drawing showing another example of the method for manufacturing the semiconductor device according to the invention. B is a process drawing showing another example of the method for manufacturing a semiconductor device according to the present invention. FIG.

FIG. 8C is a process drawing showing another example of the method for manufacturing the semiconductor device according to the invention. D is a process drawing showing another example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 9E is a process drawing showing another example of the method for manufacturing the semiconductor device according to the invention. F is a process drawing showing another example of the method for manufacturing the semiconductor device according to the invention.

10A is a process drawing showing another example of the method for manufacturing the semiconductor device according to the invention. FIG. B is a process drawing showing another example of the method for manufacturing a semiconductor device according to the present invention. FIG.

FIG. 11 is a process drawing showing another example of the method for manufacturing a semiconductor device according to the present invention. D is a process drawing showing another example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 12E is a process drawing showing another example of the method for manufacturing the semiconductor device according to the invention. F is a process drawing showing another example of the method for manufacturing the semiconductor device according to the invention.

FIG. 13A is a process drawing showing an example of a conventional method for manufacturing a semiconductor device. B is a process drawing showing an example of a method for manufacturing a conventional semiconductor device. C is a process diagram showing an example of a conventional method for manufacturing a semiconductor device.

14A is a process diagram showing another example of the conventional method for manufacturing a semiconductor device. FIG. B is a process drawing showing another example of a method for manufacturing a conventional semiconductor device. C is a process drawing showing another example of a method for manufacturing a conventional semiconductor device. D is a process drawing showing another example of a method for manufacturing a conventional semiconductor device.

15A is a process drawing showing another example of the conventional method for manufacturing a semiconductor device. FIG. B is a process drawing showing another example of a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

21, 53, 71 Semiconductor substrate 22, 56 Polycrystalline silicon layer 23, 57 Interlayer insulating film 24, 25, 54, 55 Contact hole 26 Ti layer 27 TiON layer 28 Barrier layer 29A Blanket tungsten 29 Metal plug 30 Wiring layer 31 Semiconductor device 41 insulating layer 42 first layer Al alloy layer 43 contact hole 45 pure titanium film 46 TiAl ₃ layer 47,59 second layer Al alloy layer 48,60 TiAl ₃ intermetallic compound layer 58 titanium silicide layer 74 interlayer insulating film 75,76 Contact hole 77 SiO ₂ film 78 Photoresist layer 79 Polycrystalline silicon film 81 Conductive plug 82 Barrier metal layer 83 Wiring layer

Claims (8)

[Claims] 1. A semiconductor device having a contact hole having a large aspect ratio and a contact hole having a small aspect ratio, wherein a metal plug is provided in the contact hole.
A semiconductor device in which a base semiconductor layer is selectively provided facing the inside of the contact hole having a high aspect ratio. 2. A step of forming an interlayer insulating film after forming a base semiconductor in a portion where a contact hole having a large aspect ratio is to be formed, a step of forming a contact hole in the interlayer insulating film, and a barrier in the contact hole. Forming a layer,
A method of manufacturing a semiconductor device, comprising: a step of burying a metal in the contact hole; and a step of forming an upper conductor connected to the metal. 3. A step of forming a refractory metal film in the contact hole facing the lower conductor by a sputtering method, and a step of forming a compound of the refractory metal film and the lower conductor at the bottom of the contact hole, A method of manufacturing a semiconductor device, comprising: a step of selectively removing the refractory metal film and a step of forming an upper conductor. 4. A step of forming a pad semiconductor layer in a region where a contact hole is to be formed after forming a lower conductor, and then forming a contact hole, and a refractory metal film is formed in the contact hole facing the pad semiconductor layer by a sputtering method. Forming a film, forming a compound of the refractory metal film and the pad semiconductor layer at the bottom of the contact hole, selectively removing the refractory metal film, and forming an upper conductor A method of manufacturing a semiconductor device, comprising the steps of: 5. In a semiconductor device having a contact hole having a large aspect ratio and a contact hole having a small aspect ratio, a first film is selectively formed in the contact hole having a small aspect ratio, and then a first conductive material is formed. A step of forming a film on the entire surface, and a step of etching back the first conductive material film under the condition that the etching rate of the first film is smaller than that of the first conductive material film. Of manufacturing a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the first film is an insulating film. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the first film is a conductive film. 8. The method of manufacturing a semiconductor device according to claim 5, wherein the etch back is performed by anisotropic etching.