JPH06252256A - Manufacture of dielectric isolation type semiconductor - Google Patents

Manufacture of dielectric isolation type semiconductor

Info

Publication number
JPH06252256A
JPH06252256A JP5032229A JP3222993A JPH06252256A JP H06252256 A JPH06252256 A JP H06252256A JP 5032229 A JP5032229 A JP 5032229A JP 3222993 A JP3222993 A JP 3222993A JP H06252256 A JPH06252256 A JP H06252256A
Authority
JP
Japan
Prior art keywords
type
region
island
single crystal
crystal silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5032229A
Other languages
Japanese (ja)
Inventor
Masahiro Izumi
雅裕 泉
Fumio Kato
文男 加藤
Noriteru Furumoto
憲輝 古本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP5032229A priority Critical patent/JPH06252256A/en
Publication of JPH06252256A publication Critical patent/JPH06252256A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the decrease of impurity concentration of an impurity high concentration region formed in a part of the bottom of an island type element region after sintering, in a dielectric isolation type semiconductor device wherein single crystal silicon substrates are mutually stuck. CONSTITUTION:In the island type element region of a lateral type bipolar element 18 which has a P-type impurity high concentration region 3 in the bottom part, an oxide film 19 on the bottom surface is made thin. Hence, at the time of sintering, P-type impurities contained in glass 7 can diffuse into the P-type high concentration impurity region 3. Thereby a high concentration impurity region can be selectively formed, in a dielectric isolation type semiconductor device wherein single crystal silicon substrates are mutually stuck in a sintering process.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、スート状のガラスを用
いて単結晶シリコン基板をはり合わせることにより製造
される誘電体分離型半導体装置の製造方法に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a dielectric isolation type semiconductor device manufactured by laminating single crystal silicon substrates using soot-shaped glass.

【0002】[0002]

【従来の技術】単結晶シリコン基板上に、誘電体により
分離されたp型島状素子領域を形成するため、スート状
のガラスを介して単結晶シリコン基板をはり合わせるこ
とにより製造される誘電体分離型半導体装置で、一部の
p型島状素子領域の底面にp型不純物高濃度領域を形成
する半導体装置の従来例を図3に示し、その製造方法
を、図4に基づき説明する。図4の断面図は光結合型の
半導体リレーの半導体基板の製造方法を工程順に示すも
ので、同一基板上に、光起電力ダイオードとその制御素
子であるラテラル型バイポーラ素子を同時に形成してい
く過程を示すものである。
2. Description of the Related Art A dielectric material manufactured by laminating a single crystal silicon substrate through a soot-shaped glass to form a p-type island element region separated by a dielectric material on a single crystal silicon substrate. FIG. 3 shows a conventional example of a separation type semiconductor device in which a high concentration p-type impurity region is formed on the bottom surface of a part of the p-type island element region, and a manufacturing method thereof will be described with reference to FIG. The cross-sectional view of FIG. 4 shows a method of manufacturing a semiconductor substrate of an optically coupled semiconductor relay in the order of steps. A photovoltaic diode and a lateral bipolar element that is a control element thereof are simultaneously formed on the same substrate. It shows the process.

【0003】まず、素子形成が完了した状態を示す図3
に基づいて各部の構成を説明する。図中、17で示す島
状素子領域が光起電力ダイオードを、また、18で示す
島状素子領域がラテラル型バイポーラ素子を構成してい
る。なお、2は酸化膜、3はラテラル型バイポーラ素子
18のp型不純物高濃度領域、5は各島状素子領域を電
気的に分離すると共に、不純物の拡散を防止する分離酸
化膜、6は各素子を形成するp型島状素子領域、7はp
型不純物ボロンBを含むスート状のガラスで、焼結工程
により、単結晶シリコン基板8上にp型島状素子領域6
を固着するものである。
First, FIG. 3 showing a state in which element formation is completed.
The configuration of each part will be described based on. In the figure, the island element region indicated by 17 constitutes a photovoltaic diode, and the island element region indicated by 18 constitutes a lateral bipolar element. Reference numeral 2 is an oxide film, 3 is a high concentration p-type impurity region of the lateral type bipolar element 18, 5 is an isolation oxide film for electrically isolating each island element region and preventing diffusion of impurities, and 6 is each P-type island element region for forming an element, 7 is p
A soot-shaped glass containing a boron-type impurity boron B is formed on the single crystal silicon substrate 8 by a sintering process.
Is to be fixed.

【0004】さらに、光起電力ダイオード17は、p+
型のアノード領域9、p型のアノード領域10、n+
のカソード領域11の領域で構成され、ラテラル型バイ
ポーラ素子18は、n+ 型のエミッタ領域12、p型の
ベース領域13、n+ 型のコレクタ領域14、p+ 型の
ベース領域15の領域及びp+ 型のベース領域(p型不
純物高濃度領域3)で構成されている。16は電極であ
る。
Further, the photovoltaic diode 17 has p +
It consists in the area of type anode region 9, p-type anode region 10, n + type cathode region 11, a lateral bipolar element 18, n + -type emitter region 12, p-type base region 13, n + The collector region 14 of the p-type, the region of the p + -type base region 15, and the p + -type base region (p-type impurity high-concentration region 3). 16 is an electrode.

【0005】光起電力ダイオード17は、光電流を効率
良く取り出すために、キャリアを多く発生させなければ
ならないが、基板表面の受光面積は限られているので、
そのP型島状素子領域を厚くしてキャリア発生領域を十
分確保しなければならない。各p型島状素子領域の厚さ
は、この光起電力ダイオード17のp型島状素子領域の
厚さに合わせて一様に形成されることになる。
The photovoltaic diode 17 must generate a large number of carriers in order to efficiently extract the photocurrent, but the light receiving area of the substrate surface is limited,
The P-type island element region must be thickened to ensure a sufficient carrier generation region. The thickness of each p-type island element region will be formed uniformly according to the thickness of the p-type island element region of the photovoltaic diode 17.

【0006】一方、ラテラル型バイポーラ素子18は、
電流増幅率hFEを増加させるため、また、ベース抵抗を
低減させるために、光起電力ダイオード17に合わせて
十分厚く形成されたp型島状素子領域ではp型不純物高
濃度領域3を形成する必要がある。
On the other hand, the lateral bipolar element 18 is
In order to increase the current amplification factor h FE and to reduce the base resistance, the p-type island high concentration region 3 is formed in the p-type island element region formed to be sufficiently thick in accordance with the photovoltaic diode 17. There is a need.

【0007】次に、図4(a)〜図4(g)に基づい
て、製造過程を説明する。まず、図4(a)に示すよう
に、p型単結晶シリコン(100)基板1を熱酸化し、
p型不純物高濃度領域3を形成する部分の酸化膜2をフ
ォトリソグラフィーにより選択的に除去する。そして、
残存した酸化膜2をマスクとしてp型不純物ボロンBを
拡散またはイオン注入し、p型不純物高濃度領域3を形
成する。この時、次工程のシリコン異方性エッチングに
対してマスクとなるだけの酸化膜厚が得られるように酸
化を行う。
Next, the manufacturing process will be described with reference to FIGS. 4 (a) to 4 (g). First, as shown in FIG. 4A, the p-type single crystal silicon (100) substrate 1 is thermally oxidized,
The oxide film 2 in the portion forming the p-type impurity high concentration region 3 is selectively removed by photolithography. And
Using the remaining oxide film 2 as a mask, p-type impurity boron B is diffused or ion-implanted to form a p-type impurity high concentration region 3. At this time, oxidation is performed so that an oxide film thickness enough to serve as a mask can be obtained for the subsequent silicon anisotropic etching.

【0008】次に、図4(b)のように、フォトリソグ
ラフィーによりp型島状素子領域を分離する溝を形成す
る部分の酸化膜2を選択的に除去し、残存した酸化膜2
をマスクとしてp型単結晶シリコン(100)基板1を
異方性エッチングし、溝4を形成する。
Next, as shown in FIG. 4B, the oxide film 2 in the portion forming the groove for separating the p-type island element region is selectively removed by photolithography, and the remaining oxide film 2 is removed.
Using the mask as a mask, the p-type single crystal silicon (100) substrate 1 is anisotropically etched to form a groove 4.

【0009】次に、図4(c)のように、残存した酸化
膜2を除去した後、図4(d)のように、分離酸化膜5
を形成する。分離酸化膜5の膜厚は、p型島状素子領域
6間を電気的に分離できるだけでなく、この後の工程に
おいて、ガラス7からの不純物拡散により、光起電力ダ
イオード17の光電流が減少することのないよう、十分
な膜厚が必要である。
Next, after removing the remaining oxide film 2 as shown in FIG. 4 (c), the isolation oxide film 5 is removed as shown in FIG. 4 (d).
To form. The thickness of the isolation oxide film 5 not only allows the p-type island-shaped element regions 6 to be electrically isolated from each other, but also reduces the photocurrent of the photovoltaic diode 17 due to impurity diffusion from the glass 7 in the subsequent step. A sufficient film thickness is required so as not to occur.

【0010】次に、図4(e)のように、BCl3 、S
iCl4 、O2 等のガスを用いて、分離酸化膜5上にボ
ロンドープのスート状のガラス7を堆積させ、単結晶シ
リコン基板8をはり合わせた後、熱処理を施し焼結させ
る。
Next, as shown in FIG. 4 (e), BCl 3 , S
A boron-doped soot-like glass 7 is deposited on the isolation oxide film 5 using a gas such as iCl 4 , O 2 or the like, and a single crystal silicon substrate 8 is bonded thereto, followed by heat treatment and sintering.

【0011】次に、図4(f)のように、半導体基板を
裏返して、所定厚さの分離酸化膜5が露出するまでp型
単結晶シリコン(100)基板1を研磨して、p型島状
素子領域6を有する誘電体分離型基板を作成する。
Next, as shown in FIG. 4F, the semiconductor substrate is turned upside down, and the p-type single crystal silicon (100) substrate 1 is polished until the isolation oxide film 5 having a predetermined thickness is exposed. A dielectric isolation type substrate having island-shaped element regions 6 is prepared.

【0012】最後に、図3のように、p型不純物高濃度
領域3を有するp型島状素子領域にラテラル型バイポー
ラ素子18の各領域を、p型不純物高濃度領域3を有し
ないp型島状素子領域に光起電力ダイオード17の各領
域を形成した後、電極16及び酸化膜2を形成する。
Finally, as shown in FIG. 3, each region of the lateral bipolar element 18 is provided in the p-type island element region having the p-type impurity high concentration region 3 and the p-type impurity high-concentration region 3 is not provided. After forming each region of the photovoltaic diode 17 in the island element region, the electrode 16 and the oxide film 2 are formed.

【0013】[0013]

【発明が解決しようとする課題】ところが、上述の焼結
工程は、1200℃以上の高温にて長時間の処理が必要
となるので、p型不純物高濃度領域3の不純物は拡散
し、その濃度が低下してしまう。そのため、p型不純物
高濃度領域3の抵抗が増加してしまうという問題点があ
った。上述の従来例では、ラテラル型バイポーラ素子1
8のベース抵抗が増加することになる。
However, since the above-mentioned sintering process requires treatment at a high temperature of 1200 ° C. or higher for a long time, impurities in the p-type impurity high-concentration region 3 diffuse and the concentration thereof increases. Will decrease. Therefore, there is a problem that the resistance of the p-type impurity high concentration region 3 increases. In the above-mentioned conventional example, the lateral bipolar element 1
8 will increase the base resistance.

【0014】本発明は、上記問題点に鑑みなされたもの
で、その目的とするところは、単結晶シリコン基板をは
り合わせる誘電体分離型半導体装置において、焼結工程
後、一部の島状素子領域底部に形成した不純物高濃度領
域の不純物濃度が低下するのを防止することができる誘
電体分離型半導体装置の製造方法を提供することにあ
る。
The present invention has been made in view of the above problems. An object of the present invention is to provide a dielectric isolation type semiconductor device in which single crystal silicon substrates are attached to each other, and a part of the island-shaped element is formed after the sintering step. It is an object of the present invention to provide a method of manufacturing a dielectric isolation type semiconductor device capable of preventing the impurity concentration of a high impurity concentration region formed at the bottom of a region from decreasing.

【0015】[0015]

【課題を解決するための手段】上記課題を解決するため
本発明の誘電体分離型半導体装置の製造方法は、第一導
電型(p型)の単結晶シリコン基板の表面に溝を形成す
る工程と、その溝が形成された一方の主表面に分離絶縁
膜を形成する工程と、前記一方の主表面に第一導電型の
不純物を含むガラスを堆積する工程と、前記単結晶シリ
コン基板に前記ガラスを介して別の単結晶シリコン基板
をはり合わせて熱処理する工程と、前記溝を形成した単
結晶シリコン基板の他方の主表面から前記分離絶縁膜が
露出するまで研磨して、複数の島状素子領域を形成する
工程を有する誘電体分離型半導体装置の製造方法におい
て、前記分離絶縁膜を形成する工程は、第一導電型の不
純物高濃度領域を底部に形成した一部の島状素子領域
で、熱処理時、前記ガラス中の不純物が前記不純物高濃
度領域に拡散できるように、前記島状素子領域底面の分
離絶縁膜のみ相対的に薄く形成する工程であることを特
徴とするものである。
In order to solve the above problems, a method of manufacturing a dielectric isolation type semiconductor device according to the present invention is a step of forming a groove on the surface of a first conductivity type (p type) single crystal silicon substrate. A step of forming an isolation insulating film on the one main surface in which the groove is formed, a step of depositing glass containing impurities of the first conductivity type on the one main surface, and a step of depositing glass on the single crystal silicon substrate. Bonding another single crystal silicon substrate through glass and heat-treating, and polishing until the separation insulating film is exposed from the other main surface of the single crystal silicon substrate in which the groove is formed, to form a plurality of island shapes. In the method of manufacturing a dielectric isolation type semiconductor device having a step of forming an element region, the step of forming the isolation insulating film includes the step of forming a part of the island-shaped element region in which a high-concentration impurity region of the first conductivity type is formed at the bottom. At the time of heat treatment, As impurities in Las can diffuse into the high impurity concentration region, and is characterized in that said island-like element region bottom surface of the isolation insulating film only relatively thin to process.

【0016】[0016]

【作用】堆積させたガラスに含まれるp型不純物は、焼
結時、p型不純物高濃度領域を底部に形成したp型島状
素子領域の底面の薄い分離用絶縁膜を介してp型不純物
高濃度領域に拡散する。
When the p-type impurities contained in the deposited glass are sintered, the p-type impurities pass through the thin insulating film for isolation at the bottom surface of the p-type island element region formed at the bottom of the p-type impurity high concentration region during sintering. Diffuse in high concentration area.

【0017】[0017]

【実施例】本発明の誘電体分離型半導体装置の製造方法
を図2に基づいて説明し、素子形成後の断面図を図1に
示す。従来例と異なる構成は、p型不純物高濃度領域を
底部に形成したp型島状素子領域の底面の薄い酸化膜
と、それを形成するのに用いるシリコン窒化膜のみであ
るので、前記従来例と同等の構成については、同符号を
付すこととし、詳細な説明を省略する。以下の実施例で
は、p型島状素子領域にp型不純物高濃度領域を形成す
る場合を示すが、n型島状素子領域にn型不純物高濃度
領域を形成する場合も同様である。但し、この場合は、
リンP等のn型不純物をドープしたガラスを用いなけれ
ばならない。p型不純物の種類についても、ボロンBに
限定されるものではない。
EXAMPLE A method for manufacturing a dielectric isolation type semiconductor device of the present invention will be described with reference to FIG. 2, and a sectional view after element formation is shown in FIG. The configuration different from the conventional example is only the thin oxide film on the bottom surface of the p-type island element region having the p-type impurity high-concentration region formed at the bottom and the silicon nitride film used to form the thin oxide film. The same reference numerals are given to the same configurations as, and detailed description will be omitted. In the following examples, the case where the p-type impurity high concentration region is formed in the p-type island-shaped element region is shown, but the same applies to the case where the n-type impurity high concentration region is formed in the n-type island-shaped element region. However, in this case,
Glass doped with n-type impurities such as phosphorus P must be used. The type of p-type impurities is not limited to boron B either.

【0018】まず、図2(a)に示すように、p型単結
晶シリコン(100)基板1を熱酸化し、p型不純物高
濃度領域3を形成する部分の酸化膜2をフォトリソグラ
フィーにより選択的に除去する。そして、残存した酸化
膜2をマスクとしてのp型不純物ボロンBを拡散または
イオン注入し、p型不純物高濃度領域3を形成する。こ
の時、周辺のp型島状素子領域と電気的に分離できるだ
けの酸化膜厚が得られるように酸化を行い、酸化膜19
を形成する。光起電力ダイオード17と、その制御素子
となるラテラル型バイポーラ素子18などの低耐圧素子
を形成するときは、この酸化膜19の厚さは、1μm程
度あれば十分である。また、酸化膜19の厚さが1μm
程度であれば、基板はり合わせの焼結工程において、ガ
ラス7よりp型不純物高濃度領域3へボロンをドーピン
グすることができる。
First, as shown in FIG. 2A, the p-type single crystal silicon (100) substrate 1 is thermally oxidized to select the oxide film 2 in the portion where the p-type impurity high concentration region 3 is to be formed by photolithography. To remove it. Then, the p-type impurity boron B is diffused or ion-implanted using the remaining oxide film 2 as a mask to form the p-type impurity high concentration region 3. At this time, oxidation is performed so as to obtain an oxide film thickness that can be electrically separated from the surrounding p-type island element region, and the oxide film 19 is formed.
To form. When forming the photovoltaic diode 17 and the low breakdown voltage element such as the lateral type bipolar element 18 which serves as a control element thereof, it is sufficient that the thickness of the oxide film 19 is about 1 μm. The thickness of the oxide film 19 is 1 μm.
As long as it is approximately, the p-type impurity high-concentration region 3 can be doped with boron from the glass 7 in the substrate-bonding sintering step.

【0019】次に、図2(b)に示すように、シリコン
窒化膜20を堆積させた後、図2(c)のように、p型
不純物高濃度領域3上の酸化膜19上部のシリコン窒化
膜を、フォトリソグラフィーにより選択的に残す。
Next, as shown in FIG. 2 (b), after depositing a silicon nitride film 20, as shown in FIG. 2 (c), silicon on the oxide film 19 on the p-type impurity high-concentration region 3 is deposited. The nitride film is selectively left by photolithography.

【0020】次に、図2(d)に示すように、フォトリ
ソグラフィーにより、溝を形成する部分の酸化膜2を選
択的に除去し、残存した酸化膜2とシリコン窒化膜20
をマスクとして、p型単結晶シリコン(100)基板1
を異方性エッチングし、溝4を形成する。残存した酸化
膜2は図2(e)に示すように除去しておく。
Next, as shown in FIG. 2D, the oxide film 2 in the portion where the groove is to be formed is selectively removed by photolithography, and the remaining oxide film 2 and silicon nitride film 20 are removed.
P-type single crystal silicon (100) substrate 1 using the as a mask
Is anisotropically etched to form the groove 4. The remaining oxide film 2 is removed as shown in FIG.

【0021】その後、図2(f)に示すように、ガラス
からp型不純物ボロンがp型島状素子領域6へ拡散しな
いように十分な厚さの分離酸化膜5を形成する。この
時、酸化膜19はシリコン窒化膜20により覆われてい
るので、酸化膜19の膜厚はほとんど増加しない。
Thereafter, as shown in FIG. 2F, an isolation oxide film 5 having a sufficient thickness is formed so that the p-type impurity boron is not diffused from the glass into the p-type island-shaped element region 6. At this time, since the oxide film 19 is covered with the silicon nitride film 20, the film thickness of the oxide film 19 hardly increases.

【0022】次に、図2(g)に示すように、分離酸化
膜5上にボロンドープのスート状のガラス7を堆積さ
せ、単結晶シリコン基板8をはり合わせた後、熱処理を
施し焼結させる。この時、ガラス7より酸化膜19を介
して、p型不純物高濃度領域3へボロンがドープされる
ので、p型不純物高濃度領域3に元来ドープされていた
p型不純物が拡散しても、p型不純物高濃度領域3のp
型不純物濃度は低下しない。
Next, as shown in FIG. 2 (g), a boron-doped soot-like glass 7 is deposited on the isolation oxide film 5, and a single crystal silicon substrate 8 is bonded thereto, followed by heat treatment and sintering. . At this time, since boron is doped from the glass 7 into the p-type impurity high-concentration region 3 through the oxide film 19, even if the p-type impurity originally doped in the p-type impurity high-concentration region 3 is diffused. , P of the p-type impurity high concentration region 3
The type impurity concentration does not decrease.

【0023】図5にp型不純物高濃度領域3を形成した
p型島状素子領域における厚さ方向のp型不純物濃度分
布を示す。図5で横軸は島状素子領域の底面からの距離
を示し、縦軸はp型不純物の濃度を示している。図5
(a)は前記従来の製造方法による場合、図5(b)が
本発明の製造方法による場合である。図5(a)に比
べ、図5(b)では、p型島状素子領域の底面のp型不
純物濃度が高くなっているのがわかる。
FIG. 5 shows a p-type impurity concentration distribution in the thickness direction in the p-type island element region in which the p-type impurity high concentration region 3 is formed. In FIG. 5, the horizontal axis represents the distance from the bottom surface of the island element region, and the vertical axis represents the p-type impurity concentration. Figure 5
5A shows the case of the conventional manufacturing method, and FIG. 5B shows the case of the manufacturing method of the present invention. It can be seen that the p-type impurity concentration on the bottom surface of the p-type island element region is higher in FIG. 5 (b) than in FIG. 5 (a).

【0024】次の工程として図2(h)に示すように、
半導体基板を裏返して、所定厚さの分離酸化膜5が露出
するまで、p型単結晶シリコン(100)基板1を研磨
して、p型島状素子領域6を有する誘電体分離基板を作
成する。
As the next step, as shown in FIG.
The semiconductor substrate is turned over and the p-type single crystal silicon (100) substrate 1 is polished until the isolation oxide film 5 having a predetermined thickness is exposed to form a dielectric isolation substrate having the p-type island element region 6. .

【0025】最後に、図1に示すように、p型不純物高
濃度領域3を有するp型島状素子領域には、ラテラル型
バイポーラ素子18を、p型不純物高濃度領域3を有し
ないp型島状素子領域には、光起電力ダイオード17を
前記の従来例と同様に形成して完成する。
Finally, as shown in FIG. 1, in the p-type island-shaped element region having the p-type impurity high-concentration region 3, the lateral bipolar element 18 and the p-type impurity high-concentration region 3 having no p-type impurity high-concentration region 3 are provided. The photovoltaic diode 17 is formed in the island-shaped element region in the same manner as in the above-mentioned conventional example to complete the process.

【0026】[0026]

【発明の効果】以上のように構成することで、高温で長
時間の焼結工程の際、ガラスに含まれる不純物を薄い酸
化膜を介して拡散させることにより、ガラスを用いて単
結晶シリコン基板をはり合わせる誘電体分離型半導体装
置においても、高濃度の不純物ドープ領域を選択的に形
成することができる。実施例の場合には、光起電力ダイ
オードの性能を低下させることなく、その制御素子であ
るラテラル型バイポーラ素子のベース抵抗の増加を防止
することができる。
With the above-mentioned structure, the impurities contained in the glass are diffused through the thin oxide film during the sintering process at a high temperature for a long time, so that the single crystal silicon substrate is made of glass. Also in the dielectric isolation type semiconductor device in which the above are bonded together, the high-concentration impurity-doped region can be selectively formed. In the case of the embodiment, it is possible to prevent an increase in the base resistance of the lateral bipolar element, which is the control element, without deteriorating the performance of the photovoltaic diode.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の誘電体分離型半導体装置の断
面図である。
FIG. 1 is a sectional view of a dielectric isolation type semiconductor device of an embodiment of the present invention.

【図2】本発明の実施例の製造方法を工程順に示した誘
電体分離型半導体装置の断面図である。
FIG. 2 is a cross-sectional view of a dielectric isolation type semiconductor device showing a manufacturing method according to an embodiment of the present invention in the order of steps.

【図3】従来例の誘電体分離型半導体装置の断面図であ
る。
FIG. 3 is a sectional view of a conventional dielectric isolation type semiconductor device.

【図4】従来例の製造方法を工程順に示した誘電体分離
型半導体装置の断面図である。
FIG. 4 is a cross-sectional view of a dielectric isolation type semiconductor device showing a manufacturing method of a conventional example in the order of steps.

【図5】p型不純物高濃度領域を有するp型島状素子領
域の厚さ方向のp型不純物濃度分布を示すグラフであ
り、(a)は従来の製造方法による場合、(b)は本発
明の製造方法による場合である。
FIG. 5 is a graph showing a p-type impurity concentration distribution in the thickness direction of a p-type island-shaped element region having a p-type impurity high-concentration region, where (a) is a conventional manufacturing method and (b) is a This is the case according to the manufacturing method of the invention.

【符号の説明】[Explanation of symbols]

1 p型単結晶シリコン(100)基板 2 酸化膜 3 p型不純物高濃度領域 4 溝 5 分離酸化膜 6 p型島状素子領域 7 ガラス 8 単結晶シリコン基板 9 p+ 型アノード領域 10 p型アノード領域 11 n+ 型カソード領域 12 n+ 型エミッタ領域 13 p型ベース領域 14 n+ 型コレクタ領域 15 p+ 型ベース領域 16 電極 17 光起電力ダイオード 18 ラテラル型バイポーラ素子 19 酸化膜 20 シリコン窒化膜1 p-type single crystal silicon (100) substrate 2 oxide film 3 p-type impurity high concentration region 4 groove 5 isolation oxide film 6 p-type island element region 7 glass 8 single-crystal silicon substrate 9 p + type anode region 10 p-type anode Region 11 n + type cathode region 12 n + type emitter region 13 p type base region 14 n + type collector region 15 p + type base region 16 electrode 17 photovoltaic diode 18 lateral type bipolar device 19 oxide film 20 silicon nitride film

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/73 // H01L 27/14 31/10 8422−4M H01L 31/10 A ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical display area H01L 29/73 // H01L 27/14 31/10 8422-4M H01L 31/10 A

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第一導電型の単結晶シリコン基板の一方
の主表面に溝を形成する工程と、その主表面に分離絶縁
膜を形成する工程と、前記主表面に第一導電型の不純物
を含むガラスを堆積する工程と、前記単結晶シリコン基
板に前記ガラスを介して別の単結晶シリコン基板をはり
合わせて熱処理する工程と、前記溝を形成した単結晶シ
リコン基板の他方の主表面から前記分離絶縁膜が露出す
るまで研磨して、複数の島状素子領域を形成する工程を
有する誘電体分離型半導体装置の製造方法において、前
記分離絶縁膜を形成する工程は、第一導電型の不純物高
濃度領域を底部に形成した一部の島状素子領域で、熱処
理時、前記ガラス中の不純物が前記不純物高濃度領域に
拡散できるように、前記島状素子領域底面の分離絶縁膜
のみ相対的に薄く形成する工程であることを特徴とする
誘電体分離型半導体装置の製造方法。
1. A step of forming a groove on one main surface of a first conductivity type single crystal silicon substrate, a step of forming an isolation insulating film on the main surface, and an impurity of the first conductivity type on the main surface. A step of depositing a glass containing, a step of heat-treating another single crystal silicon substrate to the single crystal silicon substrate via the glass, and from the other main surface of the single crystal silicon substrate in which the groove is formed. In the method of manufacturing a dielectric isolation type semiconductor device, which comprises a step of polishing until the isolation insulating film is exposed to form a plurality of island-shaped element regions, the step of forming the isolation insulating film is of a first conductivity type. In a part of the island-shaped element region having a high-concentration impurity region formed at the bottom, only the isolation insulating film on the bottom surface of the island-shaped element region is aligned so that the impurities in the glass can diffuse into the high-concentration impurity region during heat treatment. Thin shape A method for manufacturing a dielectric isolation type semiconductor device, comprising the steps of:
JP5032229A 1993-02-22 1993-02-22 Manufacture of dielectric isolation type semiconductor Pending JPH06252256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5032229A JPH06252256A (en) 1993-02-22 1993-02-22 Manufacture of dielectric isolation type semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5032229A JPH06252256A (en) 1993-02-22 1993-02-22 Manufacture of dielectric isolation type semiconductor

Publications (1)

Publication Number Publication Date
JPH06252256A true JPH06252256A (en) 1994-09-09

Family

ID=12353147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5032229A Pending JPH06252256A (en) 1993-02-22 1993-02-22 Manufacture of dielectric isolation type semiconductor

Country Status (1)

Country Link
JP (1) JPH06252256A (en)

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