JPH06250915A - Extension storage control system - Google Patents

Abstract

PURPOSE:To reduce the amount of materials and to improve the performance of a data processor by providing a synchronization buffer and a data accumulation buffer. CONSTITUTION:More than one clusters 1 having processors, main storage devices and storage controllers and an extension storage device 2 connected to more than one clusters 1 are provided. Data is asynchronously transferred between the clusters 1 and the extension storage device 2. In such a case, the data accumulation buffer 6 accumulates data synchronized by the synchronization buffer 5 when the synchronization buffer 5 synchronizes input data by a self clock in an interface between the extension storage device 2 and the clusters 1. Namely, data can be synchronized and the amount of the materials can be reduced by providing the synchronization buffer 5 and the data accumulation buffer 6 even if the extension storage device 2 and the clusters 1 are asynchronous.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an extended storage device for controlling an extended storage device to transfer data between one or more clusters having a processing device, a main storage device and a storage control device and the extended storage device. Regarding control method.

[0002]

2. Description of the Related Art In recent years, a data processing device is provided with a large-capacity expanded storage device in addition to a main storage device in order to improve data processing efficiency and speed up processing. This extended storage device forms a storage hierarchy with the main storage device.

In the data processing device, a plurality of clusters each having a processing device, a main storage device, and a storage control device are provided, and each cluster is connected to the extended storage device. In order to improve the processing efficiency by maintaining a good load balance between the cluster and the reliability of this device,
A shared extended storage device may be provided instead of the extended storage device.

Here, for example, when the clock for data transfer in the cluster and the clock for data transfer in the extended storage device are asynchronous, the data transmission side or the reception side uses the clock of its own cluster. The data needed to be synchronized. This data synchronization may be performed on either side of the cluster or the extended storage device, or on both sides of the cluster and the extended storage device. (1) First, FIG. 8 shows an example in which data is synchronized on either side of the cluster or the extended storage device. When the extended storage device 2a is the transmitting side, the synchronization is performed in the receiving side cluster 1a. Data is transferred from the flip-flop 22 (hereinafter referred to as FF) to the buffer 2
3 is sent.

In the cluster 1a, the buffer 23 is driven by the clock (eg, 12 ns) of the clock generator 21. Then, when a plurality of blocks of data are stored in the queue in the buffer 23, the data is read from the buffer 23 to the main storage device by the clock (for example, 6 ns) on the receiving side.

Next, when the cluster 1a is the transmitting side, synchronization is performed in the extended storage device 2a which is the receiving side. When the data is sent from the FF 25 to the buffer 26, the expansion storage device 2a drives the buffer 26 by the clock (for example, 6 ns) of the clock generator 24. Then, the data is stored in the buffer 26, and the data is read from the buffer 26 according to the clock (for example, 12 ns) on the receiving side. (2) Next, data synchronization is performed by the cluster 1b.
9A and 9B show an example in which it is performed on both sides of the extended storage device 2b. This method is used when the clock of the cluster 1b, the clock of the transmission line 50 for data transfer, and the clock of the extended storage device 2b are different from each other. In this case, the buffer 27 is provided in front of the FF 22, the data is written to the buffer 27 at the clock (for example, 12 ns) of the expansion storage device 2b, and the data is read from the buffer 27 to the FF 22 at the clock of the transmission path 50 (for example, 7 ns). .

Further, a buffer 28 is provided in front of the FF 25, and the buffer 28 is provided at the clock (6 ns) of the cluster 1b.
Write data to the transmission line 50 clock (7ns)
The data is read from the buffer 28 to the FF 25 with. In this way, the data can be synchronized.

Next, FIG. 10 shows a configuration for writing data in the buffer so as not to overflow it. The data is sent from the FF 22 in the cluster 1c to the FF 29, for example, and the data in the FF 29 is written in a plurality of queues (not shown) in the buffer 23 at the clock of the clock generator 21. At this time, the write counter 31
It is incremented each time data is written to the queue based on the clock.

When the buffer 23 is filled with data, the read counter 32 reaches a predetermined count value based on the output of the write counter 31. The read counter 32 reads the data from the buffer 23 to the FF 30, and sends a signal (buffer full signal) notifying that the buffer 23 is full to the transmission inhibiting unit 33.

Since the transmission suppressing unit 33 suppresses the transmission by using the buffer full signal as a trigger, the data can be transferred without the buffer 23 overflowing.

It is to be noted that the buffer 23 needs to have a storage area for fetching data such as a communication path already transmitted when transmission is suppressed.

[0012]

However, as the scale of computer systems has increased, it has become necessary to extend the transfer distance between the cluster and the extended storage device. For this reason, the number of data elements transmitted until the data transfer is suppressed after the buffer full signal is transmitted increases. Therefore, although the required capacity of the buffer 23 is increased, storing the data in the FF 29 is expensive.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an extended storage control system capable of reducing the physical quantity and improving the performance of a data processing device. .

[0014]

In order to solve the above problems and achieve the object, the present invention has the following constitution. FIG. 1 shows the principle of the present invention. The present invention transfers a large amount of data by providing a synchronization buffer and a data storage buffer. Also, the physical quantity is reduced by sharing the two buffers.

That is, the present invention is provided with one or more clusters 1 each having a processing device, a main storage device, and a storage control device, and an extended storage device 2 connected to one or more clusters 1. Data transfer is asynchronously performed with the storage device 2.

The cluster 1 or the extended storage device 2 has a synchronizing buffer 5 for synchronizing the input data with its own clock, and stores the data synchronized by the synchronizing buffer 5. And a data storage buffer 6.

Here, when the cluster 1 or the expansion storage device 2 outputs data, it is preferable to use the data storage buffer 6 as a buffer for storing fetch data of its own device.

Further, there is provided one or more clusters 1 each having a processing device, a main storage device, and a storage control device, and an extended storage device 2 connected to the one or more clusters 1, and the cluster 1 and the extended storage device. Data is asynchronously transferred between the two.

The cluster 1 or the expansion storage device 2 has a data storage buffer 6 for storing output data, and a synchronization for synchronizing the data stored in the data storage buffer 6 with another clock. And a buffer 5 for conversion.

The synchronization buffer 5 has a plurality of queues 51, and data is written in each queue 51 by another clock and read out from each queue 51 by its own clock.

The synchronization buffer 5 has a plurality of queues 51, and data is written in each queue 51 by its own clock and read from each queue 51 by another clock.

The data storage buffer 6 includes an odd number memory 61 for storing an odd number of data among the plurality of queues 51, and an even number memory 62 for storing an even number of data among the plurality of queues 51. And storing data in one memory, the data is read from the other memory.

Here, the odd memory 61 and the even memory 62
Can be exemplified by a random access memory or the like.
Furthermore, when writing data to the plurality of queues 51, a write counter 31 for counting the number of times of writing may be provided.

Further, a read counter 32 for reading data from the plurality of queues 51 when data writing to the plurality of queues 51 is completed may be provided.

[0025]

According to the present invention, the extended storage device 2 and the cluster 1 are provided.
In the interface between and, when the synchronization buffer 5 synchronizes the input data with its own clock, the data storage buffer 6 stores the data synchronized by the synchronization buffer 5.

That is, even if the extended storage device 2 and the cluster 1 are asynchronous, by providing the synchronization buffer 5 and the data storage buffer, the data can be synchronized and the physical quantity can be reduced. it can. Therefore,
The major point is to improve the price / performance ratio of computer systems.

Further, since the data storage buffer 6 is used as a buffer for storing the fetch data of its own device, the buffer for the fetch data becomes unnecessary and the physical quantity can be reduced.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the extended storage control system according to the present invention will be described below. FIG. 2 is a configuration block diagram of the first embodiment of the data processing device for realizing the extended storage control method. <Structure of Embodiment 1> In FIG. 2, the data processing device is provided with a plurality of clusters 1-1 to 1-n, and these plurality of clusters 1-1 to 1-n are connected to the extended storage device 2. It Each cluster 1 has a central processing unit 11, a main storage unit 13, and a storage control unit 12 that controls the main storage unit 13. With such a configuration, data transfer is performed between each of the clusters 1-1 to 1-n and the extended storage device 2. Further, the clocks in each of the clusters 1-1 to 1-n and the clock in the extended storage device 2 are asynchronous.

FIG. 3 is a circuit diagram of a part of the cluster 1 and the extended storage device 2. In the data input circuit 3 shown in FIG. 3, the cluster 1 is the data transmitting side and the extended storage device 2 is the data receiving side here. Cluster 1
May be the data receiving side and the extended storage device 2 may be the data transmitting side.

Cluster 1 is FF2 that stores data
2. It has a clock generator 21 that sends a clock to the extended storage device, and a transmission suppression unit 33 that inputs a buffer full signal from the extended storage device 2.

The data input circuit 3 in the extended storage device 2 is
FF 29, synchronization buffer 5, data storage buffer 6, write counter 31, read counters 32, 3
Have four.

The FF 29 stores the data from the FF 22 at the clock of the clock generator 21. The synchronization buffer 5 uses the clock of the clock generator 21 to generate FF2.
The data is read from 9 and written inside.

FIG. 4 is a detailed configuration diagram of the synchronization buffer and the data storage buffer. Synchronization buffer 5
Is configured to have a plurality of queues 51, and stores the block-unit data from the FF 29 in each queue 51.

The data storage buffer 6 comprises an odd random access memory 61 (hereinafter referred to as ODD RAM) and an even random access memory 62 (hereinafter referred to as EVEN RAM).

The selector 7 is an ODD RAM 61 and an EVE.
The N RAM 62 is selected alternately, and the selector 8 operates complementarily to the selector 7 to operate the ODD RAM 61 and the EV.
ENRAM 62 is selected alternately. Therefore, ODD
The RAM 61 stores the data of the odd-numbered queues 51 in order, and the EVEN RAM 62 stores the data of the even-numbered queues 51 in order. When writing data to one RAM, the data is read from the other RAM.

The write counter 31 counts each time data is written in the queue based on the clock of the clock generator 21. The read counter 32 reads the data from the plurality of queues 51 in the synchronization buffer 5 at the clock of the receiving side based on the output from the write counter 31 and writes the data in the data storage buffer 6.

The read counter 34 includes an ODD RAM 61 and an EVEN RAM 6 in the data storage buffer 6.
The data stored in 2 is read based on the output of the read counter 32. <Process of First Embodiment> FIG. 5 is a process flow of the extended storage control method. Next, the data input circuit 3 in the extended storage device 2
The process will be described with reference to FIG. Note that the processing of the data input circuit 3 in the cluster 1 is also similar to the processing of the input circuit in the expansion storage device 2, and therefore its explanation is omitted.

First, a plurality of blocks of data from the FF 22 are written in the FF 29 at the clock of the clock generator 21 (step 101). Further, the plurality of blocks of data written in the FF 29 are sequentially written in the plurality of queues 51 in the synchronization buffer 5 (step 10).
2).

At this time, each time a block is written in the queue 51, the write counter 31 increments the count value. Then, it is determined whether or not the writing to the queue 51 is completed in a certain block (step 103), and when the writing is completed, the writing counter 31 outputs a writing completion signal to the reading counter 3
2 (step 104).

Then, the read counter 32 operates by receiving the write completion signal and synchronizes the data with the clock on the receiving side (step 105). Then, by selectively operating the selector 7, the plurality of blocks of data written in the plurality of queues 1 of the synchronization buffer 5 are transferred to the ODD RAM 6 in the data storage buffer 6.
1 and EVEN RAM 62 are alternately written (step 106).

Further, when the selector 8 is operated complementarily to the selector 7 and data is being written in one RAM, the data is read from the other RAM (step 107).

Then, it is judged whether or not all the writing and reading processes have been completed (step 108), and if all the writing and reading processes have not been completed,
The process returns to step 101, and the processes after step 101 are repeated. On the other hand, when all the writing and reading processes are completed, the process is completed.

As described above, according to the first embodiment, in the interface between the extended storage device 2 and the cluster 1,
The synchronization buffer 5 and the storage buffer 6 are provided, and all operations in the data storage buffer 6 are performed by the clock on the receiving side.

As a result, R is stored in the data storage buffer 6.
AM can be used, and the physical quantity can be reduced as compared with the case of using FF. Moreover, there are many places where the price / performance ratio of the computer system is improved. <Embodiment 2> FIG. 6 is a block diagram showing the construction of Embodiment 2 of the present invention. In the second embodiment, the data storage buffer 6 is shared for data transmission and reception in the cluster 1. The cluster 1 has a buffer FF 29, a synchronization buffer 5, a data storage buffer 6, a write counter 31, read counters 32 and 34, and an FF 35.

When receiving input data, the first embodiment is used.
Perform the same processing as. That is, the FF 29 takes in the input data and writes the data in the synchronization buffer 5 with a clock. At this time, the write counter 31 counts each time a block is written in the queue 51.

When the writing is completed, the writing counter 31 outputs the writing completion signal to the reading counter 32, and the reading counter 32 operates by receiving the writing completion signal and synchronizes the data by the receiving side clock. Turn into.

Further, the data of a plurality of blocks written in a plurality of queues are transferred to the OD in the data storage buffer 6.
The data is written in the D RAM 61 and the EVEN RAM 62 alternately.

Furthermore, when data is being written in one RAM, the data is read from the other RAM to the main memory device 13. On the other hand, when outputting data, the data from the main storage device 13 is stored in the data storage buffer 6 at the clock of the read counter 32, and then the data storage buffer 34 at the clock of the read counter 34.
Data is read from 6. And the data is FF3
It is sent to the extended storage device 2 via 5.

That is, the data storage buffer 6 can write or read data according to the clock on the receiving side. On the other hand, in the conventional output transfer interface, the data fetched in the main storage device 13 must be temporarily stored in the fetch buffer, and then the data must be sent from the fetch buffer to the expansion storage device 2. This is because the fetch throughput and the transmission throughput of the main storage device 13 are different.

Therefore, according to the second embodiment, by sharing the data storage buffer 6 and the fetch buffer, a buffer for fetch data becomes unnecessary,
A large amount of material can be reduced. <Structure of Third Embodiment> In the first embodiment, the present invention is applied to the data input circuit 3, but the third embodiment is applied to the data output circuit 4. FIG. 8 shows the data output circuit 4 of the third embodiment.
It is a configuration block diagram of. The data output circuit 4 may be provided in either the extended storage device 2 or the cluster 1.

The data output circuit 4 has a data storage buffer 6, a synchronization buffer 5, an FF 29, a write counter 31, and read counters 32 and 34. When outputting data from the cluster 1 to the extended storage device 2 or when outputting from the extended storage device 2 to the cluster 1,
The data output circuit 4 performs the following processing.

First, the ODD in the data storage buffer 6
Data is alternately stored in the RAM 61 and the EVEN RAM 62. Further, the write counter 31 has data R
Every time it is written in AM, it is counted. Then, the read counter 32 reads the data from the data storage buffer 6 based on the write completion signal of the write counter 31 and writes the data in the synchronization buffer 5.

Further, the queue 5 in the synchronization buffer 5
When the writing of data to 1 is completed, the read counter 3
4 reads data from the synchronization buffer 5. And
The data is written in the FF 29, and further the data is sent out from the FF 29. The above operation is performed by the reception clock.

Thus, also in the data output circuit 4,
The same effect as the data input circuit 3 can be obtained.

[0055]

According to the present invention, the physical quantity can be reduced by providing the synchronization buffer and the data storage buffer in the interface between the extended storage device and the cluster. This greatly improves the price / performance ratio of the computer system.

Further, since the data storage buffer is used as a buffer for storing the fetched data of its own device, the buffer for the fetched data becomes unnecessary and the physical quantity can be reduced.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration block diagram of a first embodiment of a data processing device for realizing an extended storage control system according to the present invention.

FIG. 3 is a configuration block diagram of an extended storage control system according to the first embodiment.

FIG. 4 is a diagram illustrating a synchronization buffer and a data storage buffer according to the first embodiment.

FIG. 5 is a processing flow of the extended storage control method according to the first embodiment.

FIG. 6 is a configuration block diagram of a second embodiment.

FIG. 7 is a configuration block diagram of a third embodiment.

FIG. 8 is a configuration block diagram showing an example of conventional data synchronization.

FIG. 9 is a configuration block diagram showing another example of conventional data synchronization.

FIG. 10 is a configuration block diagram showing a conventional extended storage control method.

[Explanation of symbols]

 1 ... Cluster 2 ... Expansion storage device 3 ... Data input circuit 4 ... Data output circuit 5 ... Synchronization buffer 6 ... Data storage buffer 7, 8 ... Selector 11 ... Central processing unit 12 ... Storage controller 13 Main memory 21, 24 Clock generator 22, 25, 29, 30 Flip flop 23, 26, 27, 28 Buffer 31 Write counter 32, 34 Read Counter 33..Transmission suppression unit 51..Queue 61..ODD RAM 62..EVEN RAM

Claims (6)

[Claims] 1. A system comprising: one or more clusters (1) having a processing device, a main storage device, and a storage control device; and an extended storage device (2) connected to the one or more clusters (1), In a data processing device for asynchronously transferring data between a cluster (1) and an extended storage device (2), the cluster (1) or the extended storage device (2) synchronizes input data with its own clock. An extended storage control method, comprising: a synchronization buffer (5) for storing the data and a data storage buffer (6) for storing the data synchronized by the synchronization buffer (5). 2. When the cluster (1) or the extended storage device (2) outputs data, the data storage buffer (6) is used as a buffer for storing fetch data of its own device. Claim 1 characterized by
The extended storage control method described. 3. A storage device comprising: one or more clusters (1) having a processing device, a main storage device, and a storage control device; and an extended storage device (2) connected to the one or more clusters (1). In a data processing device for asynchronously transferring data between a cluster (1) and an extended storage device (2), the cluster (1) or the extended storage device (2) is for data storage for storing output data. An extended storage control system comprising a buffer (6) and a synchronization buffer (5) for synchronizing data stored in the data storage buffer (6) with another clock. 4. The synchronization buffer (5) has a plurality of queues (51), and data is stored in each queue (5).
2. The extended storage control system according to claim 1, wherein the extended storage control method is written in 1) by another clock and is read from each queue (51) by its own clock. 5. The synchronization buffer (5) has a plurality of queues (51), and data is stored in each queue (5).
4. The extended storage control system according to claim 3, wherein the extended storage control method is written in 1) with its own clock and read from each queue (51) with another clock. 6. The data storage buffer (6) comprises an odd number memory (61) for storing an odd number of data among a plurality of queues (51) and an even number of a plurality of queues (51). An even memory (62) for storing eye data, and when data is stored in one memory, the data is read from the other memory. Extended storage control method.