JPH06244828A - Receiver, preset correction circuit and communication device to be used for same - Google Patents

Abstract

PURPOSE:To enable data to be read without error even if binarizing reference voltage fluctuates on the side of a receiver in a communication transmitting data of '0' and '1' by signal which changes gently in order to prevent the radiation of noise from a communication line. CONSTITUTION:The edge of binarized binary signal B is detected by a comparator 81 and a cyclic counter 83 is preset to the output signal Z0 or Z2 of a preset correction circuit 86 by this edge detection signal. The output signal Z0 or Z2 of the preset correction circuit 86 is set to '7' when the time till the cyclic counter 83 is preset is short and is set to '0' or '1' on the contrary. Therefore, even if the reference voltage E1 of the comparator 81 fluctuates, the preset value of the cyclic counter 83 is set so as to compensate this and reading error is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving device, a preset value correction circuit used in the receiving device, and a communication device using the receiving device.

[0002]

2. Description of the Related Art In recent years, due to the dramatic innovation and practical application of microprocessor technology, various systems have been proposed in which a plurality of microprocessors are mounted on various devices, such as vehicles, and each processor is connected by a communication line. There is.
It is used for the purpose of exchanging data to be shared by the processors with each other via a communication line and for notifying the diagnosis computer of the occurrence of an abnormality.
As such a system, various systems are known, such as an in-vehicle LAN in which on-vehicle control devices are connected to each other, various control devices in a factory, and a local area LAN to which machine tools are connected.

By the way, in the communication device used in the system in this way, the voltage of the communication line is set to a low voltage signal level or higher based on the data to be transmitted (usually a binary signal of "0" and "1"). Inverts rapidly to and from the signal level. Therefore, when the potential changes from 0 → 1, 1 → 0, a so-called step response occurs, and noise is generated by the high frequency component. Therefore, conventionally, in this type of receiving apparatus, in order to reduce noise emission, a device for avoiding a steep signal change has been made.

"1""1""0""1""1""0"
Taking the case of communicating data of "0" as an example, in response to a change of "0" or "1" in the data, the transmitting side gently changes the voltage of the communication line as shown in FIG. . On the other hand, the receiving side compares this voltage with the comparison voltage TH1.
It is converted into a signal of “0” and “1” by comparing with
The transmitted data is recreated by sampling in bit lengths.

[0005]

However, in this method, the length of "0" and "1" of the received signal changes greatly even if the comparison voltage slightly changes, and a reception error occurs due to sampling. There was a problem that there is. In the example of FIG. 6, the length of the signal differs by several tens of percent depending on “1” when the comparison voltage is TH1 and when the comparison voltage is TH2. The reason why the comparison voltage, which should originally be the reference, changes is mainly due to the fluctuation of the ground potential between the electronic control devices in which the respective microprocessors are mounted. In vehicles, the ground potential is the body, but in vehicles, cell motors and lights require a few amperes of current, so the current flowing through the body as ground is large and it is difficult to reduce local fluctuations in ground potential. is there.

When the comparison voltage changes and the length of "0" and "1" of the signal changes in this way, T from the edge.
/ 2, T + T / 2, 2T + T / 2, ..., M ・ T +
When sampling was performed at the time of T / 2 (M is an integer of 0 or more), "0" and "1" may be misread as shown in the bottom column of FIG.

The receiving apparatus of the present invention solves such a problem, accurately reads a transmitted signal in place of a gentle signal change, and further provides a preset value correction circuit and a communication apparatus suitable for this. For the purpose of
The following composition was adopted.

[0008]

A first receiving device according to the present invention receives a signal obtained by converting information constituted by a combination of two or more levels into a signal which gradually decreases or increases between the levels. A receiver for recovering the information from the signal, the converter receiving the signal, comparing it with a predetermined reference value, and converting the data into at least binary data, and the data converted by the converter. And a bit width measuring means for measuring the bit width of the bit width, the bit width measuring means compares the bit width measured by the bit width measuring means with a reference bit width, and based on the difference between the bit widths. And a measurement correction means for correcting the measurement of the bit width of the signal input after that.

A second receiving device according to the present invention receives a signal obtained by converting information constituted by a combination of two or more levels into a signal which gradually decreases / increases between the levels, and from the signal, the information A clock circuit for outputting a clock signal capable of dividing the width of the minimum bit forming the information into N (N is an integer of 2 or more),
A comparator which inputs the signal and compares it with a predetermined reference value, an edge output circuit which detects an edge of the output signal of the comparator and outputs an edge signal, and when the edge signal is received, it is given from the outside A counter that is set to a preset value and that cyclically counts up or down the clock signal from the preset value, and the number of clocks output during the bit width when a start bit with a fixed bit width is received. A preset value correction circuit that determines the magnitude of N and corrects the preset value to the side of advancing or returning the count according to the magnitude, and the counter is approximately N · (M + 1
/ 2) The output of the comparator when the number of clock signals (M is an integer of 0 or more) is counted is stored as the data, and when a predetermined number of data is stored in the register, the stored The gist of the present invention is to have a register for outputting data as the information.

According to the invention of the preset value correction circuit used in such a receiving apparatus, when the input value to this circuit is within the range of the initial value ± allowable value of the counter preset value, the initial value is input. When the value is larger than the initial value + allowable value, the value on the countdown side from the initial value is set, and when the input value is smaller than the initial value−the allowable value, the value on the countup side than the initial value is set. The gist is that it is an output circuit.

A communication device according to the present invention includes: a transmission device for converting information constituted by a combination of two or more levels into a signal for gradually decreasing / increasing between the levels and outputting the signal; The gist of the present invention is that it comprises the receiving device described in 2.

[0012]

According to the invention of the receiving device described in claim 1, the signal which is obtained by converting the information constituted by the combination of two or more levels into the signal gradually decreasing / increasing between the levels, The conversion means compares this with a predetermined reference value and converts it into at least binary data. The bit width of the converted data is measured by the bit width measuring means, and when the signal of the predetermined bit width is received, the bit width measured by the bit width measuring means is compared with the reference bit width, and this bit width is measured. On the basis of the difference of (1), the measurement correction means corrects the measurement of the bit width of the signal input thereafter. As a result, when the reference value in the converting means changes relatively, the receiving device of the present invention corrects the change and receives the information.

According to the invention of the second receiving device described in claim 2, the clock circuit sets the minimum bit width of information constituted by a combination of two or more levels to N (N is 2).
A clock signal which can be divided into the above integers is output and used for counting by a counter described later. The comparator is
A signal converted into a signal that gradually decreases / increases between two or more levels is input and compared with a predetermined reference value. Furthermore,
The edge output circuit detects an edge of the output signal of the comparator and outputs an edge signal. When this edge signal is received, the counter is set to a preset value given from the outside, and the above-mentioned clock signal is cyclically counted up or down from this preset value.

When the signal of the minimum bit width is received, the preset value correction circuit determines the number of clocks output during this bit width and the magnitude of N, and the preset value is determined according to this magnitude. Correct the count forward or backward. In the register, this counter is approximately ・ N (M +
The output of the comparator when counting 1/2 clock signals is stored as data, and when a predetermined number of data is stored in this register, the stored data is output as received information. Therefore, in this receiving device, when the reference value compared by the comparator changes relatively, the effect of the change is corrected by the preset value correction circuit, and the information is received without error.

The preset value correction circuit used for such a receiving device, when the input value to the circuit is within the range of the initial value ± allowable value of the counter preset value, the input value is changed to the initial value. When it is larger than the initial value + allowable value, the value on the countdown side from the initial value is output, and when the input value is smaller than the initial value-allowable value, the value on the countup side from the initial value is output. .

According to the invention of the communication device described in claim 2, the transmitting device converts the information constituted by a combination of two or more levels into a signal which gradually decreases / increases between the levels and outputs the signal. Then, information is transmitted / received by receiving this by the receiving device according to claim 1 or 2.

[0017]

Preferred embodiments of the present invention will be described below in order to further clarify the structure and operation of the present invention described above. FIG. 1 is a block diagram showing a schematic configuration of a receiving device as an embodiment, and FIG. 2 is an explanatory diagram showing a state in which various electronic control devices incorporating this receiving device constitute a LAN.

First, various electronic control units in the vehicle are
How the AN is configured will be described. As shown in FIG. 2, in this vehicle, a fuel injection control electronic control unit (hereinafter referred to as EFIECU) that controls the valve opening time of the fuel injection valve to perform appropriate fuel injection according to the operating state of the internal combustion engine. Two
0, a transmission control ECU 30 that controls up-shifting / down-shifting of a vehicle-mounted transmission, a suspension control ECU 40 that controls damping characteristics of a vehicle-mounted suspension, an anti-skid control ECU 50 that controls brake hydraulic pressure to prevent wheel slip during braking, internal combustion The sub-throttle control ECU 60 provided in the intake air system of the engine for changing the control characteristic of the intake air amount by the main throttle valve, judges whether the operation of each of these ECUs is normal when the power is turned on, and stores the state when an abnormality occurs The diagnosis ECU 70 is provided.

Each of the ECUs 20 to 70 has its E
Sensor groups 22, 3 for detecting information necessary for controlling the CU
2, 42, 52, 62, 72, and actuator groups 24, 34, 44, 54, 64 driven by the respective ECUs.
74 are connected. Each sensor group and each actuator group are ordinary ones used for publicly known control of each ECU, and the description thereof will be omitted. Each ECU above
20 to 70 are communicably connected to each other through a communication line TR. Each of the ECUs 20 to 70 is provided with a transmission circuit for transmitting data and a reception circuit for receiving the data via the communication line TR. When each ECU exchanges data via communication line TR, the transmitting ECU gives a specific code for identifying the ECU to be received at the beginning of the transmission data. Therefore, each ECU that constantly monitors the communication line TR
Can easily recognize whether or not the received data is addressed to itself.

Next, taking the EFIECU 20 as an example, the structure and function of a receiving circuit as a receiving device for reading data from the communication line TR will be described. As shown in FIG. 1, the EFIECU 20 includes an MPU 75 that controls the actuator group 24 based on the information received from the sensor group 22 and the data received via the communication line TR, and a receiving circuit that receives the data via the communication line TR. 80 and a transmission circuit 90 for outputting data via the communication line TR are provided.

The receiving circuit 80 includes a comparator 81 for comparing a signal from the communication line TR with a reference voltage E1, an edge detector 82 for detecting rising and falling edges of an output signal of the comparator 81, and an edge detector 8.
A cyclic counter 83 preset by an output signal of 2; an oscillator 85 that generates a clock signal CK counted by the cyclic counter 83; a preset correction circuit 86 that determines a preset value according to the output value of the cyclic counter 83; Cyclic counter 83
Of the comparator circuit 87 for detecting that the output of the comparator 8 has reached a preset value (value 4 in this embodiment), and the reception shift register 89 for fetching the output of the comparator 81 as data by using the coincidence detection signal of the comparator circuit 87 as the shift signal. ,, etc.

The receiving shift register 89 is a 10-bit shift register, which fetches the signal level of the data input terminal D in synchronization with the coincidence detection signal output from the comparison circuit 87, and starts the start bit 1, the data bit 8, and the stop bit. Data consisting of bit 1 is converted into parallel data.
The reception shift register 89 is connected to the address bus AB and the data bus DB of the MPU 75 and outputs an interrupt request signal IRQ to the MPU 75 when 10-bit data is prepared. MP receiving interrupt request signal IRQ
U75 outputs the address signal to which the shift register for reception 89 is allocated to the address bus AB, and among the 10-bit data accumulated in the shift register for reception 89, 8-bit data excluding the start bit and the stop bit. To read. The reception shift register 89 is reset by reading the data from the MPU 75.

Next, the preset correction circuit 86 will be described. As shown in FIG. 3, the preset correction circuit 86 outputs 3 bits to the 3-bit input signals A0 to A2.
It is a circuit that outputs bit output signals Z0 to Z2. FIG. 3 is an explanatory diagram showing the relationship between the input signal and the output signal of the preset correction circuit 86 in the form of a truth table. As shown in the figure, the preset correction circuit 86 is an octal display,
When the input signals A0 to A2 are "0", "3", "6" and "7", the output signals Z0 to Z2 are "0", and when the input signals A0 to A2 are "1" and "2", the output signal Z0 is
To Z2 become "1" and the input signals A0 to A2 are "5" and "6", the output signals Z0 to Z2 are "7".
Becomes

The relationship between these inputs and outputs is determined by the programmable array logic (PAL) according to the truth table.
It can be easily manufactured. Inside the PAL, an inverter INV group that generates an inverted signal of the input signal, an AND gate A that receives the input signal and its inverted signal as inputs.
It is composed of an ND group and an OR gate OR group that takes the logical sum of the outputs of the AND gate AND group, and a connection between the input signal and its inverted signal and the AND gate AND group, and a connection between the AND gate AND group and the OR gate OR group. By programming, the desired input / output relationship shown in the truth table can be realized. FIG. 4 is a circuit diagram showing the internal configuration of the preset correction circuit 86 realized by PAL using logic gates.

On the other hand, the transmission circuit 90, like the reception circuit 80, has an address bus AB and a data bus D of the MPU 75.
B is connected and is a circuit that sequentially converts data including start bits and stop bits written from the MPU 75 into serial signals and outputs the serial signals. Transmission circuit 90
As shown in FIG. 1, a transmission shift register 92 for converting parallel data written via the data bus DB into serial data, and an oscillator 94 for outputting a clock signal CLK for serial reading of the transmission shift register 92. An integrating circuit 96 for integrating the serial output signal of the transmission shift register 92 is provided.

Since the transmitting circuit 90 includes the integrating circuit 96 at the output stage to the communication line TR, the signal output from the EFIECU 20 to the communication line TR is gently switched between the signal levels "0" and "1". Signal. The same transmission circuit 90 is also installed in the other ECUs 30 to 70, and the communication through the communication line TR is performed by signals that change gradually. Therefore, the radiation of radio noise from the communication line TR is suppressed to an extremely small level.

Next, the operation of the receiving circuit 80 when receiving data via the communication line TR will be described. Figure 5
FIG. 6 is an explanatory diagram showing changes in signals and data in each unit of the receiving circuit 80. The code at the left end in the figure corresponds to the code given to the signal line in the receiving circuit 80 in FIG.

The transmission data is output to the communication line TR by the transmission circuit 90 provided in each of the ECUs 20 to 70 as a signal DX that gently changes between the "0" and "1" levels. The receiving circuit 80 inputs this signal, compares it with the reference voltage E1 by the comparator 81, and outputs "0".
The binary signal B of "1" is converted. The binary signal B is output to the edge detector 82 and the reception shift register 89. Of these, the edge detector 82 is
The rising and falling edges of the binary signal B are detected, and the edge detection signal C is output.

The edge detection signal C is input to the cyclic counter 83 and presets the cyclic counter 83. That is, the cyclic counter 83
The values of the output signals Z0 to Z2 of the preset correction circuit 86 at the time when the edge detection signal C is input are set. The output signals Z0 to Z2 of the preset correction circuit 86 have the values "0", "1", "7" as shown in FIG.
Of the cyclic counter 83
Will be set to one of these values.
The cyclic counter 83 immediately starts counting from this preset value and increments its output by one for each clock signal CK from the oscillator 85.

Output signals of the cyclic counter 83 (input signals of the preset correction circuit 86) A0 to A2
Is also input to the comparison circuit 87, and when the value becomes 4, the comparison circuit 87 outputs the coincidence detection signal F to the reception shift register 89. Therefore, the output level of the comparator 81 at this timing is stored as data in the reception shift register 89.
When 10-bit data including the start bit and the stop bit is accumulated in the reception shift register 89, the reception shift register 89 outputs the interrupt request signal IRQ to the MPU 75. In response to this, the MPU75
The data in the reception shift register 89 is read, and the data reception is completed.

The operation of the receiving circuit 80 when the reference voltage E1 in the comparator 81 changes will be described.
When the reference voltage E1 becomes high, the comparator 81
The period in which it is determined that the data transmitted via the communication line TR is at the high level (“1”) becomes short. Therefore, as shown in FIG. 5, the time from the detection of the rising edge of the binary signal B to the detection of the falling edge of the binary signal B is shortened, and the time when the edge detector 82 detects the rising edge of the binary signal B. The cyclic counter 83, which has been reset to the value "0" in step 1, receives the next preset signal before it is counted up to the value "7". At the time of receiving the next preset signal, the output signal Z0 of the preset correction circuit 86 determined by the states of the output signals A0 to A2 of the cyclic counter 83.
Through Z2 are not "0" but "7" and are preset in the cyclic counter 83.

As a result, the cyclic counter 83
The next count-up operation is started from the value "7", and the timing when the output thereof becomes the value "4", that is, the timing when the coincidence detection signal F of the comparison circuit 87 becomes the high level is higher than the clock in the normal case. It will be delayed by one signal CK. When the reference voltage E1 is deviated to the high side, the period in which the comparator 81 determines that the signal input from the communication line TR is the low level value 0 becomes long, and therefore the edge detection signal C becomes active next time. After a delay, the cyclic counter 83 counts up to the value "7", becomes the value "0" by the next clock signal CK, and in some cases, counts up to the value "1". In this case, the next edge detection signal C causes the cyclic counter 83 to be preset to the value “0” or the value “1” based on the output signal of the preset correction circuit 86, and the period until the coincidence detection signal F is output. Becomes shorter.

That is, in this embodiment, when the reference voltage E1 becomes high and the period during which the binary signal B is judged to be high level becomes short, the cyclic counter 83 is preset at the rising of the binary signal B. The value is a default value (0 in the embodiment) or a value larger than this,
The timing at which the output of the comparator 81 is taken in as data is advanced, while the value preset in the cyclic counter 83 at the fall of the binary signal B is the default value or a value on the near side with respect to counting up. , The timing of fetching the output of the comparator 81 as data is delayed. Note that when two or more bits of the same level continue, the edge detection signal C is not output. Therefore, the timing at which the second match detection signal F is output is the regular interval (cycle) from the output of the first match detection signal F. Click counter 83 has eight clock signals C
(A period for counting K). As a result, even if the reference voltage E1 fluctuates and becomes higher than the normal value, the preset value of the cyclic counter 83 is compensated accordingly, and the data can be read correctly.

When the reference voltage E1 becomes low and the period during which the binary signal B is judged to be at the high level becomes long, the cyclic counter 83 is provided to the cyclic counter 83 when the binary signal B rises, contrary to the operation described above. The preset value is a value closer to the count-up than the default value, and the preset value when the binary signal falls is larger than the default value. As a result, similarly to the case where the reference voltage E1 becomes high, the influence is compensated and the data is read correctly.

The operation in which the receiving circuit 80 correctly reads the data from the signal sent through the communication line TR with respect to the fluctuation of the reference voltage E1 has been described above. Whether data can be read normally also depends on the tolerance between the clock on the transmitting side and the clock on the receiving side in the case of asynchronous communication. In the case of asynchronous communication, it is usually impossible to completely match the clocks on the transmitting side and the receiving side. Therefore, the allowable error range becomes a problem when designing the system. The present invention can be regarded as expanding the range of the permissible error of the clock in the system designed on the assumption that the reference voltage E1 fluctuates to some extent. This point will be shown by calculation in accordance with the receiving circuit 80 of the embodiment.

It is assumed that the frequency of the clock signal of the transmission circuit is deviated by (1 + δ) times the specification value. When the transmission circuit transmits data in which all 8 bits have a value of 1 with this clock, the period TL during which the transmission signal is at the high level corresponding to this data is the time prepared for 1 bit as T. Then, TL = 8 · T / (1 + δ). On the other hand, in the receiving circuit 80, the reference voltage E1
Assuming that the period during which the binary signal B is at the high level is shortened by 0.3T as compared with the case of the normal reference voltage due to the fluctuation of, the period Tw on the receiving side is Tw = TL-0. It becomes 3 · T.

The frequency of the clock signal is (1+
The most erroneous reading error occurs in the δ) times transmission circuit when the frequency of the clock signal CK is combined with the reception circuit 80 having the specification value (1-δ). Data can be read from the beginning of the data at T
Since the first bit is read after / 2, and the reading is performed every cycle T thereafter, an error occurs when reading the last bit (8th bit).
Is T / (1−δ), the condition is Tw ≦ (8−1 / 2) · T / (1−δ). In other words, no reading error occurs in the range of δ that satisfies Tw> (8-1 / 2) · T / (1-δ) (1). Then, by solving this equation, δ <0.013 is obtained. This is the allowable error of the clock signal in the conventional transmitting / receiving circuit.

On the other hand, in this embodiment, since the period of the start bit is measured and the sampling timing is adjusted, in the above case, the period until the first sampling is the clock signal CK from the oscillator 85.
It is shortened by one. Since the clock signal CK corresponds to ⅛ of the reading cycle T, the above equation (1) becomes Tw> (8−1 / 2−1 / 8) · T / (1−δ), which is acceptable. The range of the error δ is δ <0.022.

That is, when the length of the binary signal B output from the comparator 81 varies by 0.3.T due to the variation of the reference voltage E1, 1.3% of the clock accuracy is required in the prior art. According to this embodiment, 2.2
Percentage will be acceptable.

The embodiment of the present invention has been described above.
The present invention is not limited to such an embodiment. For example, the cyclic counter 83 is not an octal counter but a hexadecimal or hexadecimal counter, and the preset correction circuit 86 is realized by the MPU 75. A configuration in which the preset correction circuit 86 is realized by a ROM,
The preset correction circuit 86 is realized by a rewritable RAM so that the preset value is learned to an appropriate value when a reading error occurs, or a communication device other than communication between ECUs mounted on a vehicle (for example, a LAN in a factory or the like). Needless to say, the present invention can be implemented in various modes without departing from the scope of the present invention, such as a configuration applied to a transceiver.

[0041]

As described above in detail with reference to the embodiments, the first receiving device of the present invention compares the bit width measured by receiving a signal having a predetermined bit width with the reference bit width. Then, based on the difference, the measurement of the bit width of the subsequently input signal is corrected. Therefore, even if a reference value for converting a signal that gradually decreases / increases and converts it into binary data or more fluctuates and the bit width fluctuates, the information can be restored without error. Produce an effect.

The second receiver of the present invention uses a counter that cyclically counts clock signals,
The counter has a configuration for reading the output of the comparator as data when counting approximately N · (M + ½) clock signals, and the clock signal output within the width of the start bit when the start bit is received. The preset value of the counter is corrected to the side for advancing or returning the count according to the magnitude relation between the number of N and N. Therefore, even when the reference value of the comparator that inputs a signal that gradually decreases / increases and converts this into binary or more data fluctuates and the bit width fluctuates, it is possible to restore information without error. Produce an effect.

Further, the preset value correction circuit used in the above-mentioned receiving device is initialized depending on whether the input value to this circuit is within the allowable range, larger than the allowable range, or smaller than the initial value of the preset value of the counter. Since the value itself, the value on the countdown side or the value on the countup side from the initial value is output, it is possible to easily set the preset value of the counter to the side where data reading error is unlikely to occur.

Further, the communication device which is a combination of the receiving device and the transmitting device exchanges information constituted by a combination of two or more levels by converting it into a signal which gradually decreases or increases between the levels. It is possible to reduce noise radiation from the communication line, and moreover, it is possible to prevent data reading errors.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a receiving apparatus as an embodiment.

FIG. 2 is an explanatory diagram showing a state in which various electronic control devices incorporating the receiving device constitute a LAN.

FIG. 3 is an explanatory diagram showing an input / output relationship of a preset correction circuit 86.

FIG. 4 is a circuit diagram showing an example in which a preset correction circuit 86 is realized by PAL.

FIG. 5 is an explanatory diagram showing changes in signals and data in each unit of the receiving circuit 80.

FIG. 6 is an explanatory diagram showing a mechanism of data read error in a conventional receiving device.

[Explanation of symbols]

20 ... EFIECU 22, 32, 42, 52, 62, 72 ... Sensor group 24, 34, 44, 54, 64, 74 ... Actuator group 30 ... Transmission control ECU 40 ... Suspension control ECU 50 ... Anti-skid control ECU 60 ... Sub throttle Control ECU 70 ... Diagnostic ECU 75 ... MPU 80 ... Reception circuit 81 ... Comparator 82 ... Edge detector 83 ... Cyclic counter 85 ... Oscillator 86 ... Preset correction circuit 87 ... Comparison circuit 89 ... Reception shift register 90 ... Transmission circuit 92 ... Transmission shift register 94 ... Oscillator 96 ... Integration circuit

Claims (4)

[Claims] 1. A receiving device, which receives a signal obtained by converting information constituted by a combination of two or more levels into a signal that gradually decreases / increases between the levels, and restores the information from the signal, Conversion means for inputting the signal, comparing it with a predetermined reference value, and converting it into at least binary data, and bit width measuring means for measuring the bit width of the data converted by the conversion means, When a signal having a different bit width is received, the bit width measuring means compares the bit width measured with a reference bit width, and based on the difference in the bit width, corrects the measurement of the bit width of the signal inputted thereafter. And a receiving device that includes a measurement correction unit that 2. A receiving device, which receives a signal obtained by converting information constituted by a combination of two or more levels into a signal that gradually decreases / increases between the levels, and restores the information from the signal, A clock circuit that outputs a clock signal that can divide the width of the minimum bit that constitutes the information into N (N is an integer of 2 or more); a comparator that inputs the signal and compares it with a predetermined reference value; An edge output circuit that detects the edge of the output signal of the comparator and outputs the edge signal, and when the edge signal is received, it is set to a preset value given from the outside, and the clock signal is cyclically set from the preset value. When receiving a counter that counts up or down and a start bit with a fixed bit width,
A preset value correction circuit that determines the magnitude of the number of clocks output during the bit width and the N, and corrects the preset value to the side of advancing or returning the count according to the magnitude; Stores approximately N · (M + ½) (M is an integer of 0 or more) the clock signals, and stores the output of the comparator as the data, and a predetermined number of data is stored in the register. At this time, a receiving device comprising a register for outputting the accumulated data as the information. 3. A preset value correction circuit used in the receiving device according to claim 2, wherein the input value to the circuit is within a range of an initial value ± allowable value of a preset value of the counter. , The initial value, if the input value is larger than the initial value + allowable value, the value on the countdown side of the initial value, if the input value is smaller than the initial value-allowable value, the initial value A preset value correction circuit that is a circuit that outputs the value on the count-up side from the value. 4. A transmitting device for converting information, which is composed of a combination of two or more levels, into a signal which gradually decreases / increases between the levels and outputs the signal, and the receiving device according to claim 1 or 2. Communication device.