JPH06244725A - Codec - Google Patents

Abstract

PURPOSE:To obtain a CODEC whose S/N is satisfactory in which a master clock signal is not necessary, and the frequency of a bit clock signal is not restricted. CONSTITUTION:When a synchronizing signal SB and a bit clock signal BC are supplied from an outside, a PLL circuit 120 is operated by using the signal SB as a reference signal, and the output signal is transmitted to a selecting circuit 140. Then, a frequency-division rate is set at a frequency dividing circuit 133 according to the output frequency of the signal BC, the signal BC is frequency-divided by the frequency-division rate, and transmitted to the selecting circuit 140. The selecting circuit 140 selects one of the output of the PLL circuit 120 and the output of the selecting circuit 140 according to the frequency of the signal BC, and outputs an inside clock signal $. Then, a clock signal or a control signal or the like to be used by SCF 101 and 201, A/D converter 102, and D/A converter 202 or the like are generated by control circuits 103 and 203 by the signal phi.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a switched capacitor filter (hereinafter referred to as SCF), an analog / digital converter (hereinafter referred to as A / D converter), a digital / analog converter (hereinafter referred to as D / D). A converter) and a clock generation means, etc., and is integrated in a codec for converting an analog signal into a digital signal and converting the processed digital signal into an analog signal again, particularly in one chip or the like. SC in the codec
The present invention relates to an F, A / D converter, and a clock generation means for creating and supplying a high-speed clock signal necessary for the D / A converter.

[0002]

2. Description of the Related Art Conventionally, a signal externally supplied as an input clock signal to a codec of this kind inputs and outputs a synchronizing signal for determining a sampling frequency for A / D conversion and D / A conversion, and a digital signal. For the bit clock signal only. Therefore, S used inside the codec
The clock signal for CF, the clock signal for A / D and D / A conversion, and the like are generated by a clock generation means provided inside the codec using a synchronization signal and a bit clock signal given from the outside. As the clock generation method, the following three methods are generally used. (1) Method using master clock (2) Phase-locked loop (hereinafter referred to as PLL)
(3) Method using data input / output clock (bit clock) FIG. 2 is a functional block diagram showing a conventional master clock codec in (1). This codec has, on the A / D conversion side, an SCF1 for removing high frequency components and the like of an analog signal AS input from the outside,
An A / D converter 2 for converting the output of the SCF 1 into a digital signal, and a clock generating means for inputting / outputting a signal and generating a plurality of clock signals for operating an internal circuit,
I have it. The clock generating means is composed of the control circuit 3 and the fixed frequency divider 4. The fixed frequency divider 4 is a circuit that divides the master clock signal MC given from the outside with a division ratio of 1 / K and gives the divided signal to the control circuit 3.
The control circuit 3 inputs a synchronizing signal SB and a bit clock signal BC given from the outside, outputs a digital signal DS based on the bit clock signal BC, and
It is a circuit that generates a clock signal used for the SCF 1 and a control signal used for the A / D converter 2 based on the frequency-divided signal of the fixed frequency divider 4.

In this A / D conversion side circuit, when an analog signal AS is input to the SCF1 from the outside, the SCF1
Then, the high frequency component of the input analog signal AS is removed based on the clock signal from the control circuit 3 and the A / D converter 2
Send to. The A / D converter 2 converts the analog output of the SCF 1 into a digital signal based on the control signal from the control circuit 3 and sends it to the control circuit 3. The control circuit 3 outputs the digital signal DS converted by the A / D converter 2 to the outside based on the bit clock signal BC. In such a master clock system, since the frequency division ratio 1 / K of the fixed frequency divider 4 is fixed, the master clock signal MC is also limited.
It should be noted that FIG. 2 shows a circuit only on the A / D conversion side.
The circuit on the A conversion side is omitted. The circuit on the D / A conversion side is composed of an SCF, a D / A converter, a control circuit, and a fixed frequency divider, similar to the A / D conversion side. Then, the digital signal is input to the control circuit by the bit clock signal, and the input digital signal is D
After being converted into an analog signal by the / A converter, high frequency components and the like are removed by the SCF and output to the outside.

FIG. 3 shows the conventional PLL in (2) above.
It is a functional block diagram which shows the codec of a system. In addition,
Similar to FIG. 2, only the A / D conversion side is shown. On the A / D conversion side of this codec, a PLL circuit 5 is provided instead of the fixed frequency divider 4 of FIG. Then, the synchronization signal SB given from the outside is input to the PLL circuit 5 as a trigger signal (reference signal) of the PLL circuit 5. Then, the PLL circuit 5 generates a signal having a frequency of several tens of times the frequency of the synchronizing signal SB based on the inputted synchronizing signal SB,
It is given to the control circuit 3. The control circuit 3 generates a clock signal used for the SCF 1 and a control signal used for the A / D converter 2 based on the signal from the PLL circuit 5. Based on this clock signal and control signal, as in FIG. 2, the input analog signal AS has high-frequency components removed by the SCF 1,
After being converted into a digital signal by the A / D converter 2, it is output from the control circuit 3 to the outside.

FIG. 4 is a functional block diagram showing a conventional bit clock type codec in (3). As in FIG. 2, only the A / D conversion side is shown. On the A / D conversion side of this codec, a variable frequency divider 6 is provided instead of the fixed frequency divider 4 of FIG. Then, the bit clock signal BC given from the outside is divided by the variable frequency divider 6 to a division ratio of 1 / L, and the divided signal is given to the control circuit 3. In the control circuit 3, the clock signal used for the SCF 1 and the A /
A control signal or the like used for the D converter 2 is generated. Based on the clock signal and the control signal, as in FIG. 2, the input analog signal AS is SCF1 where high frequency components are removed, and A / A
After being converted into a digital signal by the D converter 2, it is output to the outside through the control circuit 3. In this bit clock method, the frequency of the bit clock signal BC input from the outside is a signal that also determines the input / output speed of the digital signal DS, and changes depending on the use of the codec, so the frequency division ratio is 1 / L. Variable divider 6 so that the
Is used.

[0006]

However, when a plurality of clock signals for internal circuit operation are generated by the conventional master clock system (1), PLL system (2), and bit clock system (3), the following occurs. There was a problem. (A) The conventional master clock system (1) requires the master clock signal MC which is not necessary for the operation of the codec. Moreover, since the frequency of the master clock signal MC is limited, if the device using the codec does not have a signal corresponding to the master clock frequency, a new oscillator must be provided. (B) In the conventional PLL system (2), the phase / frequency difference between the signal generated in the PLL circuit 5 and the reference signal (synchronous signal) is detected, and the oscillator in the PLL circuit 5 is fed back. The signal output from the PLL circuit 5 has jitter (phase temporal fluctuation). When this is used as the clock signal of the SCF1 using the switched capacitor technology, the signal input from the outside, especially the high-frequency bit clock signal BC becomes noise, and aliasing noise is generated in the SCF1 to cause the codec as a codec. The signal-to-noise ratio (S / N ratio) deteriorates. (C) In the conventional bit clock method (3), the frequency of the bit clock signal BC is SCF1 of the codec,
The condition is that the signal frequency is higher than that required for the A / D converter 2 and the D / A converter on the D / A conversion side. Therefore, the frequency of the bit clock signal BC is SCF1, A
There is a problem that it cannot be used for applications lower than the frequency of the signal required for the / D converter 2 and the D / A converter on the D / A conversion side. The present invention has a problem that the clock generation method using the master clock requires the master clock signal MC and, in some cases, an oscillator, and the clock generation method using the PLL uses S as a codec. The clock generation method using the bit clock, which deteriorates the / N ratio, solves the problem that the application of the codec is limited, does not require the master clock signal MC, and does not have the restriction of the bit clock frequency, and the S / N ratio is reduced. It provides a good codec.

[0007]

According to a first aspect of the present invention, in order to solve the above problems, a synchronizing signal for determining a sampling frequency and a bit clock signal for inputting / outputting a digital signal are supplied from the outside. A clock generating means for generating an internal clock signal based on those signals and generating a plurality of internal circuit operating signals from the internal clock signal is provided, and an analog signal passing through the SCF is In a codec in which a digital signal is converted into a digital signal by a D / D converter and output, and a digital signal input from the outside is converted into an analog signal by a D / A converter, the clock generating means is configured as follows. There is. That is, in the clock generating means of the present invention, a frequency divider circuit for frequency-dividing the bit clock signal, a PLL circuit that operates using the synchronizing signal as a reference signal, and the frequency divider circuit output according to the frequency of the bit clock signal. And a selection circuit that selects one of the outputs of the PLL circuit and outputs it as the internal clock signal.

According to a second aspect of the invention, there is provided a variable frequency divider for dividing the bit clock signal at a frequency division ratio determined by the frequency division ratio setting data, and the variable frequency divider of the first frequency divider circuit. A fixed frequency divider that divides the output at a constant frequency division ratio, and a frequency coincidence signal / frequency inconsistency signal that detects the coincidence / disagreement between the frequency of the synchronization signal and the output frequency of the fixed divider. And a frequency-matching detector that outputs the frequency-matching signal, and a frequency-dividing-ratio setting data selector that outputs the frequency-dividing-ratio setting data to the variable frequency divider based on the frequency mismatch signal. Furthermore, the selection circuit of the first invention outputs the first selection signal when the frequency mismatch signal is counted and the signal is generated more than a specified value, and the frequency match signal is counted and the signal is specified value. A counter that outputs a second selection signal when the above occurs, and a selector that selects the output of the PLL circuit based on the first selection signal and selects the output of the frequency divider circuit based on the second selection signal. And with
I am configuring. In a third invention, in the codec of the second invention, power is supplied to the PLL circuit based on the first selection signal, and power supply to the PLL circuit is cut off based on the second selection signal. It is configured.

[0009]

According to the first aspect of the invention, since the clock generating means of the codec is configured as described above, the frequency dividing circuit divides the frequency of the bit clock signal supplied from the outside and sends it to the selecting circuit. The PLL circuit operates using a synchronization signal supplied from the outside as a reference signal and sends its output signal to the selection circuit. The selection circuit selects either the frequency divider circuit output or the PLL circuit output according to the frequency of the bit clock signal, and outputs it as an internal clock signal. Based on this internal clock signal, the SCF, A / D converter, and D
A plurality of internal circuit operation signals used in the / A converter and the like are generated. According to the second invention, when the frequency coincidence detector outputs the frequency coincidence signal or the frequency discordance signal, the division ratio setting data selector outputs the division ratio setting data based on the frequency discord signal. The division ratio of the variable frequency divider is set. With the variable frequency divider, at the set division ratio,
The bit clock signal supplied from the outside is divided and the divided output signal is sent to the fixed divider and the selector. on the other hand,
The PLL circuit operates with the synchronizing signal supplied from the outside as a reference signal, and the output signal is sent to the selector. The selector selects either the frequency divider circuit output or the PLL circuit output according to the first or second selection signal from the counter, and outputs the internal clock signal. Here, the frequency dividing circuit operates as a variable frequency dividing circuit capable of changing the frequency dividing ratio of the bit clock signal supplied from the outside according to its frequency. Therefore, either the frequency divider circuit output or the PLL circuit output is selected by the selector according to the frequency of the bit clock signal, and is output as the internal clock signal. According to the third invention, the PLL circuit operates based on the first selection signal output from the counter, and stops the operation based on the second selection signal output from the counter. Therefore, the above problem can be solved.

[0010]

1 is a functional block diagram of a codec showing an embodiment of the present invention. On the A / D conversion side of this codec, S for removing high frequency components etc. of the analog signal AS1
A CF 101 and an A / D converter 102 that converts the output of the SCF 101 into a digital signal are provided. Further, on the D / A conversion side, an SCF 201 that removes high frequency components and outputs an analog signal AS2, and the SCF 201
D / A converter 202 for giving an analog signal to 01
And are provided. A / D converter 10 on the A / D conversion side
2 and the D / A converter 202 on the D / A conversion side are connected to a clock generation means. The clock generation means is A /
An internal clock generation circuit 11 that generates an internal clock signal φ based on a control circuit 103 on the D conversion side and a bit clock signal BC for inputting and outputting a synchronizing signal SB that determines a sampling frequency and digital signals DS1 and DS2.
0, and a control circuit 203 on the D / A conversion side.

The control circuit 103 on the A / D conversion side inputs the bit clock signal BC, the synchronization signal SB, and the internal clock signal φ, and A / D based on the bit clock signal BC.
The digital signal DS1 from the D converter 102 is output to the outside, and SCF1 is output based on the internal clock signal φ.
A circuit for generating a clock signal used for 01, a control signal used for the A / D converter 102, and the like. The control circuit 203 on the D / A conversion side controls the bit clock signal BC and the synchronization signal S.
B and an internal clock signal φ are input, a digital signal DS2 is input from the outside based on the bit clock signal BC and is given to the D / A converter 202, and a clock signal used in the SCF 201 based on the internal clock signal φ,
And a circuit for generating control signals and the like used in the D / A converter 202. The internal clock generation circuit 110 uses the synchronization signal S
A PLL circuit 120 that operates with B as a reference signal, a frequency divider circuit 130 that inputs the synchronization signal SB and the bit clock signal BC and divides the bit clock signal BC, and a frequency divider circuit 130 that operates according to the frequency of the bit clock signal BC. PLL circuit 1
A selection circuit 140 that selects either the output of 20 or the output of the frequency dividing circuit 130 and outputs the internal clock signal φ.
It consists of and.

The PLL circuit 120 has a phase comparator 121 which inputs the synchronizing signal SB from a reference signal input terminal 121a. The phase comparator 121 has a reference signal input terminal 1
21a is a circuit for comparing the phase of the signal of the feedback signal input terminal 121b and outputting a voltage according to the phase difference. A voltage controlled oscillator is provided at its output terminal via a filter 122 for removing high frequency components. (Hereafter, VCO
123) is connected. The VCO 123 is a circuit that outputs an output signal having a frequency corresponding to the output voltage of the filter 122 from the output terminal 123a. Output terminal 12
3a is connected to the phase comparator 12 via the 1 / N frequency divider 124.
One feedback signal input terminal 121b is connected. The frequency dividing circuit 130 has a frequency coincidence detector 131 that inputs the synchronization signal SB from the first input terminal 131a. The frequency coincidence detector 131 has a first input terminal 1
A frequency match / mismatch between the signal of 31a and the signal of the second input terminal 131b is detected, and when they do not match, a frequency mismatch signal (for example, NG pulse) S131a is output from the first output terminal 131c. The frequency matching signal (eg, OK pulse) S131b is output to the second output terminal 1
It is a circuit which outputs from 31d. First output terminal 131
In c, the input terminal 13 of the frequency division ratio setting data selector 132
2a is connected. Frequency division ratio setting data selector 132
Is the NG pulse S13 input from the input terminal 132a.
1a to output the division ratio setting data S132 to the output terminal 1
A circuit for outputting from 32b, and its output terminal 132b
A frequency division ratio setting input terminal 133b of a variable frequency divider 133 having a frequency division ratio of 1 / M is connected to.

The frequency divider 133 has a frequency division ratio setting input terminal 13
It is a circuit that divides the bit clock signal BC input from the clock input terminal 133a by 1 / M based on the division ratio setting data S132 input from 3b and outputs the result from the output terminal 133c. The output terminal 133c has a division ratio of 1 /
The clock input terminal 134a of the N fixed frequency divider 134 is connected. The frequency divider 134 is a circuit that divides the output of the frequency divider 133 by 1 / N and outputs the result from the output terminal 134b. The output terminal 134b has a frequency coincidence detector 131.
Of the second input terminal 131b. The selection circuit 140 is a counter (for example, an up / down counter).
141 and a selector 142, the first input terminal 141a of the up / down counter 141 is connected to the first output terminal 131c of the frequency coincidence detector 131, and the second input terminal 141b of the up / down counter 141 is It is connected to the second output terminal 131d of the frequency coincidence detector 131. The up / down counter 141 has an NG pulse S131a input from the first input terminal 141a or an OK pulse S input from the second input terminal 141b.
131b are counted, and the first or second selection signal S141 is output to the output terminal 1 when these signals are generated more than a specified value.
It is a circuit which outputs from 41c. The output terminal 141c is
Connected to the third input terminal 142c of the selector 142,
If the first input terminal 142a of the selector 142 is VC
The second input terminal 142 is connected to the output terminal 123a of the O123.
b is connected to the output terminal 133c of the frequency divider 133, respectively. The selector 142 uses the third input terminal 14
2c is a circuit that connects either one of the first and second input terminals 142a and 142b to the output terminal 142d based on the selection signal S141 input to the output terminal 1c.
42d is connected to the control circuits 103 and 203, respectively.

Next, the operation will be described. When the bit clock signal BC and the synchronization signal SB are supplied to the control circuits 103 and 203 and the internal clock generation circuit 110, the internal clock generation circuit 110 generates an internal clock signal φ and supplies it to the control circuits 103 and 203. In the control circuit 103 on the A / D conversion side, based on the internal clock signal φ,
It outputs a clock signal given to the SCF 101, a control signal given to the A / D converter 102, and the like. Then, the input analog signal AS1 has high-frequency components removed by the SCF 101, is converted into a digital signal by the A / D converter 102, and is sent to the control circuit 103. Control circuit 103
Then, the digital signal from the A / D converter 102 is output to the outside in the form of DS1 based on the bit clock signal BC. Further, in the control circuit 203 on the D / A conversion side, when the internal clock signal φ is given from the internal clock generation circuit 110, the SCF 20 is generated based on the internal clock signal φ.
1 outputs a clock signal for operating 1 and a control signal for operating the D / A converter 202. When the digital signal DS2 is given from the outside, the control circuit 2
In 03, the digital signal DS2 is input based on the bit clock signal BC and sent to the D / A converter 202. D
The / A converter 202 converts the digital signal from the control circuit 203 into an analog signal. The analog signal AS2 of this analog signal is output to the outside after the high-frequency component and the like are removed by the SCF 201.

Next, the operation of the internal clock generating circuit 110 will be described. Sync signal SB and bit clock signal BC
Is given, the synchronizing signal SB is input to the reference signal input terminal 121a of the phase comparator 121 in the PLL circuit 120, and the frequency coincidence detector 1 in the frequency dividing circuit 130 is supplied.
31 is input to the first input terminal 131a of 31 and the bit clock signal BC is further input to the frequency divider 13 in the frequency divider circuit 130.
3 is input to the clock input terminal 133a. In the PLL circuit 120, the phase comparator 121 compares the phase of the synchronization signal SB input from the reference signal input terminal 121a with the output signal of the 1 / N frequency divider 124 input from the feedback signal input terminal 121b. , And outputs a voltage according to the phase difference. This voltage is sent to the VCO 123 after the high frequency component is removed by the filter 122. V
The CO 123 oscillates at a frequency according to the output voltage of the filter 122, outputs the output signal from the output terminal 123a and feeds it back to the 1 / N frequency divider 124, and at the same time, outputs the first signal from the selector 142 in the selection circuit 140. To the input terminal 142a.

On the other hand, in the frequency divider circuit 130, the bit clock signal BC is applied to the clock input terminal 13 of the frequency divider 133.
3a, the frequency divider 133 outputs the frequency division ratio setting data S input from the frequency division ratio setting data selector 132.
The bit clock signal BC is frequency-divided at a frequency division ratio 1 / M determined by 132, and is output from the output terminal 133c. This frequency-divided output is 1 / N-divided by the 1 / N frequency divider 134, output from the output terminal 134b, and sent to the second input terminal 131b of the frequency coincidence detector 131. The frequency coincidence detector 131 compares the frequency of the synchronization signal SB input to the first input terminal 131a with the output frequency of the 1 / N frequency divider 134 input to the second input terminal 131b, When the frequency of the synchronization signal SB and the output frequency of the 1 / N frequency divider 134 are different, an NG pulse S131a is output from the first output terminal 131c every time the synchronization signal SB is input,
When the frequency of the synchronizing signal SB matches the output frequency of the 1 / N frequency divider 134, an OK pulse S131b is output from the second output terminal 131d every time the synchronizing signal SB is input. For example, when the frequency coincidence detector 131 outputs the NG pulse S131a, the frequency division ratio setting data selector 132, which receives the NG pulse S131a, outputs the frequency division ratio 1 of the frequency divider 133.
The frequency division ratio setting data S132 so that the value of / M becomes a value of 1 / Ma which is different from the value of the frequency division ratio 1 / M.
Input to the frequency division ratio setting input terminal 133b. This frequency division ratio setting data S132 is updated by the frequency coincidence detector 131.
This is repeated until the NG pulse S131a disappears. Here, when the frequency of the bit clock signal BC input to the frequency divider 133 is f _BC and the frequency of the synchronization signal SB is f _SB , the following equation (1) is established.

[0017]

[Equation 1] When the value of M that satisfies the equation (1) is selected by the frequency division ratio setting data selector 132, the frequency coincidence detector 131
An OK pulse S131b is output from the second output terminal 131d. On the other hand, when the value of M satisfying the equation (1) is not included in the frequency division ratio setting data S132, the frequency coincidence detector 131 outputs the NG pulse S from the first output terminal 131c.
131a is continuously output. NG pulse S131a and OK pulse S13 output from the frequency coincidence detector 131
The up / down counter 141 that receives 1b is NG
Count up with pulse S131a, OK pulse S1
Countdown at 31b. The up / down counter 141 may be configured to count down with the NG pulse S131a and count up with the OK pulse S131b. The set value of the count number of the up / down counter 141 is determined by minimizing the value obtained by adding +1 to the frequency division ratio setting data S132 prepared in the frequency division ratio setting data selector 132. This up / down counter 141
The selection signal S141 output from the counter changes from "0" to "1" when the count-up input number exceeds the count number setting value, and continues to be "1" until the next countdown input number exceeds the count number setting value. When the countdown input number exceeds the set value of the count number, the state is maintained and the count is changed from "1" to "0". Up-down counter 141
When the selection signal S141 output from the selector 142 is input to the third input terminal 142c of the selector 142,
2 selects either the output of the PLL circuit 120 input to the first input terminal 142a or the output of the frequency divider 133 input to the second input terminal 142b,
The internal clock signal φ is output from the output terminal 142d and sent to the control circuits 103 and 203.

Next, the counting operation of the up / down counter 141 will be described with reference to FIG. FIG. 5 shows FIG.
It is a time chart which shows the count operation of the inside up-down counter 141. In FIG. 5, among the waveforms representing the count state of the up / down counter 141, the chain line Ca is the “0” count state, and the broken line Cb is the counter set value. In FIG. 5, since the frequency of the synchronization signal SB and the output frequency of the 1 / N frequency divider 134 do not match from time t1 to t5, the frequency match detector 131
As a result, the NG pulse S131a is output, and the up / down counter 141 counts up. This time t1 to t
During the period of 5, the frequency division ratio setting data selector 132 outputs the frequency division ratio setting data S13 every time the NG pulse S131a is input.
Update 2.

In the period from time t6 to time t16, time t
As a result of the frequency division of the frequency divider 133 by the frequency division ratio setting data S132 set by the NG pulse S131a of No. 5, the frequency of the synchronization signal SB and the output frequency of the 1 / N frequency divider 134 match. OK pulse S from the detector 131
131b is output and the up / down counter 141 counts down. Here, at time t10, the up / down counter 141 counts down to the “0” state and holds that state thereafter. After time t16, the frequency of the bit clock signal BC input to the clock input terminal 133a of the frequency divider 133 changes, the frequency match detector 131 outputs an NG pulse S131a, and the up / down counter 141 starts counting up. After the time t17, the frequency division ratio setting data selector 132 receives the frequency division ratio setting data S132 for each input of the synchronization signal SB.
Update. However, since there is no frequency division ratio setting data in which the frequency of the synchronization signal SB and the output frequency of the 1 / N frequency divider 134 match in the frequency division ratio setting data S132 prepared, the frequency coincidence detector 131 outputs NG. Pulse S131
Continue to issue a. The up / down counter 141 is NG
The pulse S131a is counted up, and the NG pulse S
When the number of 131a reaches the counter setting value Cb, "1"
Output the selection signal S141. This selection signal S141
As a result, the selector 142 outputs the internal clock signal φ output to the output terminal 142d from the output signal of the frequency divider 133.
Switching to the output signal of the PLL circuit 120. Also, the frequency divider 1
The frequency of the bit clock signal BC input to the clock input terminal 133a of 33 changes, and the frequency division ratio setting data S
When the frequency of the synchronization signal SB and the output frequency of the 1 / N frequency divider 134 match due to the update of 132, the frequency match detector 131 outputs an OK pulse S131b. Then, the counter setting value C of the up / down counter 141
When OK pulses S131b whose number is equal to or greater than b are output, the count state of the up / down counter 141 is inverted. Then, the selector 142, which receives the selection signal S141 output from the up / down counter 141, has the output terminal 14
The internal clock signal φ output to 2d is supplied to the PLL circuit 12
The output signal of 0 is switched to the output signal of the frequency divider 133.

The above-mentioned counting operation will be described below with specific numerical values. For example, the frequency of the synchronization signal SB is 8 KHz, and the frequency of the necessary internal clock signal φ is 2
If the frequency is 56 KHz, the frequency division number N of the frequency dividers 124 and 134 is N.
Is 32. Under this condition, if the frequency of the bit clock signal BC is 2048 KHz, and if the frequency division number M of the frequency divider 133 is 8, the frequency of the synchronization signal SB and the output frequency of the 1 / N frequency divider 134 are equal. Frequency matching detector 1
31 continuously outputs the OK pulse S131b. As a result, the signal obtained by dividing the bit clock signal BC by the frequency divider 133 is output to the output terminal 142d of the selector 142 through the selector 142 as the internal clock signal φ and supplied to the control circuits 103 and 203. If the frequency of the bit clock signal BC is 64 KHz, which is lower than the required frequency of 256 KHz of the internal clock signal φ, the frequency divider 133 cannot perform frequency division. for that reason,
Successive NG pulses S13 from the frequency coincidence detector 131
1a is output, and the selector 142 outputs PL by the selection signal S141 output from the up / down counter 141.
The output signal of the L circuit 120 is selected, and the internal clock signal φ
Output as.

As described above, this embodiment has the following advantages. A frequency divider circuit 130 capable of changing the frequency division ratio of the bit clock signal BC supplied from the outside according to its frequency, and a synchronization signal S supplied from the outside.
A PLL circuit 120 that operates using B as a reference signal, and the selection circuit 140 causes the bit clock signal BC
The internal clock signal φ by selecting either the output of the frequency dividing circuit 130 or the output of the PLL circuit 120 according to the frequency of
Is generated, the master clock signal is not required unlike the conventional master clock system. Moreover,
It is possible to generate an accurate internal clock signal φ without deterioration of the S / N ratio due to aliasing noise with the high frequency bit clock signal due to the jitter generated in the conventional PLL system. Furthermore, there is no restriction on the frequency of the bit clock signal BC that can be used, and by using the frequency of any bit clock signal BC,
The internal clock signal φ can be accurately generated. The present invention is not limited to the above embodiment, and various modifications can be made.
The following are examples of such modifications.

(A) In FIG. 1, the control signal S141 output from the up / down counter 141 is set to the PLL.
When used as the power-on signal and the power-off signal of the circuit 120, the power consumption of the PLL circuit 120 can be reduced when the output signal of the PLL circuit 120 is not used. For example, if the power supply or cutoff of the VCO 123 that consumes relatively large power in the PLL circuit 120 is controlled using the selection signal S141, the VCO 12
3 can reduce the power consumption. (B) In FIG. 1, the control circuits 103 and 203 are separately provided on the A / D conversion side and the D / A conversion side, but if they are configured by a common circuit, the circuit configuration becomes simpler. (C) PLL circuit 1 in the internal clock generation circuit 110
It is also possible to change 20, the frequency dividing circuit 130, or the selecting circuit 140 to another circuit configuration.

[0023]

As described in detail above, according to the first aspect of the invention, either the frequency divider circuit output or the PLL circuit output is selected by the selection circuit according to the frequency of the bit clock signal, and the internal clock is selected. Since the signal is generated, an extra master clock signal is not required unlike the conventional master clock system. Moreover, the deterioration of the S / N ratio due to the aliasing noise with the high frequency bit clock signal due to the jitter generated in the conventional PLL system is small, and an accurate internal clock signal can be generated. According to the second aspect of the invention, since the frequency dividing circuit has a variable configuration in which the frequency dividing ratio can be changed according to the frequency of the bit clock signal, there is no restriction on the frequency of the bit clock signal that can be used and any frequency can be set. The frequency of the bit clock signal can be used to generate an accurate internal clock signal. Moreover, since the selection circuit is composed of the counter and the selector, it is possible to accurately generate the internal clock signal by selecting either the frequency divider circuit output or the PLL circuit output with a simple configuration. According to the third invention, since the first and second selection signals are used as the power-on signal and the power-off signal of the PLL circuit, the consumption of the PLL circuit is reduced when the PLL circuit output signal is not used. Electric power can be reduced.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a codec showing an embodiment of the present invention.

FIG. 2 is a functional block diagram of a codec using a conventional master clock method.

FIG. 3 is a functional block diagram of a codec using a conventional PLL system.

FIG. 4 is a functional block diagram of a codec using a conventional bit clock method.

5 is a time chart of the counting operation in FIG.

[Explanation of symbols]

 101,201 SCF 102 A / D converter 103,203 Control circuit 110 Internal clock generation circuit 120 PLL circuit 121 Phase comparator 122 Filter 123 VCO 124,134 1 / N frequency divider 130 Frequency division circuit 131 Frequency coincidence detector 132 Frequency division ratio setting data selector 133 Variable frequency divider 140 Selection circuit 141 Up / down counter 142 Selector 202 D / A converter

Claims (3)

[Claims] 1. A synchronization signal for determining a sampling frequency,
And a clock generating means for generating a plurality of internal circuit operation signals from the internal clock signal by generating an internal clock signal based on the bit clock signal for inputting and outputting the digital signal from the outside. Based on the internal circuit operation signal, the analog signal that has passed through the switched capacitor filter is converted into a digital signal by an analog / digital converter and output, and a digital signal input from the outside is converted into a digital signal.
In a codec for converting into an analog signal with an analog converter, the clock generation means divides the bit clock signal, a phase lock loop circuit that operates using the synchronization signal as a reference signal, and the bit clock signal. A codec comprising: a selection circuit that selects one of the frequency division circuit output and the phase lock loop circuit output according to the frequency and outputs it as the internal clock signal. 2. The variable frequency divider divides the bit clock signal at a frequency division ratio determined by frequency division ratio setting data, and an output of the variable frequency divider at a constant frequency division ratio. A fixed frequency divider for frequency division, and a frequency coincidence detector for detecting coincidence / disagreement between the frequency of the synchronization signal and the output frequency of the fixed frequency divider and outputting a frequency coincidence signal / frequency disagreement signal accordingly A frequency division ratio setting data selector which outputs the frequency division ratio setting data based on the frequency mismatch signal and supplies the variable frequency divider with the frequency division ratio setting data selector, wherein the selection circuit counts the frequency mismatch signal and A first selection signal is output when a signal is generated above a specified value, the frequency matching signal is counted, and a second selection signal is output when the signal is generated above a specified value.
And a selector that selects the output of the phase locked loop circuit based on the first selection signal and selects the output of the frequency dividing circuit based on the second selection signal. The codec according to claim 1, wherein: 3. A configuration in which power is supplied to the phase-locked loop circuit based on the first selection signal and power supply to the phase-locked loop circuit is cut off based on the second selection signal. The codec according to claim 2, wherein the codec is a codec.