JPH06244678A - Digital filter circuit - Google Patents

Abstract

PURPOSE:To provide a digital filter circuit for providing data close to a waveform before A/D conversion. CONSTITUTION:This circuit is provided with a k-fold over sampling filter 1 for inputting the data of N bits sampled by a sampling pulse at a frequency fs, converting them to the data of (N+a) bits sampled by a sampling pulse at a frequency (kXfs) by performing k-fold over sampling, and outputting those converted data, correlation detector 2 for inputting the output data from the k-fold over sampling filter 1, plural digital low-pass filters 41, 42. with the same group delay time and the different passing frequency bands so as to input the output data from the k-fold over sampling filter 1, and selector 3 for selectively outputting one of outputs from the digital low-pass filters based on the output of the correlation detector 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter circuit, which converts N-bit data sampled by a sampling pulse having a frequency fs into a frequency (K × fs)
Of the sampling pulses of (N
The present invention relates to a digital filter circuit that converts + a) bit data and outputs the data.

[0002]

2. Description of the Related Art N-bit data sampled by a sampling pulse of frequency fs is converted into frequency (K
When converting to (N + a) -bit data sampled by a sampling pulse of (× fs) and outputting the data,
As shown in FIG. 14, the N-bit data sampled by the sampling pulse having the frequency fs is subjected to the frequency (K × fs) by the K times oversampling filter 1.
Sampled with the sampling pulse of (N +
a) It was converted into bit data and output.

[0003]

When N-bit data sampled by a sampling pulse of frequency fs is converted into (N + a) -bit data sampled by a sampling pulse of frequency (K × fs) and is output. , When the dynamic range of N-bit data sampled by the sampling pulse of frequency fs is relatively small and the frequency band is relatively low, it is K times oversampled and sampled by the sampling pulse of frequency (K × fs). (N +
a) Even if converted to bit data, most of the a bits increased by multiplication by K times oversampling are 〃
It was 0, and there was a problem that the increased dynamic range was not used effectively.

This will be specifically described. Sampling frequency fs = 44.1 kHz shown in FIG. 15 and data frequency (in this specification, the frequency of the curved waveform connecting the ends when the data value is displayed as a bar is referred to as the data frequency) f
= 1 kHz, number of bits N = 16, dynamic range D
When the data of 16 bits is passed through the 8-times oversampling filter 1, the sampling frequency is increased by 8 times, and the multiplication in the 8-times oversampling filter 1 increases the number of bits of output data. Here, it is assumed that the number of bits is 20. Further, in the drawings in this specification, the crosses on the waveform indicate sample points. Here, the output data has a sampling frequency fs = (8 × 4) as shown in FIG.
4.1) The data has a kHz, a data frequency f = 1 kHz, a bit number N = 20, and a dynamic range D = 20 bits.

Sampling frequency fs = 44.1 kHz shown in FIG. 17, which is obtained by digitizing a sine wave having a frequency of 20 kHz, whose peak-to-peak has an amplitude of 1/16 of 2
When the data of frequency f = 20 kHz, the number of bits N = 16, and the dynamic range D = 1 bit is passed through the 8 times oversampling filter 1, the sampling frequency becomes 8 times. 8 times oversampling filter 1
The number of bits of output data increases due to multiplication in
Suppose it has become 0 bit. Therefore, the output data has a sampling frequency fs = (8 × 44.1) as shown in FIG.
kHz, data frequency f = 20 kHz, number of bits N =
20, dynamic range D = 5 bits of data.

FIG. 1 is a digital representation of a sinusoidal wave having a frequency of 1 kHz and an amplitude whose peak is 1/16 of 2 to the peak.
When the sampling frequency fs = 44.1 kHz, the data frequency f = 1 kHz, the bit number N = 16, and the dynamic range D = 1 bit shown in 9 are passed through the 8-times oversampling filter 1, the sampling frequency becomes 8-times. . Moreover, the number of bits of the output data is increased by the multiplication in the 8-fold oversampling filter 1. Here, it is assumed that the number of bits is 20. Therefore, the output data has a sampling frequency fs = (8 × 4) as shown in FIG.
It is 4.1) kHz, the data frequency f = 1 kHz, the number of bits N = 20, and the dynamic range D = 5 bits, but it is understood that the dynamic range of 5 bits is not effectively used.

As described above, when the dynamic range of the input data is relatively small and the frequency of the input data is relatively low, the input data is a square wave or a staircase wave. Or it is interpolated as a staircase wave. Also in this case,
The lower 4 bits of 20 bits are mostly "0" data, and even if the dynamic range becomes 5 bits, only 1 bit is effectively used.

The present invention converts a N-bit data sampled by a sampling pulse of frequency fs into (N + a) -bit data sampled by a sampling pulse of frequency (K × fs) and outputs the digital filter circuit. Thus, even if the dynamic range of the input data is relatively small and the frequency band of the input data is relatively low, data close to the waveform before A / D conversion that effectively uses the increased a-bit dynamic range is output. It is an object to provide a digital filter circuit.

[0009]

The digital filter circuit of the present invention receives N-bit data sampled by a sampling pulse of frequency fs as an input, and performs oversampling by k times to obtain a frequency (k × fs).
Of the sampling pulses of (N
+ A) A k-fold oversampling filter that converts and outputs the data, a correlation detector that receives the output data from the k-fold oversampling filter, and a group that receives the output data from the k-fold oversampling filter. A plurality of digital low-pass filters having the same delay time and different pass frequency bands, and one of the outputs of the digital low-pass filter is selected based on the output of the correlation detector and sampled by the sampling pulse of the frequency (k × fs). And a selector for outputting (N + a) -bit data.

In the correlation detector in the digital filter circuit of the present invention, at one point of the input data, (r1) pieces of data having a correlation with the input data of the one point continuously exist before the one point. In addition, after the above 1 point, (r
2) It is characterized in that, when there are two, there is output to the selector as a selection signal for selecting the output of the digital low-pass filter based on the value of r (= r1 + r2).

In the correlation detector in the digital filter circuit of the present invention, the value of the data at the two adjacent points with (N + a) -bit data sampled by the sampling pulse of the frequency (k × fs) is present. The absolute value of the difference is less than the power of 2 to A, and the difference in the value of the a-th bit from the lower order of the data at the two points is B, and the lower order of the data at the two points is (a + 1). C that the value of the th bit is different
And then the logical expression

[0012]

[Equation 7]

When the above conditions are satisfied, the data at the two points are correlated data.

The number of taps of the digital low-pass filter in the digital filter circuit of the present invention is

[0015]

[Equation 8]

And each coefficient of the low-pass filter is

[0017]

[Equation 9]

It is characterized in that

In the digital filter circuit of the present invention,
Digital low-pass filter processes input data in order from newest input data

[0020]

[Equation 10]

[0021]

[0022]

[Equation 11]

When expressed by, the output is

[0024]

[Equation 12]

It is characterized in that

[0026]

According to the digital filter circuit of the present invention, the correlation detection output based on the dynamic range and the frequency band of the input data is output from the correlation detector, and the plurality of digital low-pass filters are output by the selection signal based on the correlation detection output. Since the output of one digital low-pass filter is selected from the output of A, even if the dynamic range is relatively low and the frequency band of the input data is relatively low, A / Data close to the waveform before D conversion is output. The reasons will be clarified one after another.

When the selection signal is r, the digital low pass filter is switched based on the selection signal r. Further, if the logical expression, if it is assumed that the data has correlation when the equation 1 is satisfied, it is determined that the flat portions of the square wave and the staircase are correlated, and both the square wave and the staircase have the correlation. Data close to the waveform before A / D conversion, which effectively utilizes the dynamic range increased by oversampling, is output.

When the number of taps of the digital low-pass filter is set to 2 and each multiplication coefficient is set to 3, the multiplication and division are simplified, and a small-scale and high-speed digital low-pass filter is obtained. When the digital low-pass filter is a digital low-pass filter satisfying the equation 6, the number of taps is the equation 2 and each multiplication coefficient is the equation 3. The digital low-pass filter is accurately approximated to the digital low-pass filter.

[0029]

EXAMPLES The present invention will be described below with reference to examples. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the embodiment of the present invention, 16-bit data sampled at a sampling pulse of 44.1 kHz is converted by a sampling pulse (8 × 44.1) kHz. The case of a digital filter circuit for converting sampled 20-bit data is illustrated.

The N-bit input data sampled by the sampling pulse of the frequency fs is supplied to the K times oversampling filter 1 and oversampled by the k times oversampling filter 1 to obtain k
The frequency (k × f
(s) is converted into (N + a) -bit data sampled by the sampling pulse.

The output from the k times oversampling filter 1, that is, the (N + a) -bit data sampled by the sampling pulse of the frequency (k × fs) is supplied to the correlation detector 2 to detect the correlation, and the correlation detection output Is the selection signal of the selector 3. In the present embodiment, the correlation detection output is the selection signal, which is also referred to as the correlation detection signal r.

The k-fold oversampling filter 1
From the digital low-pass filters 41, 4 having the same group delay time and different frequency bands.
4, ..., 4n (hereinafter, the digital low-pass filter is simply referred to as a low-pass filter) are supplied to output data having different pass frequency bands from the low-pass filters 41, 42 ,. Low pass filter 4
The outputs from 1, 42, ..., 4n are supplied to the selector 3,
1 of the outputs from the low-pass filters 41, 42, ..., 4n
One of them is selected by the selector 3 based on the selection signal from the correlation detector 2, and is sampled by the sampling pulse of the frequency (k × fs) from the selector 3 (N +
a) Output the bit data.

The correlation detector 2 is sampled by a sampling pulse of frequency (k × fs) (N +
a) At one point of the bit data, there is (r1) consecutive data before the one point and data having a correlation with the one point data (r2).
If there is one, a selection signal is output to the selector 3 according to r (= r1 + r2).

Further, the correlation detector 2 uses the frequency (k × f
At two adjacent points having (N + a) -bit data sampled by the sampling pulse of s), the absolute value of the difference between the data values at these two points is less than the a-th power of 2, and A If the difference in the value of the a-th bit from the lower-order data at the two points is B, and the difference in the value of the (a + 1) -th bit from the lower-order data in the point 2 is C, a logical expression

[0035]

[Equation 13]

When the above conditions are satisfied, the data at the two points are assumed to be correlated data.

Further, the low-pass filters 41, 42, ...
4n is the number of taps

[0038]

[Equation 14]

(M is arbitrary), and the low-pass filter 4
Each coefficient of 1, 42, ..., 4n

[0040]

[Equation 15]

It is assumed that

Further, the low pass filters 41, 42, ...
4n, low-pass filters 41, 42, ..., 4n
The input data of

[0043]

[Equation 16]

And

[0045]

[Equation 17]

In this case, the low-pass filters 41 and 4
2, ..., 4n output dout

[0047]

[Equation 18]

It is assumed that

In one embodiment constructed as described above,
When N-bit data sampled at the sampling frequency of frequency fs is converted into (N + a) -bit data sampled at the sampling frequency of frequency (k × fs) and output, the dynamic range of the input data is relatively large. Even if it is small and the frequency of the input data is relatively low, the effective dynamic range of the output can be increased by a bits. This is mainly because the low pass filter is switched based on the correlation output.

The input data of the operation of the above-described embodiment is
The sampling pulse frequency fs is 44.1 kHz, and the data frequency f is 1 kHz in the first half and 20 kHz in the second half.
A case where z, the number of bits N is 16, the dynamic range D is 1 bit, and the k-times oversampling filter 1 is an 8-times oversampling filter will be specifically described.

The above input data is as shown in FIG. When this input data is passed through the 8 times oversampling filter, the sampling frequency is increased by 8 times, and the number of bits of the output data is increased by the multiplication in the 8 times oversampling filter. Here, it is assumed that the number of bits is 20. Therefore, as shown in FIG. 3, the output data has sampling frequency fs = 8 × 44.1 kHz, data frequency f = first half 1 kHz, second half 20 kHz, bit number (N +
The data has a) = 20 bits and a dynamic range D = 5 bits. As it is, the dynamic range of 5 bits is not effectively used in the first half (the frequency f = 1 kHz portion of the data) as in the conventional case.

The low-pass filter is two low-pass filters, and the low-pass filter 41 is a through filter consisting of 63 unit delay elements 411 connected in series as shown in FIG. 5A and having only 63 clock delay (low-pass without cut-off frequency). The filter) 410, and the low-pass filter 42 adds 127 unit delay elements 421 connected in series shown in FIG. 5B to the input of the unit delay element of the first stage and the output of the unit delay element of each stage. Low pass filter 4 with a tap number of 127 and a coefficient of 1/127, which is composed of a multiplier 423 and a coefficient multiplier 424 whose multiplication coefficient is 1/127.
Twenty.

Since both the low-pass filters 410 and 420 have a group delay time of 1 clock (1/8 fs),
In order to make the low-pass filters 410 and 420 common, 63 unit delay elements 421 can be superposed and connected as shown in FIG. With this configuration, the phases are aligned and the waveform is not distorted.

One of the outputs of the above low-pass filters 410 and 420 is selected based on the output of the correlation detector 2 which detects the correlation between the data at one point of the output of the 8 × oversampling filter and the data. However, the correlation detector 2 detects the correlation between one-point data having 20-bit output that has been subjected to 8 times oversampling and data in the vicinity of the data.

This correlation detection by the correlation detector 2 is equivalent to detecting the dynamic range and frequency band of the 20-bit output that has been subjected to 8 times oversampling, and is equivalent to the output of the low-pass filter 410 and the low-pass filter. One of the output of 420 is selected based on the output of the correlation detector 2, so the output is as shown in FIG. 4A, and when the output data shown in FIG. 3 is unconditionally passed through the low-pass filter. As shown in FIG. 4B, the high frequency component is not attenuated, the dynamic range is increased by 4 bits, the dynamic range is effectively used, and the output is close to the waveform before A / D conversion. Can be obtained.

In this case, the group delay time of the low-pass filter 410 and the group delay time of the low-pass filter 420 are the same, and even if the output of the low-pass filter 410 and the output of the low-pass filter 420 are switched, the output is not distorted. The same applies when the low-pass filter 40 configured by connecting the low-pass filters 410 and 420 as shown in FIG. 6 is used.

Next, the correlation detector 2 will be described. In the correlation detector 2, at one point with 20-bit data that is 8 times oversampled, there is (r1) consecutive data before the one point, which has a correlation with the data at the one point. When there are (r2) consecutive points after one point, r (= r1 + r2) is used as the correlation detection output, and the output of the low-pass filter 410 and the output of the low-pass filter 420 are switched according to the correlation detection output. here,
When the correlation detection output r <12, the low-pass filter 410
The output of the low-pass filter 420 is selected when the correlation detection output r ≧ 12.

Here, it is assumed that input data as shown in FIG. 3 is input when the low-pass filter 40 is used, for example. The output of the low-pass filter 40 based on the correlation detection output r is 63 as shown in FIG.
The output e of the unit delay elements 421 and the output f of the coefficient multiplier 424 are switched, and in this case, as shown in FIG. 4A, filtering is performed in a flat portion of r ≧ 12 and r <12. The waveform remains as it is in the steep part. Also, there is no distortion. If switching is not performed and only the output of the coefficient multiplier 424 is used, the output has a waveform as shown in FIG. 4B and the high frequency component is attenuated.

Next, the criteria for the presence or absence of correlation in the correlation detector 2 will be described. In the correlation detector 2, it is confirmed that the absolute value of the difference between the data values at two adjacent points of the 8-bit oversampled 20-bit data is less than 2 4 = 16. Let A be the difference in the value of the fourth bit from the lower order of the data at the two points, and B be the difference in the value of the fifth bit from the lower order of the data at the two points be C
In this case, when the logical expression, Formula 1, is satisfied, the data at the two points are regarded as correlated data.

For example, the sampling frequency fs = 44.
When the data shown in FIG. 7 having 1 kHz, the data frequency f = 1 kHz, and the dynamic range D = 1 bit is oversampled by 8 times, the output data has a sampling frequency fs = 8 × 44.1 kHz and a data frequency f as shown in FIG.
= 1 kHz, dynamic range D = 5 bits of data. Here, the flat part of the square wave and the staircase wave must be judged as a correlated data string. In the case of FIG. 8, the portion S1 between FFFE8 and FFFF7 must be judged as correlated data. Also FFFF8
The portion S2 between ˜00007 must be judged as correlated data.

The criterion for this is the equation 1. When Equation 1 is used as the criterion, it is determined that the flat portions of the square wave and the staircase wave are the correlated data strings. Parts S1 and S
The low-pass filter 410 based on the number of data strings of 2
, And the output of the low pass filter 420 must be selected. In this case, both parts S1 and S2 are 17
It is preferable to select the output of the low-pass filter having 0 to 180 pieces (in the case of 8 × 44.1 kHz / 2 × 1 kHz), and the number of taps is approximately the same as the number.

Next, the low-pass filter in this embodiment will be described. The tap number of the low-pass filter is 2,
That is, (2 m −1) is set, and each coefficient of the low-pass filter is set to Expression 3, that is, 1 / (2 m −1). By doing so, multiplication and division are simplified, and a small-scale and high-speed low-pass filter can be obtained.

When m = 7, the number of taps is 12
7, each coefficient is 1/127. Therefore, Σ ₁ =
(D0) + (d-1 ) + ... + (d-126) and an output dout is, dout = sigma _1/127, and the hardware of the low-pass filter as shown in FIG. 5 (b), the unit delay elements 127, one adder, multiplication coefficient 1/127
This is a low-pass filter with one coefficient multiplier.

If this is left as it is, the calculation error becomes large in the part of the coefficient multiplier of the multiplication coefficient 1/127.
_{ut = Σ 1/127 = (} d-63) + [Σ 1 -127 ×
(D-63)] / 127 ≒ (d-63) + [Σ 1 -12
7 × (d−63)] / 128, and a low-pass filter is constructed based on this equation, which allows accurate approximation. The low-pass filter in this case has 127 unit delay elements, as shown in FIG.
This uses three adders, a coefficient multiplier with a multiplication coefficient (−128), and a coefficient multiplier with a multiplication coefficient of 1/128.

Next, a specific example of one embodiment of the present invention will be described. FIG. 10 is a block diagram showing a specific example of an embodiment of the present invention.

In the specific example shown in FIG. 10, data having a sampling frequency fs = 44.1 kHz and a bit number N = 16 is converted into a sampling frequency fs = 8 × 44.1 kHz,
This is a case of a digital filter circuit that converts data with the number of bits N = 20, where the number of increasing bits a = 4 and the number of taps of the low-pass filter are 〃1〃 and 〃127〃, that is m = 1 and 127 (1 Tap low pass filter (through) and 127 tap low pass filter)
The output of the low-pass filter is selected by selecting the output of the 1-tap low-pass filter when the selection signal r <12.
When ≧ 12, the output of the 127-tap low-pass filter is selected. In this specific example, the output of the comparison circuit 15 described later is substantially a selection signal, and is therefore referred to as a selection signal r.

The 16-bit input data sampled by the sampling pulse having the frequency of 44.1 kHz is oversampled by the 8 × oversampling filter 11, and the output data of the 8 × oversampling filter 11 is sent to the unit delay element 12, The output data of the double oversampling filter 11 and the output data of the unit delay element 11 are supplied to the correlation detector 13 to detect the correlation. The correlation detection output of the correlation detector 13 is supplied to the counting circuit 14 to count the number of consecutive correlated data, and the count value of the counting circuit 14 is compared with the reference data 12 by the comparison circuit 15 to select the signal. r is r
It is detected whether <12 or r ≧ 12. This detection output becomes the selection signal r for selecting one of the outputs of the low-pass filter, and the selection signal r is stored in the memory circuit 16.

On the other hand, the oversampling filter 11
The continuous output of 127 of the oversampling filter 11 is sequentially sent to and stored in the memory circuit 17, and the data read from the memory circuit 17 is supplied to the selector 23 as one input. Here, the memory circuit 17 constitutes a 1-tap low-pass filter F1.

12 consecutive data read from the memory circuit 17
The seven pieces of data are cumulatively added by the cumulative adder 18. The cumulative addition output data of 127 pieces of data is output from the cumulative adder 18. The cumulative addition output data, the output data read from the storage circuit 17, and the output data obtained by multiplying the output data read from the storage circuit 17 by the coefficient multiplier 19 of the multiplication coefficient (-128) (-128) are added by the adder 20. However, the output data from the adder 20 has a multiplication coefficient of 1/128.
Of the coefficient multiplier 21 is multiplied by 1/128, the output data from the coefficient multiplier 21 and one input of the selector 23 are added by the adder 22, and the output data from the adder 22 is used as the other input of the selector 23. Supply to.

Here, the memory circuit 17 and the adders 18 and 20
And 22, and the coefficient multipliers 19 and 21 constitute a 127-tap low-pass filter F2.

One of the output data of the low pass filter F1 and the output data of the low pass filter F2 is selected and output by the selector 23 by the selection signal r read from the memory circuit 16.

It is now assumed that the waveform data shown in FIG. 11 is input to the oversampling filter 11. The frequency of this input data is f = 20 kHz in the section α.
z, dynamic range D = 1 bit, frequency f of input data f = 1 kHz, dynamic range D =
1 bit, frequency f = 1kH of input data in section γ
z, dynamic range D = 16 bits.

By the input of this input data, the output data of the oversampling filter 11 becomes as shown in FIG.
As shown in FIG. 2, in the section α, the frequency f = 20 kHz, the dynamic range D = 5 bits, the first half section β _{1 of the} section β
At frequency f = 1 kHz, dynamic range D = 5 bits, and in the latter half of section β of section β ₂ , frequency f = about 20 kHz due to the influence of section γ and dynamic range D = 5 to 1
Ringing of about 0 bit occurs. In the section γ, the data has a frequency f = 1 kHz and a dynamic range D = 20 bits.

In the section α, since the dynamic range is small but the frequency is high, the selection signal r is about 8 and never exceeds 12. Therefore, in the section α, the low-pass filter F
The output data from 1 is selected, and the through data delayed by 63 clocks is output from the selector 23.

In the section β ₁ , since the dynamic range is small and the frequency is low, the selection signal r is 100 or more, so that the selector 23 outputs the low-pass filter F2.
Output data from the selector 23 is selected and the filtered data having a group delay time of 63 clocks is selected by the selector 23.
Is output from. As in the case of the section α, the section β ₂ has a small dynamic range but a high frequency, so that the selection signal r does not exceed 12. Therefore, in the section β ₂ , the output data from the low pass filter F1 is selected, and the through data delayed by 63 clocks is output from the selector 23.

In the section γ, the frequency is low but the dynamic range is large, so that the selection signal r does not exceed 12 or more. Therefore, in the section γ, the output data from the low-pass filter F1 is selected, and the through data delayed by 63 clocks is output from the selector 23.

From the above, the waveform of the output data from the selector 23 is as shown in FIG. As a result,
Only the data whose waveform is flat and whose lower 4 bits are close to "0" are filtered, and the data close to the waveform before A / D conversion that effectively uses the increased 4-bit dynamic range can be output. it can.

[0078]

As described above, according to the digital filter circuit of the present invention, the dynamic range of input data is relatively small, and the a-bit dynamic range increased by oversampling is obtained even when the frequency band of the input data is low. It is effectively used and has an effect that data close to the waveform before A / D conversion can be obtained.

Equation 1 in correlation detection in the correlation detector
When the above condition is satisfied, and there is a correlation in the data between the two points, there is an effect that there is a correlation in the flat portion of the square wave or the staircase wave.

The number of taps of the low-pass filter is set to 2, and
When the coefficient of the low-pass filter is set to 3, a low-pass filter that is small in size and capable of high-speed processing is effective.

When the low-pass filter is constructed so as to satisfy the equation 6, the number of taps is set to the equation 2 and the coefficient is set to the equation 3 to obtain an approximate low-pass filter with good accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a schematic diagram of signals for explaining the operation of one embodiment of the present invention.

FIG. 3 is a schematic diagram of signals for explaining the operation of one embodiment of the present invention.

FIG. 4 is a schematic diagram of signals for explaining the operation of one embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a low-pass filter according to an embodiment of the present invention.

FIG. 6 is a block diagram showing the configuration of a low-pass filter according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of signals for explaining the operation of one embodiment of the present invention.

FIG. 8 is a schematic diagram of signals for explaining the operation of one embodiment of the present invention.

FIG. 9 is a block diagram showing another configuration of the low-pass filter according to the embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a specific example of an exemplary embodiment of the present invention.

FIG. 11 is a schematic diagram of signals for explaining the operation of the specific example of the embodiment of the present invention.

FIG. 12 is a schematic diagram of signals for explaining the operation of the specific example of the embodiment of the present invention.

FIG. 13 is a schematic diagram of signals for explaining the operation of the specific example of the embodiment of the present invention.

FIG. 14 is a lock diagram showing a configuration of a conventional example.

FIG. 15 is a schematic diagram of signals for explaining the operation of the conventional example.

FIG. 16 is a schematic diagram of signals for explaining the operation of the conventional example.

FIG. 17 is a schematic diagram of signals for explaining the operation of the conventional example.

FIG. 18 is a schematic diagram of signals for explaining the operation of the conventional example.

FIG. 19 is a schematic diagram of signals for explaining the operation of the conventional example.

FIG. 20 is a schematic diagram of signals for explaining the operation of the conventional example.

[Explanation of symbols]

1 K times oversampling filter 2 and 13 Correlation detector 3 and 23 Selector 12 Unit delay element 14 Count circuit 15 Comparison circuit 16 and 17 Storage circuit 18 Cumulative adder 41, 42, 4n, 40, 410, 420, F1 and F2 , Low pass filter

Claims (5)

[Claims] 1. Input of N-bit data sampled by a sampling pulse of frequency fs, and k
Frequency (k × f
s) a k-fold oversampling filter for converting and outputting to (N + a) -bit data sampled by the sampling pulse, and a correlation detector having the output data from the k-fold oversampling filter as an input,
A plurality of digital low-pass filters having the same group delay time and different pass frequency bands and the output data from the k-fold oversampling filter, and one of the outputs of the digital low-pass filter are selected based on the output of the correlation detector. And a selector for outputting (N + a) -bit data sampled by a sampling pulse of frequency (k × fs). 2. The digital filter circuit according to claim 1, wherein the correlation detector has one of the input data at one point.
When there is (r1) continuous data before the 1 point and (r2) continuous data after the 1 point, the value of r (= r1 + r2) is obtained. A digital filter circuit which outputs to a selector as a selection signal for selecting the output of the digital low-pass filter based on the above. 3. The digital filter circuit according to claim 1 or 2, wherein the correlation detector is sampled by a sampling pulse of a frequency (k × fs) (N +
a) At two adjacent points having bit data, it is assumed that the absolute value of the difference between the data values at the two points is less than the a-th power of 2, and A is the second from the lower order of the data at the two points. Letting B be a different bit value and C be a different (a + 1) th bit value from the lower order of the data at the two points, the logical expression The digital filter circuit is characterized in that the data at the two points are correlated data when the above condition is satisfied. 4. The digital filter circuit according to claim 1, wherein the digital low-pass filter has a tap number of And each coefficient of the low-pass filter is given by A digital filter circuit characterized by the following. 5. The digital filter circuit according to claim 1, wherein the digital low-pass filter inputs the input data in order from new input data. And, , The output is A digital filter circuit characterized by the following.