JPH06242746A - Dc offset correcting circuit and display processor - Google Patents

Abstract

PURPOSE:To automatically detect a DC-like offset generated by a DC cutting capacitor and correcting a threshold value on the basis of it, and to perform stable display operation at all times even if the value varies according to display contents as to the improvement of the DC offset correcting circuit and display processor. CONSTITUTION:The DC offset correcting circuit is equipped with a threshold voltage generating circuit 11 which outputs a threshold voltage Vo on the basis of an image input signal Vin and a horizontal synchronizing signal *Hs and a signal processing circuit 12 which corrects the DC offset of the image input signal V in on the basis of the threshold voltage Vo; and the threshold voltage generating circuit 11 samples and holds the DC offset level in the horizontal blanking period of the image input signal Vin and outputs the threshold voltage Vo of the horizontal display period of a next image input signal Vin to the signal processing circuit 12 and the display processor uses this DC offset correcting circuit as an analog interface circuit 13 which inputs video signals R, G, and B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC offset correction circuit and a display processing device, and more specifically, a circuit for removing the influence of a DC offset voltage caused by a coupling capacitance between a transmitter and a receiver and its application. It concerns the improvement of the device.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory diagram of a signal transmitting / receiving circuit of an image device according to a conventional example. Further, FIG. 4A is a schematic diagram between the transmitting and receiving circuits according to the conventional example, and FIG. 4B shows the signal waveform diagram thereof.

For example, when a computer is connected to a matrix type display or the like to perform various display processes,
In FIG. 4A, a video data output element 1 on the transmission side (computer) that sends out a video data signal Vin and an analog interface element 3 on the reception side (display).
A coupling capacitor Cc is used between and.
The coupling capacitor Cc is connected for the purpose of cutting the DC component contained in the video data signal Vin,
The analog interface element 3 compares and inputs the video data signal Vin of the AC component input via the capacitor Cc based on the constant threshold potential generated by the threshold generation circuit 2, and the display data signal Vout as the next stage circuit. Output to. This allows the computer to display
R (red), G (green), B (blue) as shown in FIG.
The video data signal Vin, the horizontal synchronizing signal * Hs, and the vertical synchronizing signal * Vs can be supplied. In addition, 4 is a horizontal synchronizing signal output element, 5 is a vertical synchronizing signal output element, and 6 is an inverter.

[0004]

By the way, according to the video data output device 1 according to the above-mentioned conventional example, in order to prevent the direct current component from being involved with the analog interface device 3, the direct current component is output to the output part. A cut capacitor Cc is connected, but D according to the content of the video data signal Vin of one line (one scanning line) sent to the display.
The C offset is stored in the DC-cutting capacitor Cc, which causes a problem that the display quality is deteriorated. Here, in order to simplify the description, the case where the display on the display has only two values of lighting and non-lighting will be described. For example, depending on the amount of data corresponding to the pixels to be lit and displayed, the capacitor Cc may be changed. This is because the amount of stored charges is different, and as a result, a DC offset is generated on the receiving side and the value thereof fluctuates. That is, when the DC-cutting capacitor Cc is adopted, the DC offset differs for each line due to the difference in display contents such as full lighting, full extinction, and half lighting. If this is compared and input to the video data signal Vin based on a constant threshold potential generated by the threshold generation circuit 2, it becomes difficult to determine whether the data corresponds to lighting or non-lighting, and as a result, , The display screen flickers, and a stable screen cannot be obtained.

The present invention is intended to solve the above-mentioned problems, in the case where a DC-cutting capacitor causes a DC-like offset at a video data receiving terminal and the value thereof varies depending on the displayed contents. Another object of the present invention is to provide a DC offset correction circuit and a display processing device capable of always performing a stable display operation by automatically detecting the size and correcting the threshold value of the data signal processing circuit.

[0006]

In order to solve the above problems SUMMARY OF THE INVENTION The means of the DC offset correction circuit taken by the invention, as shown in FIG. 1, the image input signal Vin and the horizontal synchronizing signal H _S A threshold voltage generation circuit 11 that outputs a threshold voltage Vo based on the threshold voltage Vo, and an image input signal V based on the threshold voltage Vo.
and a signal processing circuit 12 for correcting the DC offset of in, and the threshold voltage generating circuit 11 performs DC offset level sample hold during the horizontal blanking period of the image input signal Vin, and based on this, the next image Input signal Vin
The threshold voltage Vo is output to the signal processing circuit 12 during the horizontal display period.

Further, the threshold voltage generation circuit 11 of the DC offset correction circuit of the present invention turns on the sampling switch SW in synchronization with the horizontal blanking period to directly sample the DC offset voltage contained in the image input signal Vin. It is characterized by having a sample hold circuit for charging Cs.

Further, the means of the display processing device according to the present invention is driven and displayed by a method similar to the image display means 13 based on the video signals R, G, B, the horizontal synchronizing signal * Hs and the vertical synchronizing signal * Vs. In the matrix type display processing device described above, an analog interface circuit 13 for inputting video signals R, G, B is provided, and the DC offset correction circuit of the present invention is used for the analog interface circuit 13.

[0009]

According to such means, the DC offset correction circuit of the present invention comprises the threshold voltage generation circuit 11 and the signal processing circuit 12, and during the horizontal blanking period of the image input signal Vin,
The DC offset level is sampled and held by the threshold voltage generation circuit 11.

For example, the sampling switch SW of the threshold voltage generating circuit 11 is turned on in synchronization with the horizontal blanking period.
The N operation is performed, and the DC offset voltage included in the image input signal Vin is directly held in the sampling capacitor Cs. In the horizontal display period of the next image input signal Vin,
The threshold voltage Vo automatically generated based on the potential charged in the capacitor Cs is output to the signal processing circuit 12. Therefore, a DC offset occurs in the video data receiving terminal due to the DC cutting capacitor as in the conventional example,
Even if the value fluctuates depending on the display content, the threshold value of the signal processing circuit 12 is automatically corrected by automatically detecting the magnitude by the sample hold circuit of the threshold voltage generating circuit 11. Is possible. This makes it possible to remove the influence of the DC offset of the image input signal Vin based on the automatically corrected threshold voltage Vo.

Further, according to the display processing apparatus of the present invention, the DC offset correction circuit of the present invention is used in the analog interface circuit 13 for inputting the video signals R, G, B.

Therefore, in the matrix type display processing device which is driven and displayed by a method according to the image display means on the basis of the video signals R, G, B, the horizontal synchronizing signal * Hs and the vertical synchronizing signal * Vs, a DC offset is generated. In the signal processing circuit 1, the result value obtained by adding the DC offset included in the image input signal Vin to the threshold value set corresponding to the case where there is no
It can be used as a threshold value of 2. As a result, it is possible to always perform a stable display operation without being affected by the magnitude of the DC offset that varies depending on the display content of the display processing device.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a principle diagram of a DC offset correction circuit and a display processing device according to the present invention, FIG. 2 is a configuration diagram of a display processing device including a DC offset correction circuit according to an embodiment of the present invention, and FIG. The signal waveform diagrams of the DC offset correction circuit are shown respectively.

For example, a DC offset correction circuit applicable to the analog interface circuit 13 of a matrix type display processing device (hereinafter referred to as a display) is shown in FIG.
In, a threshold voltage generating circuit 11, a signal processing circuit 12, resistance elements R1 to R7, and the like. That is, the threshold voltage generation circuit 11 includes the sample hold circuit 11A and the amplifier circuit.
11B and an inverting addition circuit 11C, which outputs a threshold voltage Vo to the signal processing circuit 12 based on the image input signal Vin and the horizontal synchronizing signal * Hs. For example, a sample and hold circuit
11A includes a MOS transistor, which is an example of the sample switch SW, and a sample hold capacitor Cs,
The sample switch SW is turned on by the horizontal synchronizing signal * Hs.
N / OFF controlled. The amplifier circuit 11B has a gain of -1.
It is composed of a double operational amplifier OP and a resistance element R2. The inverting addition circuit 11C is composed of an operational amplifier OP having a gain of -1 and resistance elements R5 to R7. The values of the resistance elements R5 to R7 are all the same in order to realize the gain of -1 (R5. = R6 = R7). Further, resistors R3 and R4 for generating the reference voltage Vref are connected to the inverting input portion of the operational amplifier OP. Further, the signal processing circuit 12 is connected to the threshold voltage generating circuit 11 and the input resistor R1, inputs the image input signal Vin based on the threshold voltage Vo, and outputs the display data output signal Vout whose DC offset is corrected to the next stage circuit. Output. A coupling capacitor Cc is used between the video data output element 1 on the transmitting side (computer) that sends out the video data signal Vin and the signal processing circuit 12 on the receiving side (display), and the coupling from the transmitting side to the receiving side is performed. , R
(Red), G (green), B (blue) video data signals Vin,
The horizontal synchronizing signal * Hs and the vertical synchronizing signal * Vs are supplied.

Next, the operation of the DC offset correction circuit will be described. FIG. 3 is a signal waveform diagram of the DC offset correction circuit according to the embodiment of the present invention. In FIG. 3, the analog switch is turned on while the horizontal synchronizing signal * Hs sent from the transmitting side is at the “L” level, and the image input signal Vin
The DC offset voltage (−ΔV) included in the sampling capacitor Cs is stored in the sampling capacitor Cs. The polarity of the stored voltage ΔV is inverted (+ Δ) by the operational amplifier OP having a gain of −1 times.
V) and is guided to the inverting addition circuit 11C. Further, the reference voltage Vref generated in the resistors R3 and 4, that is, the optimum threshold value set when the DC offset is not included is given to the inverting input portion of the inverting addition circuit 11C. However, in this case, the size is equivalent to the conventional example, but the polarity is negative (-Vref) due to the convenience of connecting the inverting adder circuit 11C after the operational amplifier OP having the gain of -1 times. Has been done. These inputs (-Vref + ΔV) are added by the amplifier OP of the inverting addition circuit 11C with a gain of −1, so that the output becomes Vref−ΔV, and during the horizontal display period of the next image input signal Vin, The automatically generated threshold voltage Vo is output to the signal processing circuit 12. This allows
The DC offset voltage is automatically corrected.

When an inverting operational amplifier OP is connected to the output of the sampling capacitor Cs as in this example, a voltage error (ΔVer: error voltage = Ib (bias current) × (holding time) / Cs)
May be a problem. In such a case, one stage of the voltage follower circuit may be inserted between the capacitor Cs and the amplifier OP.

Thus, the D according to the embodiment of the present invention is
According to the C offset correction circuit, the threshold voltage generation circuit 11
And the signal processing circuit 12, and the DC voltage is generated by the threshold voltage generating circuit 11 during the horizontal blanking period of the image input signal Vin.
The offset level is sampled and held. Therefore, even if a DC offset occurs in the video data receiving terminal due to the DC-cutting capacitor Cc as in the conventional example, and the value varies depending on the display content, the magnitude of the threshold voltage is generated. The threshold value of the signal processing circuit 12 can be automatically corrected by automatically detecting it by the sample hold circuit of the circuit 11 or the like. This makes it possible to remove the influence of the DC offset of the image input signal Vin based on the automatically corrected threshold voltage Vo.

Further, according to the display processing device of the embodiment of the present invention, the DC offset correction circuit of the present invention is used in the analog interface circuit for inputting the video signals R, G, B. Therefore, when there is no DC offset in the matrix type display driven and displayed by a method similar to that of a CRT or a liquid crystal panel based on the video signals R, G, B, the horizontal synchronization signal * Hs and the vertical synchronization signal * Vs. To the threshold value set corresponding to
The result value obtained by adding the DC offset included in in can be used as the threshold value of the signal processing circuit 12. As a result, the R, G, and B image input signals Vin are normally output directly from the output device to the outside, and there is no need to consider DC fluctuations due to the displayed contents. A stable operation can be obtained only by comparing the signal Vin with a fixed constant level threshold value. From this, it is possible to always perform a stable display operation without being affected by the magnitude of the DC offset that varies depending on the display content of the display processing device.

Since a circuit that feeds back the DC offset voltage to the threshold value generation circuit of the signal processing circuit 12 can be configured only when the DC offset exists, the direct current in the video data output element as in the conventional example can be constructed. The method of the present invention can be applied regardless of the presence or absence of the cutting capacitor Cc.

Further, in the embodiment of the present invention, in order to simplify the description, the ON-OFF operation of the sample switch SW 2 is performed.
Although the display method for values has been described, it is also effective when the maximum amplitude of each R, G, B data is divided into equal parts to display subtle color tones, as in the case of gradation display. Needless to say.

[0021]

As described above, according to the DC offset correction circuit of the present invention, it is composed of the threshold voltage generating circuit and the signal processing circuit, and the DC voltage is corrected by the threshold voltage generating circuit during the horizontal blanking period of the image input signal Vin. The offset level is sampled and held.

Therefore, even if a DC offset occurs in the video data receiving terminal due to the DC cutting capacitor as in the prior art, and the value fluctuates depending on the display content, the magnitude of the DC offset is set to the threshold value. It is possible to automatically correct the threshold value of the signal processing circuit by automatically detecting it by the sample hold circuit of the voltage generation circuit or the like.

Further, according to the display processing apparatus of the present invention, the DC offset correction circuit of the present invention is used as the analog interface circuit for inputting the video signal. For this reason,
In a matrix type display processing device driven and displayed by a method similar to an image display means on the basis of a video signal, a horizontal synchronizing signal and a vertical synchronizing signal, an image is input to a threshold value set corresponding to the case where there is no DC offset. The result value obtained by adding the DC offset included in the signal can be used as the threshold value of the signal processing circuit. As a result, the influence of the DC offset of the image input signal can be eliminated based on the automatically corrected threshold voltage, which largely contributes to the provision of a highly reliable display processing device that always performs a stable display operation.

[Brief description of drawings]

FIG. 1 is a principle diagram of a DC offset correction circuit and a display processing device according to the present invention.

FIG. 2 is a configuration diagram of a display processing device including a DC offset correction circuit according to an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the DC offset correction circuit according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a signal transmission / reception circuit of an image device according to a conventional example.

[Explanation of symbols]

 11 ... Threshold voltage generation circuit, 12 ... Signal processing circuit, 13 ... Analog interface circuit, SW ... Sample switch, Cc ... Sample hold capacitor, * Hs ... Horizontal sync signal, * Vs ... Vertical sync signal, Vin ... Image input signal.

Claims (3)

[Claims] 1. A threshold voltage generating circuit that outputs a threshold voltage based on an image input signal and a horizontal synchronizing signal; and a signal processing circuit that corrects a DC offset of the image input signal based on the threshold voltage. The threshold voltage generating circuit samples and holds a DC offset level during a horizontal blanking period of the image input signal, and based on this, outputs the threshold voltage to a signal processing circuit during a horizontal display period next to the image input signal. A DC offset correction circuit characterized by: 2. The DC offset correction circuit according to claim 1, wherein the threshold voltage generation circuit turns on a sampling switch in synchronization with a horizontal blanking period to directly sample the DC offset voltage included in the image input signal. A DC offset correction circuit having a sample hold circuit for charging a capacitor. 3. A matrix type display processing device, which is driven and displayed based on a video signal, a horizontal synchronizing signal and a vertical synchronizing signal by a method according to an image display means, is provided with an analog interface circuit for inputting the video signal. A display processing apparatus, wherein the DC offset correction circuit according to claim 1 or 2 is used in the analog interface circuit.