JPH06237181A - Data compression circuit - Google Patents

Abstract

PURPOSE:To provide the compression circuit in which data quantity is considerably reduced. CONSTITUTION:Output data DH of an A/D converter are fed to a correction means 21, and when only middle data in three consecutive data differ, the middle data are set equal to preceding and succeeding data. Output data DH1 from the correction means 21 are fed to a detection means 22 to calculate a predicted value by using two just preceding data with respect to each of data DH1 and a difference from the predicted value is obtained. Output data DH2 of the detection means 22 are fed to a code bit shift means 23. When the MSB of the data DH2 is logical 1, a 2's complement is obtained and the result is shifted by one bit toward high-order bits and a sign bit of logic 1 is added to the LSB. When the MSB of the data DH2 is logical 0, the data are shifted by one bit toward the high order bits and a sign bit of logical O is added to the LSB. Output data DH3 of the shift means 23 are fed to a common processing means 24, data are classified into plural bit data based on a valid bit and common processing is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data compression circuit suitable for use in a Holter system (long-time electrocardiographic recorder).

[0002]

2. Description of the Related Art It has been conventionally known to record an electrocardiographic waveform signal from an electrocardiographic waveform measuring device on a magnetic tape or the like in the form of an analog signal. However, there are problems such as poor reproduction accuracy due to head characteristics and the like. Therefore, conventionally, in order to improve the reproducibility, it has been proposed to record an electrocardiographic waveform signal on a magnetic tape, a semiconductor memory or the like in the form of a digital signal.

[0003]

By the way, the Holter system, for example, continuously records electrocardiographic waveform signals for 24 hours, has a very large amount of recorded data, and requires a recording medium suitable for it. There were problems such as.

Therefore, an object of the present invention is to provide a data compression circuit capable of significantly reducing the amount of data.

[0005]

According to the present invention, when only the central data of three consecutive input data are different, the central data is the same as the preceding and following data, and Data difference detecting means for calculating an expected value by using the immediately preceding two data for each of the output data of the data correcting means and detecting a difference from the expected value, and output data of the data difference detecting means. If the most significant bit of the is a logical one, a two's complement is obtained, then one bit is shifted to the upper bit side, the code bit of the logical one is added to the least significant bit, and the most significant bit of the output data is a logical zero. If so, a code bit moving means for shifting the higher bit side by 1 bit as it is and adding a code bit of logical 0 to the least significant bit, and the output of this code bit moving means Enable chromatography data bit is what and a data sharing means for the common processing of data classified into a plurality of different bit data.

[0006]

In the present invention, the data correcting means 21, the data difference detecting means 22 and the sign bit moving means 23 are processed to increase the number of similar data,
Since the data commonizing unit 24 collects similar data and standardizes the data, the data amount can be significantly reduced. Further, since similar data is output as the compressed data from the data commonizing means 24, when the data is further compressed using a compression method capable of 100% expansion such as the Huffman method or the LZW (Lample-Ziv-Welch) method. Can increase the compression efficiency.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. This example is an example applied to a recording system of a Holter system for recording an electrocardiographic waveform signal with a digital VTR.

FIG. 1 is a block diagram showing the overall configuration of the Holter system. In the figure, an analog electrocardiographic waveform signal SH output from an electrocardiographic waveform measuring device (not shown)
Is supplied to the A / D converter 1, and the sampling frequency is 2
It is converted into a digital signal at 50 Hz and 10 bits per sample. The data of each sample is treated as 16-bit data in the following processing.

The electrocardiographic waveform data DH output from the A / D converter 1 is subjected to data compression processing by the data compression circuit 2 and then supplied to the digital VTR 3 for recording. The data compression circuit 2 is configured by including a microcomputer (hereinafter referred to as "microcomputer"), and the data compression processing is performed by software with the microcomputer.

FIG. 2 is a functional block diagram showing the configuration of the data compression circuit 2. In the figure, the electrocardiographic waveform data DH output from the A / D converter 1 is supplied to the data correction means 21. In the correcting means 21, when only the central data of the three consecutive data DH output from the A / D converter 1 is different, the central data is processed to be the same as the preceding and following data. Is performed.

For example, the data DH is 03F3H 03F
4H 03F3H When continuous, 03F3H 03F3H
It will be 03F3H. Here, “H” indicates hexadecimal display. The same applies to the following.

As described above, when the sampling frequency in the A / D converter 1 is set to 250 Hz, 125 which is a half frequency of the sampling frequency is 125 according to the well-known sampling theorem.
Can be completely restored up to Hz. However, in the case of the electrocardiographic waveform, it is not considered that the frequency band up to 125 Hz is necessary, and 125 H is obtained by the above-mentioned processing by the correction means 21.
The frequency component of z can be removed, thereby increasing similar data.

Next, the data DH1 output from the correction means 21 is supplied to the data difference detection means 22. In the detection means 22, the immediately preceding 2 for each of the data DH1.
The expected value is calculated using the data, and the difference from the expected value is detected.

For example, when the data DH1 is continuous with x1, x2, x3, x4, x5, ... As shown in FIG.
The expected value x3 'for x is set to x1 + 2 (x2-x1),
The expected value x4 'for x4 is set to x2 + 2 (x3-x2), and the expected values x5', x6 ', ... Are calculated in the same manner. Then, the difference .DELTA.x3 is set to x3'-x3 with respect to x3, the difference .DELTA.x4 is set to x4'-x4 with respect to x4, and the differences .DELTA.x5, .DELTA.x6 ,. In the calculation of the above-mentioned predicted value, the calculation of doubling the difference between the immediately preceding two data is performed, but "double" is an example,
It is not limited to this.

From the detecting means 22, when the difference is positive, it is outputted as it is, and when the difference is negative, it is outputted in 2's complement.

Next, the data DH2 output from the detecting means 22 is supplied to the sign bit moving means 23. In this moving means 23, the data DH2 (b15, b14, ...
16-bit data of b0) most significant bit (MSB) b1
It is processed as follows according to the logic state of 5.

That is, the most significant bit b of the data DH2
When 15 is a logic 1, the 2's complement of the data DH2 is obtained, and then one bit is shifted to the upper bit side and the code bit of the logic 1 is added to the least significant bit (LSB) b0. For example, when the data DH2 is "FFFFH", the bit b15 is logic 1, and when the complement of 2 is obtained, it becomes "0001H", and the sign bit of logic 1 is added to the bit b0 after shifting 1 bit to the upper bit side. Then it becomes "0003H".

On the other hand, when the most significant bit b15 of the data DH2 is a logical 0, it is shifted by 1 bit to the upper bit side as it is and a code bit of logical 0 is added to the least significant bit b0. For example, the data DH2 is "0001H"
, The bit b15 is a logical 0, and if the sign bit of the logical 0 is added to the bit b0 after shifting by 1 bit to the upper bit side, it becomes "0002H".

FIG. 4 shows the correspondence between the data DH2 output from the detecting means 22 and the data DH3 output from the moving means 23.

Next, the data DH3 output from the moving means 23 is supplied to the data commonizing means 24 to
Is processed.

The data DH3 is classified into three types of data of valid 4 bits, valid 8 bits, and valid 16 bits based on the valid bits. For example, "0004
"H", "0005H", etc. are effective 4-bit data,
“0080H”, “0090H”, etc. are valid 8-bit data, and “0100H”, “0200H”, etc. are valid 16 bits.
It is bit data. When this classification is performed, a header is placed before each type of data so that the content of each type can be understood.

Here, the header has bits b7 to b0, for example.
1 byte data. The header has the following meanings, for example. That is, 2 of "b7b6"
The type of data is represented by bits. For example,
“00” indicates valid 4-bit data, “01” indicates valid 8-bit data, and “10” indicates valid 16-bit data. Also, the 6 bits of "b5 to b0" represent the number of chunks of bit data. The number is 01H to 3FH
(1 to 63) can be represented.

The effective 4-bit data is in 8-bit units. In this case, if the same data is not continuous, bits b15 to b8 are removed to obtain 8-bit data. When the same data continues, 8-bit data "b7-b0" is formed as follows. That is, the continuous number of the same data is represented by 4 bits of "b7 to b4". Here, 0H to FH (0 to 15) are shown, but it is considered that 0 to 15 represents 1 to 16. Also, 4-bit data is represented by 4 bits of "b3 to b0".

For example, 0004H 0005H 0005H
The data of 0005H 0005H 0005H 0006H becomes 04H 45H 06H.

The effective 8-bit data is in 8-bit units. In this case, bits b15 to b8 are removed and 8
It is treated as bit data.

For example, 0010H 0020H 0030H
The data of 0040H 0050H 0060H is 10H 2
It becomes 0H 30H 40H 50H 60H.

As described above, in the data commonizing means 24,
The processing of is performed. For example, 0004H 0005
H 0005H 0005H 0005H 0005H 0006
The data of H 0080H 0090H 0100H 0200H is 03H 04H 45H 06H 42H 80H 90H 82
It becomes H 0100H 0200H. Where 03H, 42
H and 82H are headers.

Next, the data DH4 output from the commonizing means 24 is lossless compression means 25.
Is supplied to. In the compression means 25, data compression processing is performed using a compression method capable of 100% expansion such as the conventionally known Huffman method or LZW (Lample-Ziv-Welch) method.
The data DH5 output from the compression means 25 is supplied to the digital VTR 3 as the output of the data compression circuit 2.

Thus, in this example, the correction means 2
1. After being processed by the detecting means 22 and the moving means 23 so that similar data is increased, the commonizing means 2
Since the similar data are collected by 4 and the data is made common, the amount of data can be significantly reduced. Further, since similar data is output from the commonizing means 24 as compressed data, the Huffman method or LZ in the compressing means 25 is output.
The compression efficiency of data compression by a compression method such as the W (Lample-Ziv-Welch) method can be increased.

For example, the output data DH of the A / D converter 1
Is as shown in FIG. 5, the output data DH1, DH3 of the correction means 21, the movement means 23 and the commonization means 24
And DH4 are as shown in FIGS. 6 to 8, respectively. In this case, the input 768 bytes (see FIG. 5) becomes 275 bytes (see FIG. 8) by the processing of the correcting unit 21 to the commonizing unit 24, and the compression of 275 / 768≈1 / 2.8 is performed. . 5 to 8 and FIGS. 12 and 13 which will be described later do not include the symbol "H",
It is displayed in hexadecimal.

In the reproducing system, as shown in FIG. 9, the reproduced data of the digital VTR 3 is expanded by the data expansion circuit 4 and then converted into an analog signal by the D / A converter 5 for output. The decompression processing in the data decompression circuit 4 is shown in FIG.
The processing reverse to the processing by each means is performed. However, the reverse process of the correction means 21 is omitted.

FIG. 10 shows an electrocardiographic waveform obtained by the compression-processed electrocardiographic waveform signal of this example, which is almost the same as the electrocardiographic waveform obtained by the non-compressed electrocardiographic waveform signal shown in FIG. The compression process does not adversely affect the reproduction accuracy.

Although the data compensating means 21 is provided in the data compression circuit 2 in the above embodiment, it is not always necessary to provide this. 12 and 13 show A /
The output data DH of the D converter 1 is as shown in FIG. 5, and shows the output data DH3 and DH4 of the moving means 23 and the data commonizing means 24 when the correcting means 21 is not provided. In this case, the input 768 bytes (see FIG. 5) is the detection means 22 to the data commonizing means 24.
Becomes 309 bytes (see Fig. 13) by the process of 3
This means that the compression of 09 / 768≈1 / 2.5 has been performed.

As described above, when the correction means 21 is not provided, the compression rate is lower than when the correction means 21 is provided. This is because the correction means 21 is not provided, so the commonization means 24
It is considered that similar data is reduced in the data DH3 input to the.

The above embodiment is applied to a Holter system for recording an electrocardiographic waveform signal, but the present invention has many other signals, for example, an electrocardiographic waveform signal, which has a small level change. It is suitable for application to data compression processing when recording a signal.

[0036]

According to the present invention, the data correcting means, the data difference detecting means, and the sign bit moving means process the similar data, and then the common data means collects the similar data. Since the data is shared by the data, the amount of data can be significantly reduced. Further, since similar data is output from the data commonizing means as compressed data, the Huffman method and LZW (La
The compression efficiency can be increased when data compression is performed using a compression method that can expand 100%, such as the mple-Ziv-Welch) method.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a functional block diagram showing a configuration of a data compression circuit.

FIG. 3 is a diagram for explaining the operation of the data difference detection means.

FIG. 4 is a diagram showing a correspondence relationship between output data DH2 of the data difference detecting means and output data DH3 of the sign bit moving means.

FIG. 5 is a diagram showing an example of output data DH of an A / D converter.

FIG. 6 is a diagram showing output data DH1 of the data correction means.

FIG. 7 is a diagram showing output data DH3 of the sign bit moving means.

FIG. 8 is a diagram showing output data DH4 of the data commonizing means.

FIG. 9 is a diagram showing a configuration of a reproduction system.

FIG. 10 is a diagram showing an electrocardiographic waveform based on data subjected to compression processing.

FIG. 11 is a diagram showing an electrocardiographic waveform based on data that has not been compressed.

FIG. 12 is a diagram showing output data DH3 of the sign bit moving means (without data correcting means).

FIG. 13 is a diagram showing output data DH4 (without data correcting means) of the data commonizing means.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 2 Data compression circuit 3 Digital VTR 21 Data correction means 22 Data difference detection means 23 Code bit moving means 24 Data commonizing means 25 Lossless compression means

Claims (1)

[Claims] 1. When only the central data of three consecutive input data are different, the data correcting means for making the central data the same as the preceding and following data, and the output data of the data correcting means, respectively. In contrast to this, the data difference detecting means for calculating the expected value using the immediately preceding two data and detecting the difference from the expected value, and the most significant bit of the output data of the data difference detecting means are logic 1 When there is a 2's complement, it is shifted by 1 bit to the upper bit side and a code bit of logic 1 is added to the least significant bit. And a sign bit moving means for adding a sign bit of logic 0 to the least significant bit, and valid bits for the output data of the sign bit moving means. A data compression circuit, comprising: a data commonization unit that classifies the data into a plurality of different bit data and performs a data commonization process.