JPH06237130A - Buffer circuit - Google Patents

Abstract

PURPOSE:To obtain a buffer circuit with high impedance independently of a voltage at the operating point of an input terminal. CONSTITUTION:PNP 3rd and 5th transistors(TRs) 3, 5 for feedback in cascade connection are provided on NPN 1st and 2nd TRs 1, 2 in cascade connection. Furthermore, 4th TR 4 for suppressing the Early effect of the 3rd TR 3 is provided and a 6th TR 6 for suppressing the Early effect of the 5th TR 5 is provided. Through the constitution above, a collector-emitter voltage of the 3rd TR 3 is made the same as a collector-emitter voltage of the 5th TR 5 to make the collector current of the 3rd TR 3 equal to that of the 5th TR 5. Thus, the base current flowing to the 1st TR 1 is also equal to a base current flowing out of the 6th TR 6 and then no current flows to an input terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit, and more particularly to a buffer circuit connected to the next stage such as a peak hold circuit.

[0002]

2. Description of the Related Art Conventionally, as a buffer circuit,
There is Japanese Patent Laid-Open No. 59-83410, and its circuit is shown in FIG.

In FIG. 5, assuming that the current of the current source I0 is I, the current I flows through the emitter of the NPN type first transistor 1 and, as a result, the NPN type first transistor 1
A current I / βn will flow to the base of.

Here, β n is the current gain of the NPN type transistor, and β p is the current gain of the PNP type transistor.

On the other hand, a current I / βn similarly flows through the base of the NPN type second transistor 2.

Therefore, a current (βp / βn) × I flows through the collector of the PNP type third transistor 3.

Here, the PNP-type fourth transistor 4 is cascade-connected to the PNP-type third transistor 3. Therefore, a current (βp / βn) × I flows through the emitter of the PNP-type fourth transistor 4, and therefore the PNP
A current I / βn flows through the base of the fourth transistor 4 of the mold.

From the above, the base current of the NPN type first transistor 1 is equal to the PNP type fourth transistor 4
Of the NPN type first transistor 1 is canceled by the base current of the PNP type fourth transistor 4, and no current flows from the input terminal IN. That is, when the peak hold circuit or the like is connected to the preceding stage, charging and discharging of the capacitor forming the peak hold circuit due to ripple does not occur, and a high impedance buffer circuit can be realized.

[0009]

However, in the above-described conventional circuit, the emitter-collector voltage of the PNP type fourth transistor 4 and the third transistor 3 varies depending on the signal voltage level input to the input terminal IN. To do. Along with this, the collector currents of the PNP type fourth transistor 4 and the third transistor 3 fluctuate (Early effect), so that the collector currents of both do not have the same value.

That is, since the base current flowing into the NPN first transistor 1 and the base current flowing out from the PNP fourth transistor 4 are not the same, charging / discharging of the capacitor forming the peak hold circuit connected to the preceding stage is possible. Therefore, a buffer circuit having a sufficiently high impedance cannot be constructed.

The present invention has been made in view of the above problems, and an object thereof is to obtain a high impedance buffer circuit without depending on the output point voltage.

[0012]

SUMMARY OF THE INVENTION The present invention is a buffer for interconnecting the bases of an NPN-type transistor pair and a PNP-type transistor pair connected in cascade, and compensating for the base current of a transistor whose base is connected to an input terminal. In the circuit, a buffer circuit is characterized in that a transistor for suppressing an Early effect is cascade-connected to a transistor pair forming a feedback circuit among the cascade-connected transistor pairs.

Further, according to the present invention, a first transistor having an emitter connected to an output terminal, a second transistor having an emitter connected to a collector of the first transistor, and an emitter connected to the power supply, A third transistor whose base is connected to the base of the second transistor, and a fourth transistor whose emitter is connected to the collector of the third transistor and whose base is connected to the emitter of the second transistor. A fifth transistor whose emitter is connected to the collector of the fourth transistor and whose base is connected to the base of the first transistor; and whose emitter is connected to the collector of the fifth transistor and whose base is the output terminal Circuit including a sixth transistor connected to the collector and having a collector connected to a reference potential point A.

Further, according to the present invention, a first transistor having an emitter connected to an output terminal, a second transistor having an emitter connected to a collector of the first transistor, and an emitter connected to the reference potential point A third transistor whose base is connected to the base of the second transistor, and a fourth transistor whose emitter is connected to the collector of the third transistor and whose base is connected to the emitter of the second transistor. A fifth transistor having a transistor and an emitter connected to the collector of the fourth transistor and a base connected to the base of the first transistor.
And the emitter is connected to the collector of the fifth transistor and the base is connected to the output terminal,
And a sixth transistor having a collector connected to a power supply.

According to the present invention, a first transistor whose emitter is connected to the base of the eighth transistor in Darlington connection, and a first transistor whose emitter is connected to the collector of the first transistor and whose collector is connected to the power supply side are provided. Second transistor, the emitter is connected to the power supply side, the base is connected to the base of the second transistor, the third transistor, the emitter is connected to the collector of the third transistor, the base is the second A fourth transistor connected to the emitter of the first transistor, and a fifth transistor having an emitter connected to the collector of the fourth transistor and a base connected to the base of the first transistor.
And a sixth transistor whose emitter is connected to the collector of the fifth transistor, whose collector is connected to the reference potential point, and whose emitter is Darlington-connected to the base of the sixth transistor, and whose base is the output terminal. And a seventh transistor whose collector is connected to a reference potential point.

Further, according to the present invention, a first transistor having an emitter connected to an output terminal, a second transistor having an emitter connected to a collector of the first transistor and a collector connected to a power supply side, An emitter is connected to the power supply side, a base is connected to the base of the second transistor, and a third transistor is connected to the collector of the third transistor, and a base is connected to the first transistor.
A fourth transistor connected to the reference potential point of, and an emitter connected to the collector of the fourth transistor,
A fifth transistor having a base connected to the base of the first transistor, an emitter connected to the collector of the fifth transistor, a base connected to an output terminal, and a collector connected to a second reference potential source. And a buffered sixth transistor.

[0017]

According to the present invention, by adopting the above configuration, the collector-emitter voltages of the two transistors connected in cascade become equal, and the collector currents of the two transistors become equal accordingly. As a result, the base current of the transistor connected to the input terminal is compensated by the base current of the feedback transistor.

[0018]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.

An embodiment will be described below in the case where the input terminal is IN0 and the output terminal is OUT0.

In FIG. 1, reference numeral 1 is an NPN type first transistor, the base of which is connected to the input terminal IN0, the emitter of which is connected to the output terminal OUT0 and the reference potential VEE of which is connected via the current source 9. ing. This NP
An NPN type second transistor 2 having the same polarity as the N type first transistor 1 is connected in cascade. That is,
The emitter of the second transistor 2 is connected to the collector of the first transistor 1, and the collector is connected to the power supply Vcc.

On the other hand, between the reference potential point VEE and the power source Vcc, a PNP type third transistor 3, a fourth transistor 4, a fifth transistor 5 and a sixth transistor 6 are provided.
Are cascaded. That is, the emitter of the third transistor 3 is connected to the power supply Vcc, the collector is connected to the emitter of the fourth transistor 4, and the collector of the fourth transistor 4 is connected to the emitter of the fifth transistor 5. The collector of the fifth transistor 5 is connected to the emitter of the sixth transistor 6 and the collector of the sixth transistor 6 is connected to the reference potential point VEE.

The base of the third transistor 3 is the second
It is connected to the base of the transistor 2 and the base of the fourth transistor 4 is connected to the emitter of the second transistor 2. The base of the fifth transistor 5 is connected to the base of the first transistor 1, and the base of the sixth transistor 6 is connected to the emitter of the first transistor 1.

Next, the operation of this buffer circuit will be described.

Since the voltage of the power supply is now VCC, the voltage at point A, which is the base of the third transistor 3, becomes VCC-VBE, and the voltage at point C, which is the emitter of the second transistor 2, becomes VCC-2VBE. The voltage at the point D, which is the collector of the fourth transistor 4, becomes VCC-VBE. Therefore,
The voltage between the collector and the emitter of the third transistor 3 is V
BE.

On the other hand, if the voltage at point E is e, the voltage at point F is e-VBE, the voltage at point G is e-2VBE, and the voltage at point H is e-VBE. Therefore, the voltage between the collector and the emitter of the fifth transistor 5 is VBE.
Becomes

That is, the fourth transistor 4 and the sixth transistor 6 operate as transistors for suppressing the Early effect.

Therefore, since the collector-emitter voltages of the third transistor 3 and the fifth transistor 5 have the same value, their base currents also have the same value, and the base current from the input terminal to the base of the first transistor 1 is the same. There is no inflow.

From the above, when the peak hold circuit circuit is connected in the preceding stage, the ripple due to the leak current of the capacitor and the buffer circuit forming the peak hold circuit can be suppressed, and the high impedance buffer circuit. To work as.

In the present embodiment, the description has been given of the case where the input terminal IN0 and the output terminal OUT0 are used, but the input terminal may be IN1 and the output terminal may be OUT1.
But it is possible.

Next, FIG. 2 shows a second embodiment of the buffer circuit of the present invention.

Since the operation of the circuit is similar to that of the first embodiment, its explanation is omitted.

The second embodiment differs from the first embodiment in that the polarity of the cascade-connected transistors is opposite to that of the first embodiment.

In FIG. 2, reference numeral 1 is a PNP type first transistor, the base of which is connected to the input terminal IN0, the collector of which is connected to the output terminal OUT0 and the power source Vcc through the current source 9. . The NPN type second transistor 2 having the same polarity as the NPN type first transistor 1 is cascade-connected. That is, the emitter of the second transistor 2 is connected to the collector of the first transistor 1, and the collector is connected to the reference potential point VEE.

On the other hand, between the reference potential point VEE and the power source Vcc, the third transistor 3, the fourth transistor 4, the fifth transistor 5, and the sixth transistor 6 of the NPN type are provided.
Are cascaded. That is, the emitter of the third transistor 3 is connected to the reference potential point VEE, the collector is connected to the emitter of the fourth transistor 4, and the collector of the fourth transistor 4 is connected to the emitter of the fifth transistor 5. The collector of the fifth transistor 5 is connected to the emitter of the sixth transistor 6 and the collector of the sixth transistor 6 is connected to the power supply Vcc.

The base of the third transistor 3 is the second
It is connected to the base of the transistor 2 and the base of the fourth transistor 4 is connected to the emitter of the second transistor 2. The base of the fifth transistor 5 is connected to the base of the first transistor 1, and the base of the sixth transistor 6 is connected to the emitter of the transistor 1.

In this embodiment, the description has been given on the case where the input terminal IN0 and the output terminal OUT0 are used.
Similar to the embodiment described above, the input terminal may be IN1 and the output terminal may be OUT1.

Next, FIG. 3 shows a third embodiment of the present invention.

Since the operation of the circuit is similar to that of the first embodiment, its explanation is omitted.

The third embodiment is different from the first embodiment in that the eighth transistor 8 is connected to the first transistor 1 in a Darlington connection, and the sixth transistor 6 for suppressing the Early effect is provided with a second transistor. The point is that the 7-transistor 7 is connected in Darlington connection.

In FIG. 3, reference numeral 1 is an NPN-type first transistor, the base of which is connected to the input terminal IN0 and the emitter of which is connected to the base of the Darlington-connected eighth transistor 8. The collector of the eighth transistor 8 is connected to the power supply VCC, and the emitter is the output terminal OU.
It is connected to T0 and is also connected to the reference potential point VEE via the current source 9. The NPN type second transistor 2 having the same polarity as the NPN type first transistor 1 is cascade-connected. That is, the emitter of the second transistor 2 is connected to the collector of the first transistor 1, and the collector is connected to the power supply Vcc.

On the other hand, a PNP type third transistor 3, a fourth transistor 4, a fifth transistor 5, and a sixth transistor 6 are provided between the reference potential point VEE and the power source Vcc.
Are cascaded. That is, the emitter of the third transistor 3 is connected to the power supply Vcc, the collector is connected to the emitter of the fourth transistor 4, and the collector of the fourth transistor 4 is connected to the emitter of the fifth transistor 5. The collector of the fifth transistor 5 is connected to the emitter of the sixth transistor 6 and the collector of the sixth transistor 6 is connected to the reference potential point VEE.

The base of the third transistor 3 is the second
It is connected to the base of the transistor 2 and the base of the fourth transistor 4 is connected to the emitter of the second transistor 2. The base of the fifth transistor 5 is connected to the base of the first transistor 1, and the base of the sixth transistor 6 is connected to the emitter of the Darlington-connected seventh transistor 7. The base of the seventh transistor 7 is connected to the emitter of the eighth transistor 8.

Therefore, the input impedance of the first transistor 1 becomes high, and a sufficient output can be obtained at the emitter of the eighth transistor 8 by passing a small amount of current. Therefore, it is possible to reduce the capacity of the capacitor forming the peak hold circuit connected to the preceding stage, and it is possible to incorporate the peak hold capacitor, which has been conventionally attached externally, in the IC.

In the present embodiment, the description has been given in the case where the input terminal IN0 and the output terminal OUT0 are used.
Similar to the embodiment described above, the input terminal may be IN1 and the output terminal may be OUT1.

Next, FIG. 4 shows a fourth embodiment of the present invention.

Since the operation of the circuit is similar to that of the first embodiment, its explanation is omitted.

The fourth embodiment differs from the first embodiment in that the base of the fourth transistor 4 for the Early effect voltage of the third transistor 3 is not connected to the emitter of the second transistor 2 but is different. Is a point connected to the reference potential point DC1.

In FIG. 4, reference numeral 1 is a first NPN transistor, the base of which is connected to the input terminal IN0, the emitter of which is connected to the output terminal OUT0 and the reference potential point VEE through the current source 9. ing. This NP
An NPN type second transistor 2 having the same polarity as the N type first transistor 1 is connected in cascade. That is,
The emitter of the second transistor 2 is connected to the collector of the first transistor 1, and the collector is connected to the power supply Vcc.

On the other hand, between the reference potential point VEE and the power source Vcc, the PNP type third transistor 3, the fourth transistor 4, the fifth transistor 5, and the sixth transistor 6 are provided.
Are cascaded. That is, the emitter of the third transistor 3 is connected to the power supply Vcc, the collector is connected to the emitter of the fourth transistor 4, and the collector of the fourth transistor 4 is connected to the emitter of the fifth transistor 5. The collector of the fifth transistor 5 is connected to the emitter of the sixth transistor 6 and the collector of the sixth transistor 6 is connected to the reference potential point VEE.

The base of the third transistor 3 is the second
It is connected to the base of the transistor 2 and the base of the fourth transistor 4 is connected to the reference potential point DC1. The base of the fifth transistor 5 is the first transistor 1
The base of the sixth transistor 6 is connected to the emitter of the first transistor 1.

Therefore, since the base current of the fourth transistor 4 does not flow into the emitter of the first transistor 1, the influence of the base current of the fourth transistor 4 can be removed, and a more accurate buffer circuit can be obtained. be able to.

In this embodiment, the description has been given on the case where the input terminal IN0 and the output terminal OUT0 are used.
Similar to the embodiment described above, the input terminal may be IN1 and the output terminal may be OUT1.

[0054]

According to the present invention, since the base width modulation due to the Early effect can be suppressed by configuring as described above,
A high impedance buffer circuit with a low input current can be obtained without being affected by the operating point voltage from the input terminal.

[Brief description of drawings]

FIG. 1 is a first embodiment of a buffer circuit of the present invention.

FIG. 2 is a second embodiment of the buffer circuit of the present invention.

FIG. 3 is a third embodiment of the buffer circuit of the present invention.

FIG. 4 is a fourth embodiment of the buffer circuit of the present invention.

FIG. 5 is a diagram showing a conventional buffer circuit.

[Explanation of symbols]

 1 1st transistor 2 2nd transistor 3 3rd transistor 4 4th transistor 5 5th transistor 6 6th transistor 7 7th transistor 8 8th transistor

Claims (5)

[Claims] 1. A buffer circuit in which the bases of an NPN-type transistor pair and a PNP-type transistor pair are connected to each other and the bases of the transistors are connected to an input terminal to compensate the base current of the transistor. A buffer circuit characterized in that a transistor for suppressing an Early effect is cascade-connected to a transistor pair forming a feedback circuit of the transistor pair. 2. A first transistor having an emitter connected to the output terminal, a second transistor having an emitter connected to the collector of the first transistor, an emitter connected to the power supply, and a base connected to the first power supply. A third transistor connected to the base of the second transistor; a fourth transistor having an emitter connected to the collector of the third transistor and a base connected to the emitter of the second transistor; A fifth transistor connected to the collector of the fourth transistor, the base of which is connected to the base of the first transistor; the emitter of which is connected to the collector of the fifth transistor, and the base of which is connected to the output terminal, And a sixth transistor having a collector connected to the reference potential point. 3. A first transistor having an emitter connected to the output terminal, a second transistor having an emitter connected to the collector of the first transistor, an emitter connected to the reference potential point, and a base connected to the reference potential point. A third transistor connected to the base of the second transistor;
A fourth transistor having an emitter connected to the collector of the third transistor and a base connected to the emitter of the second transistor, and an emitter connected to the collector of the fourth transistor and a base of the first transistor. A fifth transistor connected to the base of the transistor, and a sixth transistor whose emitter is connected to the collector of the fifth transistor, whose base is connected to the output terminal, and whose collector is connected to the power supply. circuit. 4. A first transistor having an emitter connected to the base of the eighth transistor in Darlington connection, and an emitter connected to the collector of the first transistor,
A second transistor whose collector is connected to the power supply side,
A third transistor having an emitter connected to the power supply side and a base connected to the base of the second transistor;
A fourth transistor having an emitter connected to the collector of the third transistor and a base connected to the emitter of the second transistor, and an emitter connected to the collector of the fourth transistor and a base of the first transistor. A fifth transistor connected to the base of the transistor, an emitter connected to the collector of the fifth transistor, a collector connected to the reference potential point, and an emitter connected to the sixth transistor. A buffer circuit including a seventh transistor connected to the base in Darlington connection, the base connected to the output terminal, and the collector connected to the reference potential point. 5. A first transistor having an emitter connected to an output terminal, a second transistor having an emitter connected to a collector of the first transistor and having a collector connected to a power supply side, and an emitter having a power supply side. A third transistor having a base connected to the base of the second transistor, an emitter connected to a collector of the third transistor, and a base connected to a first reference potential point. The transistor and the emitter are the fourth
A fifth transistor connected to the collector of the transistor, the base of which is connected to the base of the first transistor, the emitter of which is connected to the collector of the fifth transistor, the base of which is connected to the output terminal, and the collector of which is And a sixth transistor connected to the second reference potential source.