JPH06236925A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit in which high integration and speedup are materialized and also operation becomes possible by lessening the capacitance used for the impedance drop of reference voltage. CONSTITUTION:In a semiconductor integrated circuit device, which are equipped with a plurality of macrocells, and gives a reference voltage line main reference voltage by means of a main reference voltage generating circuit 11, and supplies the macrocelles with following reference voltage by means of sub-reference voltage generating circuit 12-1-12-4 for generating sub-reference voltage, based on the main reference voltage, being connected to the reference voltage line LM, at least two or more sub-reference voltage generating circuit are put in such condition that the current supply is possible, among the sub-reference voltage generating circuit 12-1-12-4 being connected Lc with each other capably of current supply.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a large scale semiconductor integrated circuit device such as a gate array type having a plurality of macro cells arranged therein and a reference voltage circuit for supplying a reference voltage to each macro cell. .

With the recent demand for higher integration and higher speed of semiconductor integrated circuit devices, higher integration of gate array type semiconductor integrated circuit devices having a plurality of macrocells has been achieved.
Higher speed is required.

[0003]

2. Description of the Related Art ECL (Emitter Coup) as a logic circuit
A led logic) / CML (Current Mode Logic) type integrated circuit requires a reference voltage for operating as a current switching circuit.

The impedance of the reference voltage needs to be lowered for the following reasons. a) To suppress a transient voltage change due to current switching of the circuit.

B) To prevent oscillation of the reference voltage generating circuit itself. c) To prevent the influence of noise on the logic circuit. As a method for lowering this impedance, it is effective to insert a capacitance between the ground potential or fixed potential and the reference voltage line. As a method for realizing the insertion of the electrostatic capacitance, there is a method in which a P-type diffusion region and an N-type diffusion region are brought into contact with each other to form a PN junction, and the PN junction is used with a reverse bias.

A more specific conventional example will be described with reference to FIG. FIG. 10 shows a schematic configuration of a main part of a conventional gate array type LSI. The gate array type LSI 50 is provided in each macrocell with a main reference voltage generation circuit 51 that supplies a reference voltage to the entire LSI 50, and is connected to the main reference voltage generation circuit 51 via a main reference voltage line L _M. ,
The gate circuit G _51, G ₅₂ constituting the macro cell, ... etc. with a plurality of sub-reference voltage for supplying a sub reference voltage through a sub reference voltage line L _S generator 52 _-1 to 52 _-4, and includes a It is configured.

For example, when the sub reference voltage generating circuits 52 _-1 , 52 _-2 , 52 _-3 in the macro cell array are used, when the main reference voltage of the main reference voltage generating circuit 51 fluctuates, it is supplied to each macro cell. The secondary reference voltage to be used also changes.

Therefore, each sub-reference voltage generating circuit 52 _-1 , 5
A capacitance (not shown) is provided in 2 _-2 and 52 _-3 to absorb the voltage fluctuation of the main reference voltage generation circuit 51, thereby stabilizing the sub reference voltage.

[0009]

By the way, in order to reduce the above-mentioned capacitance, it is necessary to reduce the circuit current, but in the ECL / CML type integrated circuit which requires high-speed operation, the circuit current is not so much. In some cases it cannot be made smaller.

On the other hand, in recent years, the miniaturization of circuit elements has advanced and the size of the macro cell has become smaller. Therefore, the area occupied by the capacitance is relatively increased with respect to the area occupied by the macro cell. As a result, there is a problem that it becomes a major obstacle in achieving high integration.

Further, since the area occupied by the electrostatic capacitance cannot be reduced, the wiring length cannot be shortened.
There was a problem that it impeded speeding up. Therefore, an object of the present invention is to provide a semiconductor integrated circuit that can reduce the capacitance used for lowering the impedance of a reference voltage to achieve high integration and high speed and stable operation. .

[0012]

In order to solve the above problems, the present invention is provided with a plurality of macro cells, and a main reference voltage is applied to a reference voltage line by a main reference voltage generation circuit and connected to the reference voltage line. In the semiconductor integrated circuit device that supplies the sub-reference voltage to the macro cell by the sub-reference voltage generation circuit that generates the sub-reference voltage based on the main reference voltage, the sub-reference voltages commonly connected to each other so that currents can be supplied. Among the generation circuits, at least two sub-reference voltage generation circuits are in a state capable of supplying current.

[0013]

According to the present invention, since a plurality of sub-reference voltage generation circuits are commonly connected via the reference voltage line, any of the sub-reference voltage generation circuits commonly connected is changed by the fluctuation of the main reference voltage. Even if the secondary reference voltage is about to fluctuate due to noise or the like, the current is supplied from another secondary reference voltage generation circuit, so that the variation of the secondary reference voltage can be suppressed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described with reference to the drawings. First Embodiment FIG. 1 is a block diagram showing a schematic configuration of the first embodiment.

FIG. 1 shows an output of a sub reference voltage generating circuit adjacently arranged in a gate array type LSI having a plurality of sub reference voltage generating circuits for supplying a reference voltage (sub reference voltage) to corresponding gates. This is an example in the case where a sub-reference voltage line is connected.

The gate array type LSI 10 has a temperature compensation and
And power supply compensation etc. are performed, and the reference voltage of the entire LSI concerned is
The generated main reference voltage generation circuit 11 and the main reference voltage line L_M
Is connected to the main reference voltage generation circuit 11 via
Gate G₁, G₂, ..., the reference voltage is supplied via the reference voltage line.
A plurality of sub reference voltage generating circuits 12_-11
Two _-2, ..., and are configured.

Further, the sub reference voltage line L _S of the adjacent sub reference voltage generating circuit is connected via the connection line L _C. A specific circuit example of the reference voltage generation circuit according to FIG. 2 is shown. Figure 2
Since the sub-reference voltage generating circuit 12 _-1 and the sub-reference voltage generating circuit 12 _-2 have the same configuration, the sub-reference voltage generating circuit 12 _-1 will be mainly described in the following description.

The sub-reference voltage generating circuit 12 _-1 has a first transistor Q whose collector terminal is connected to the ground line GND.
₁ , a first resistor R ₁ connected between the base terminal of the first transistor Q ₁ and the ground line GND, and a collector terminal connected to the emitter terminal of the first transistor Q ₁ ,
The second transistor Q ₂ whose base terminal is connected to the main reference voltage line, the second resistor R ₂ connected between the emitter terminal of the second transistor Q ₂ and the power supply line VE, and the first transistor Q ₁ collector terminal is connected to the intermediate connection point of the base terminal and the first resistor R _1, the third transistor Q ₃ which base terminal is connected to the main reference voltage line, and the collector terminal to the emitter terminal of the third transistor Q ₃ based a fourth transistor Q ₄ which terminals are commonly connected, is configured to include a third resistor R ₃ connected between the emitter terminal and the power supply line VE of the fourth transistor Q _4, a.

The common connection point between the emitter terminal of the first transistor Q ₁ and the collector terminal Q ₂ of the second transistor Q ₂ is connected to the corresponding gate G ₁ via the _secondary reference voltage line L _S.

Further, two sub reference voltage generating circuits 12 are provided._-1,
12_-2Secondary reference voltage line L_SIs a connection line L that is a fixed wiring_C
Are connected in common via each of the sub reference voltage generating circuits 12_-1,
12 _-2Connection line L_CBetween the ground line GND and
The capacitor C that functions as a buffer that absorbs voltage fluctuations is connected
Has been continued.

Next, a more specific connection state of the reference voltage line
This will be described with reference to FIGS. 3 to 5. Figure 3
As shown in (a), the macro cell MC₁The games that make up
G₁₁, G₁₂, G ₁₃If you use
MC₁Sub-reference voltage generation circuit 13 corresponding to _-1Used condition
And

Further, as shown in FIG. 3B, even when the gates G _{21 to} G ₂₄ forming the macro cell MC ₂ adjacent to the macro cell MC ₁ are not used, the sub reference voltage generating circuit 13 _{-1 is used.} The secondary reference voltage generation circuit 13 _-2 connected to the connection line L _C1 is set to the use state.

In this case, even if the sub-reference voltage supplied from the sub-reference voltage generation circuit 13 _-1 of the gates G ₁₁ , G ₁₂ , and G ₁₃ is likely to change due to various use conditions, the sub-reference voltage generation circuit is generated. A current is actively supplied from 13 _-2, and it becomes possible to minimize the voltage fluctuation of the secondary reference voltage.

In the above description, the fixed wiring provided in advance was used as the connection line L _C , but as shown in FIG. 4, an unused channel region is used and the connection line L is used instead of the signal line.
_{Even if C1} is formed, the same processing can be performed.

According to the first embodiment As described above, sub-reference voltage noise or the like is supplied from the sub reference voltage generating circuit 13 _-1 macrocells MC ₁ generated varies in the macro cell MC ₁ However, a current is actively supplied from the sub reference voltage generation circuit 13 _{-2 of} the macro cell MC ₂ so that the variation of the sub reference voltage is suppressed and a correct operation can be performed.

In particular, as shown in FIG. 5, when there are simultaneously switching gates (gate G ₃₁ and gate G ₃₂ , or gate G ₄₁ and gate G ₄₂ ) in the same macro cell, the sub reference voltage is applied. The voltage fluctuations can be compensated for by the macrocells, and the effect becomes more remarkable.

Even when the number of used gates is light as the load of the sub-reference voltage generating circuit, the sub-reference voltage of the sub-reference generating circuit can be connected in common to suppress the fluctuation. Modification of First Embodiment Another specific example of the reference voltage generating circuit is shown in FIG. 6, the same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The specific example of FIG. 6 is different from the specific example of FIG. 2 in that one of two adjacent sub reference voltage generating circuits 15 _-1 , 15 _-2 to which the sub reference voltage line L _C1 is commonly connected, That is,
This is that only the sub-reference voltage generation circuit 15 _-2 is provided with the electrostatic capacitance C ′ for absorbing the voltage fluctuation of the sub-reference voltage.

As a result, the area required for forming the electrostatic capacitance is reduced as compared with the case of the above-mentioned first embodiment, and the integration rate can be improved. Another modification of the first embodiment FIG. 7 shows still another specific example of the reference voltage generating circuit.
7, the same parts as those in FIG. 2 are designated by the same reference numerals,
Detailed description thereof will be omitted.

The specific example of FIG. 7 is different from the specific example of FIG. 2 in that the connection lines of two adjacent sub reference voltage generation circuits 16 _-1 and 16 _-2 to which the sub reference voltage line L _S is commonly connected. A capacitance for absorbing the voltage fluctuation of the sub reference voltage is provided between L _C and the ground line GND, and each sub reference voltage generation circuit 16 _-1 , 16 _-2 is provided.
That is, the capacitance for absorbing the voltage fluctuation of the secondary reference voltage is not provided inside.

As a result, as in the other specific examples described above, as compared with the case of the first embodiment described above, the area required for forming the capacitance is reduced, and the integration rate can be improved. Becomes Second Embodiment FIG. 8 is a block diagram showing the schematic configuration of the second embodiment.
8, the same parts as those in the embodiment of FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0032] Figure 8 is a plurality of sub-reference voltage generating circuit 12 _-1 to disposed near the gate array LSI 10 '
This is an embodiment in the case where a sub reference voltage line which is an output of 12 _-4 is connected.

As a result, a plurality of sub reference voltage generating circuits 12
_{-1 to} 12 _-4 in common (see FIG. 2 or FIG. 6) or shared by using the capacitance (see FIG. 7) provided outside the slave reference voltage generating circuit. Since the voltage fluctuation of the reference voltage is absorbed, the magnitude of the electrostatic capacitance can be increased as compared with the case of the first embodiment, and the voltage fluctuation can be further suppressed.

In this case, theoretically, more voltage fluctuations can be absorbed by increasing the number of secondary reference voltage generating circuits to be connected, as in the case of further connecting the connection points P ₁ and P _2. However, in that case, in order to prevent the current from flowing into a specific sub reference voltage generating circuit, it is necessary to keep the sub reference voltage output from each sub reference voltage generating circuit substantially constant.

Further, in the case where the capacitance of the entire sub reference voltage generating circuit is made equal to that in the case of providing each sub reference voltage generating circuit, the area required for forming the capacitance in each sub reference voltage generating circuit is reduced. Therefore, the integration rate can be improved. Further, as a result, the wiring length between the macro cells can be shortened and the wiring capacitance can be reduced, so that high-speed operation can be achieved. Modification of Second Embodiment In the above description of the second embodiment, the fixed wiring provided in advance is used as the connection line L _C. However, as shown in FIG. 9, an unused channel region is used, Connection line L instead of signal line
_{Even if C2} is formed, the same treatment can be performed. In this case, as shown in FIG. 9, the sub-reference voltage generation circuit 17 of the macro cells MC ₂₁ , MC ₂₃ and MC ₂₄ using the gates is used.
_-1 , 17 _-3 , 17 _-4 may be connected, or a sub reference voltage generating circuit in a neighboring macro cell may be connected regardless of whether the gate belonging to the macro cell is used or not, for example, The sub reference voltage generating circuits 17 _{-1 to} 17 _-4 may be connected.

As described above, according to each embodiment,
The capacitance forming area for stabilizing the reference voltage can be reduced, and the integration rate can be increased.
Further, by forming an electrostatic capacity only in a specific sub-reference voltage generating circuit, or by forming an electrostatic capacity by wiring, it is possible to reduce the area for forming the electrostatic capacity in the gate array type LSI, It is possible to achieve integration, and it is possible to shorten the wiring length that connects macro cells,
Wiring capacitance is reduced, and high speed operation becomes possible.

In each of the above embodiments, the case where the main reference voltage generating circuit and the plurality of sub reference voltage generating circuits are provided in the gate array type LSI has been described, but a plurality of main reference voltage generating circuits are provided. The present invention can be applied to the case where the reference voltage is directly supplied from each main reference voltage generating circuit to each macro cell.

In this case, each main reference voltage generating circuit may be connected in the same manner as the above-mentioned sub reference voltage generating circuit.

[0039]

According to the present invention, a plurality of sub-reference voltage generating circuits are commonly connected to each other via the reference voltage line so that current can be supplied to each other, thereby lowering the impedance of the reference voltage line and operating stably. Can be made.

Further, since it is not necessary to reduce the installation area of the capacitance for stabilizing the reference voltage in each macro cell or to provide the capacitance in the macro cell, it is possible to reduce the size of the macro cell, so that it is possible to reduce the size between the macro cells. The wiring length is shortened, the wiring capacitance is reduced, and higher speed can be achieved.

Furthermore, the chip size of the LSI or the like can be reduced, the yield can be improved, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part of a gate array type LSI according to a first embodiment.

FIG. 2 is a diagram illustrating a specific example of a sub reference voltage generation circuit.

FIG. 3 is an explanatory diagram (1) of a connection state of a sub reference voltage line.

FIG. 4 is an explanatory diagram (2) of a connection state of the sub reference voltage line.

FIG. 5 is an explanatory diagram (3) of the connection state of the sub-reference voltage line.

FIG. 6 is a diagram illustrating a modified example of the first embodiment.

FIG. 7 is a diagram illustrating another modification of the first embodiment.

FIG. 8 is a configuration diagram of a main part of a gate array type LSI according to a second embodiment.

FIG. 9 is a diagram illustrating a modified example of the second embodiment.

FIG. 10 is a configuration diagram of a main part of a conventional gate array type LSI.

[Explanation of symbols]

10 ... Gate array type LSI 11 ... Main reference voltage generation circuit 12 _{-1 to} 12 _-4 ... Sub reference voltage generation circuit 13 _-1 , 13 _-2 ... Sub reference voltage generation circuit 14 _-1 , 14 _-2 ... Sub reference voltage Generation circuit 15 _-1 , 15 _-2 ... Sub reference voltage generation circuit 16 _-1 , 16 _-2 ... Sub reference voltage generation circuit 17 _{-1 to} 17 _-4 ... Sub reference voltage generation circuit C, C ', C "... Static capacitance GND ... ground line L _M ... main reference voltage line L _S ... sub reference voltage line MC ₁ to MC ₄ ... macro cell MC ₂₁ to MC ₂₄ ... macrocell VE ₁ ... power line

Claims (4)

[Claims] 1. A plurality of macro cells are provided, and a main reference voltage is applied to a reference voltage line by a main reference voltage generation circuit, and the main reference voltage is connected to the reference voltage line to generate a sub-reference voltage based on the main reference voltage. In a semiconductor integrated circuit device that supplies a reference voltage to the macro cell by a sub-reference voltage generation circuit, at least two or more sub-reference voltage generation circuits among the sub-reference voltage generation circuits commonly connected to each other so that currents can be supplied. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is in a state capable of supplying current. 2. The semiconductor integrated circuit device according to claim 1, wherein a transient current supply is provided in at least one sub-reference voltage generation circuit among the plurality of sub-reference voltage generation circuits connected to the reference voltage line. A semiconductor integrated circuit device characterized by forming a capacitance as a current supply source. 3. The semiconductor integrated circuit device according to claim 1, wherein an electrostatic capacitance is formed between the commonly connected reference voltage line and a power supply line as a current supply source for transient current supply. A semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 2 or 3, wherein a wiring capacitance is used as the electrostatic capacitance.