KR100284455B1 - Semiconductor integrated circuit - Google Patents

Abstract

The semiconductor integrated circuit makes it possible to stabilize the substrate potential and to suppress the occurrence of abnormal current when the power is turned on. The well is divided into four P wells, each of which is provided with a back bias generation circuit BBG.

Description

Semiconductor integrated circuit

The present invention relates to a semiconductor integrated circuit. More specifically, the present invention relates to a semiconductor integrated circuit provided with a back bias generation circuit for a dynamic random access memory (DRAM) or the like.

In semiconductor integrated circuits, in general, a back bias generation circuit (hereinafter referred to as BBG) has been widely used. In particular, in DRAM, the BBG protects the memory cell from undershoot of the input potential, and the BBG also plays an important role in reducing the capacity of the PN junction of the substrate. The BBG receives a power supply voltage supplied to a chip, generates a substrate potential different from the power supply voltage, and the BBG applies a substrate potential to a semiconductor substrate (hereinafter referred to as a substrate).

In the conventional case, only one BBG is provided inside the chip. Even if the first conventional semiconductor integrated circuit has only one BBG, if the BBG's ability to draw substrate current is sufficient, the BBG is continuously generated from the entire RAM in a carrier, i. The substrate current injected into the substrate is sucked up to suppress the potential variation of the substrate caused by the substrate current.

1 is a circuit diagram illustrating an example of a general BBG. An example of a general BBG will be described with reference to FIG. 1. As shown in Fig. 1, the BBG is composed of N-channel MOS transistors formed on a P-type substrate. A drain and a gate are connected to the BBG in common, a transistor Q1 outputting a substrate potential VS at the drain, a drain and a gate are connected in common, a source is connected to a ground potential, and a capacitor C1. Is provided with a transistor Q2 configured to receive the alternating substrate potential drive signal S through < RTI ID = 0.0 >

The operation of the general BBG is described below. The circuit is a known doubler rectifier circuit comprising a substrate capacitance C2 as an output load. The current supply capability of the output substrate potential VS is almost proportional to the frequency of the substrate potential drive signal S. do.

Recently, however, large-capacity DRAMs and high-speed DRAMs have been developed. As a result, the transistor in the DRAM needs to be driven at high speed with a large capacity. The current driving capability of each transistor is increased. As a result, a large amount of current flows through the entire chip of the semiconductor integrated circuit, and the substrate current injected into the carrier, i.e., the entire chip, also increases. Moreover, the substrate resistance increases because the chip area increases. Therefore, in the area away from the BBG circuit, the time constant constituted by the resistance component and the capacity of the substrate until the carrier injected into the substrate during the circuit operation in the area is pulled up through the resistance component of the substrate to the BBG circuit. There is a time delay due to this.

The time delay causes a transient or local variation resulting from a set point according to the BBG of the substrate potential or well potential of the remote region. Since the enhancement mode transistor is changed to a depletion layer by the back gate bias effect, the circuit cannot operate normally. This causes the circuit in the area to malfunction. This causes the destruction of data in the memory cell in the vicinity of the BBG due to the occurrence of hot electrons during the operation of the BBG.

As a countermeasure against this problem, the second conventional semiconductor integrated circuit described in Japanese Patent Laid-Open No. 3-21052 or Japanese Patent Laid-Open No. 1-298059 prevents the above-described problem by arranging a plurality of BBGs.

When a plurality of the BBGs are arranged, since the distance between the BBG and the place where the variation in the well potential occurs is short, the variation in the substrate potential is unlikely to occur. In addition, the BBG capacity of each separate BBG is lowered. The occurrence of hot electrons occurring in each BBG can be prevented. Therefore, data destruction in the memory cell can be suppressed.

However, in the above-described second conventional semiconductor integrated circuit, the substrate potential in the chip is common. In conjunction with the increase in the speed of circuit operation, even if the BBG increases in plural numbers, local and transient variations in the substrate potential are likely to occur in a portion where the circuit operation is active, that is, a large drive current. This is because a large amount of memory is used, an increased memory area is used, and the high speed circuit operation of the memory is used.

Furthermore, according to the above conditions, since the plurality of BBGs start to operate in response to the fluctuations, power consumption can be increased and data destruction of the memory cells due to the generation of hot electrons in each BBG can occur. have.

In addition, when a chip having a large area is used, the capacitance C and the resistance R of the substrate are increased, thereby increasing the time constant. As a result, it takes a lot of time to set the substrate potential by the time constant of the substrate when the power is turned on. If the chip enters the operating state before the substrate potential is determined, abnormal potential flows to the substrate. As a result, there is a possibility that the substrate potential rises and latchup occurs.

Only one BBG is provided in the above-described conventional first semiconductor integrated circuit. The first circuit generates a transient variation or a local variation resulting from a set point according to the BBG of the substrate potential or well potential of the separated region. Therefore, normal operation of the circuit becomes impossible, and a malfunction of the circuit occurs in the region, and the operation of the BBG causes the destruction of data in the memory cell in the vicinity of the BBG due to the generation of hot electrons.

The conventional second semiconductor integrated circuit solves the problem by providing a plurality of BBGs. However, since the substrate potential is common in the chip, even with the increase in the circuit operation, even if the BBG increases in plural numbers, the local and transient variations of the substrate potential in a portion where the circuit operation is active, i. Easy to get up This is because a large amount of memory is used, an increased memory area is used, and the high speed circuit operation of the memory is used. Eventually, the problem of transient and local fluctuations is not solved. Furthermore, according to the above conditions, since a plurality of BBGs start to operate in response to the fluctuations, power consumption can be increased, and data destruction of memory cells due to the occurrence of hot electrons in each BBG occurs. There is this.

In addition, when a chip having a large area is used, there is a problem in that the capacitance C and the resistance R of the substrate are increased, thereby increasing the time constant. As a result, it takes a lot of time to set the substrate potential by the time constant of the substrate when the power is turned on. If the chip enters the operating state before the substrate potential is determined, abnormal potential flows to the substrate. As a result, the substrate potential rises, whereby a latchup may occur.

1 is a circuit diagram illustrating an example of a general back bias generation circuit BBG.

2 is a layout diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention;

3 is a layout diagram showing a second embodiment of a semiconductor integrated circuit according to the present invention;

4 is a layout diagram showing a third embodiment of a semiconductor integrated circuit according to the present invention;

5 is a cross-sectional view showing a typical configuration of a well of a semiconductor integrated circuit according to the above embodiment.

As described above, an object of the present invention is to provide a semiconductor integrated circuit which can stabilize the substrate potential and at the same time suppress the generation of abnormal current when the power is turned on.

According to one embodiment of the present invention, in order to achieve the above object, the semiconductor integrated circuit receives a back bias generation circuit for generating a substrate potential different from the first power supply voltage supplied to the chip, and the supply of the substrate potential A well held at the substrate potential and formed in a predetermined circuit block, wherein the back bias generation circuit and the well are formed on a chip, and the well is divided into a plurality of subwells or a plurality of subwell groups, respectively, The plurality of subwells or a plurality of subwell groups of are provided with the back bias generation circuit.

The above and other objects and novel features of the present invention will become apparent from the following description with reference to the accompanying drawings. However, the following description is for the purpose of understanding only and various modifications and variations are possible within the spirit and scope of the invention. With reference to the accompanying drawings, a preferred embodiment according to the present invention will be described in detail. 2 is a layout diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention. Referring to Fig. 2, the semiconductor integrated circuit of this embodiment includes a P-type P well 11-14 in which a well for maintaining a substrate potential of a circuit element on a semiconductor substrate is divided into four parts, and the respective P wells 11- And a back bias generation circuit (BBG) 21-24 for selectively controlling 14).

The BBGs 21-24 are the same as the BBGs of FIG. 1. That is, as shown in FIG. 1, the back bias generation circuit BBG includes an N-channel MOS transistor formed on a P-type substrate. A drain and a gate are commonly connected to the back bias generation circuit BBB, a transistor Q1 for outputting a substrate potential VS at the drain, a drain and a gate are commonly connected, and a source is connected to a ground potential. A transistor Q2 is provided, which is connected to the gate and receives the substrate potential driving signal S of alternating current through the capacitor C1.

Next, the operation of this embodiment will be described with reference to FIG. The circuit in the P wells 11-14 includes a portion in which a large current flows and operates at a high speed, so the variation of the substrate carrier is large. First, the P well 11 is a portion in which a large current flows and operates at a high speed. In the other P wells 12-14, a portion in which a large current flows and operates at a high speed does not operate. In this case, the frequency of the substrate potential drive signal S1 of the BBG21 which supplies the substrate potential of the P well 11 is increased, the current supply capability of the substrate potential VS1 is increased, and the inside of the P well 11 is increased. This suppresses variations in substrate potential (well potential). In the P well 12-14, since there is no change in the well potential according to the operation of the internal current, the respective BBGs 22-24 drop the frequency of the substrate potential driving signals S2-S4, respectively. The current consumption of the BBG 22-24 is suppressed by the fact of lowering the well potentials VS2-VS4. Further, when there is no circuit operation in the P well 12-14 and no abnormality occurs in the well potential, the substrate potential driving signals S2-S4 of the respective BBGs 22-24 are stopped. You may stop the operation.

Also, in this embodiment, since the well is divided into a plurality of small wells, the capacitance C and the resistance R of the circuit area shared by one BBG can be reduced. As a result, the time constant is reduced, so that the setting of the well potential at the time of power supply can be performed quickly. This makes it possible to prevent abnormal current when the power is turned on.

3 is a layout showing a second embodiment of a semiconductor integrated circuit according to the present invention. In FIG. 3, the same reference numerals are used for the same components as in FIG. 2. The semiconductor integrated circuit of this embodiment includes a P-type P well 11-14 in which the wells for maintaining the substrate potential of the circuit elements on the semiconductor substrate are divided into four parts.

BBG 21A, 23A is the same as BBG of FIG. That is, as shown in Fig. 1, it is a back bias generation circuit BBB composed of N-channel MOS transistors formed on a P-type substrate. A drain and a gate are commonly connected to the back bias generation circuit BBB, a transistor Q1 for outputting a substrate potential VS at the drain, a drain and a gate are commonly connected, and a source is connected to a ground potential. A transistor Q2 is provided, which is connected to the gate and receives the substrate potential driving signal S of alternating current through the capacitor C1. The difference between the first and second embodiments is that two P well sets 11 and 12, 13 and 14 are provided with BBG 21A and BBG 23A, respectively.

It is preferable that the current driving capability of each of the BBGs 21A and 23A is larger than the current driving capability of the BBGs 21 and 23 of the first embodiment.

This embodiment is useful, for example, when the circuitry in the P well 12 or P well 14 is idle when the P well 11 or P well 13 is operating.

4 is a layout diagram showing a third embodiment of the semiconductor integrated circuit according to the present invention. In FIG. 4, the same reference numerals are used for the same components as in FIG. 2. The semiconductor integrated circuit of this embodiment includes P-type P wells 11A and 12A.

BBG 21B-24B is the same as BBG of FIG. That is, as shown in Fig. 1, it is a back bias generation circuit BBB composed of N-channel MOS transistors formed on a P-type substrate. A drain and a gate are commonly connected to the back bias generation circuit BBB, a transistor Q1 for outputting a substrate potential VS at the drain, a drain and a gate are commonly connected, and a source is connected to a ground potential. A transistor Q2 is provided, which is connected to the gate and receives the substrate potential driving signal S of alternating current through the capacitor C1. The difference between the first embodiment and the third embodiment is that two PBs 11A and 12A are provided with two BBGs 21B and 22B and two BBGs 23B and 24B, respectively. One well potential is set by two BBGs.

In another case, the present invention may be realized in any case in which, for example, the well is divided into eight and eight BBGs are provided with respect to the number of the well dividing methods or the number of BBGs.

5 is a cross-sectional view showing a typical configuration of a well of a semiconductor integrated circuit according to the embodiment. The well manufacturing method will be described with reference to FIG. 5. First, the retrode N well 1 is formed by implanting phosphorus and thermal diffusion using a photomask. Next, boron is implanted into the entire surface of the wafer and phosphorus is implanted using another photomask to form N wells 3 and 5. At this time, P wells 2, 4, and 6 are formed in regions where phosphorus is not implanted. Here, the bottom surface of the P well 4 is separated by the retrolled N well 1, and the periphery of the P well 4 is surrounded by the N wells 3 and 5, so that the P well Is independently separated from the substrate.

When the plurality of P wells 4 are arranged in a chip in a manner such as the P wells 11-14 described above, the planar pattern shown in FIGS. 2 to 4 is completed.

As described above, in the semiconductor integrated circuit of the present invention, it is divided into a plurality of subwells or a plurality of subwell groups each having a back bias circuit BBG. By selectively operating each independent BBG, thereby increasing the current driving capability of the BBG only within the well containing the operation circuit and reducing the current driving capability of the BBG in the well including the non-operating circuitry, thereby It has the effect of stabilizing the potential and at the same time reducing the power consumption.

In addition, since the well is divided into small wells, it is possible to reduce the time constant in the well potential transfer of each of the divided wells. Since the time for setting the well potential at the time of power supply can be shortened, there is an effect that the occurrence of abnormal current in the well can be suppressed.

While the preferred embodiments of the present invention have been described using specific phrases, it is for illustrative purposes only and various modifications and changes are possible within the spirit and scope of the claims.

Claims (6)

In a semiconductor integrated circuit, A back bias generation circuit for generating a substrate potential different from the first power supply voltage supplied to the chip; and A well received at the substrate potential and held at the substrate potential and formed in a predetermined circuit block, The back bias generation circuit and the well are formed on a chip, and the well is divided into a plurality of subwells or a plurality of subwell groups, and the back bias generation circuit is included in each of the plurality of subwells or a plurality of subwell groups. Semiconductor integrated circuits are provided. 2. The semiconductor integrated circuit of claim 1, wherein each of said subwells is provided with one said back bias generation circuit. 2. The semiconductor integrated circuit of claim 1, wherein each of said subwells is provided with at least two said back bias generation circuits. 2. The semiconductor integrated circuit according to claim 1, wherein each subwell group consists of two or more said subwells, and one or more said back bias generation circuits are provided. The semiconductor integrated circuit according to claim 1, wherein the supply capability of each substrate potential of the plurality of back bias generation circuits is independently controlled. 6. The plurality of back bias generation circuits are formed on a first conductivity type semiconductor substrate. A drain and a gate are connected in common, a first transistor of a second conductivity type that outputs the substrate potential at the drain, and a drain and a gate are connected in common, and the drain is connected to a source of the first transistor. And a second conductive type second transistor having a source connected to a second power potential, and the gate receiving a substrate potential supply signal of an alternating current through a capacitor, wherein the semiconductor integrated circuit varies a frequency of the substrate potential driving signal. And controlling the supply capability of the substrate potential.