JPH06235645A - Multiple-rotation absolute encoder - Google Patents

Abstract

PURPOSE:To save consumption current of a battery by making a switch switch a path to that path on power failure when a power supply detection part detects power-failure state and then sending the signal of the most significant bit directly to a multiple-rotation counter. CONSTITUTION:Lower bit detection elements LSB-1-LSB-n and synchronization circuits 5 and 10 are not energized on power failure and only a multiple-rotation counter and the minimum circuit required for storing the data are energized by a battery. The power-failure state is detected by a power supply detection part 6, a switch 7 is switched to a path on power failure according to the signal from the detection part 6, and then the output of the most significant bit detection element MSB is directly input to an OR circuit 11 without passing through the synchronization circuit 10. Therefore, the output of the OR circuit 11 is inputted to a multiple-rotation counter 13, multiple-rotation count is performed by the counter 13 as in normal operation, and then the data are inputted to a storage. Only the minimum circuit which is required is energized by the battery on power failure, thus saving the current consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-turn absolute encoder having a battery backup function.

[0002]

2. Description of the Related Art An absolute encoder using a code other than a gray code for a pattern of a rotary slit changes signals of a plurality of bits when an address changes.
Synchronize by changing the signal of the lowest bit
The signal change timings are aligned. The same applies to a multi-turn absolute encoder that also uses the signal of the highest bit as a count pulse for multi-turn count.

As this type of multi-rotation absolute encoder, there is one having a battery backup function. In the multi-rotation absolute encoder having this battery backup function, conventionally, the change timing of the signal of the highest bit is set to be low even at the time of power failure. It is synchronized with the change timing of the bit signal, and for that reason, the battery is energized to the synchronizing circuit at the time of power failure.

[0004]

However, in the above-described multi-turn absolute encoder, it is sufficient to count the multi-turn and store the data thereof at the time of power failure.
In that case, since the signal of the highest bit is used only as the count pulse of the multi-rotation count, the lower bit
It is not necessary to synchronize with the signal of t. Therefore, in order to extend the battery life, it is better to reduce the current consumption by stopping the extra circuit such as the synchronous circuit at the time of power failure.

The present invention has been made in order to solve the above problems, and in a multi-rotation absolute encoder which performs multi-rotation counting with the signal of the highest bit as a count pulse and has a battery backup function,
It is an object of the present invention to provide a multi-rotation absolute encoder in which an extra circuit such as a synchronous circuit is stopped at the time of a power failure to reduce battery current consumption.

[0006]

The multi-turn absolute encoder of the present invention synchronizes the change timing of the signal of each bit with the change timing of the signal of the lower bit at the time of normal energization, and then makes the signal of each bit one revolution absolute. In the multi-rotation absolute encoder that uses the output signal and also uses the highest bit signal for multi revolution count, the power detection unit that detects the energized state and power failure state, and the highest bit detection by the signal from this power detection unit A switch that switches the element output between a path for normal energization and a path for power failure, a synchronization circuit that synchronizes the output of the switch on the path side during normal energization with the change timing of the lower bit signal, and the output of this synchronization circuit And the OR circuit connected to the output of the above switch at the time of power failure and the output from this OR circuit In which and a multi-turn counter that performs multiple rotation count as a pulse.

[0007]

In the multi-rotation absolute encoder of the present invention, during normal energization, the energized state is detected by the power source detection unit, and the switch outputs the highest bit by the signal from the power source detection unit.
Switch the detection element output to the path when energized, and set the highest bit
Signal is sent to the synchronizing circuit through the path when the power is on, and the synchronizing circuit synchronizes the change timing of the signal of the uppermost bit with the changing timing of the signal of the lower bit, and then the signal from the synchronizing circuit becomes the maximum. The signal from the synchronous circuit is sent to the multi-revolution counter through the OR circuit as a high-order bit signal for one-revolution absolute output, and is used as a count pulse for multi-revolution counting.

Further, at the time of power failure, the power source detecting section detects the power failure state, and the signal from the power source detecting section causes the switch to switch the output of the highest-order bit detection element to the path at the time of power failure, and the signal of the highest-order bit fails. It is sent directly to the multi-revolution counter through the time path, and the signal of the most significant bit is used only for the count pulse of the multi-revolution count.

Therefore, at the time of a power failure, only the minimum circuit necessary for performing multi-revolution counting and storage of the data is energized by the battery, and the current consumption of the battery is saved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multi-turn absolute encoder of the present invention will be described below with reference to the principle diagram.

This multi-turn absolute encoder is
As shown in FIG. 1, a rotary slit 2 in which an absolute code is patterned is attached to the input shaft 1, and after light from the LED 3 passes through the rotary slit 2,
Lower bit detection elements LSB-1, LSB-2, ...
It is adapted to be converted into an electric signal by the LSB-n and the most significant bit detection element MSB.

Lower bit detection elements LSB-1, LSB-
The outputs of 2, ..., LSB-n are connected to the synchronizing circuit 5, and the output of the synchronizing circuit 5 is the lower bit output of the one-turn absolute output.

The uppermost bit detection element MSB is adapted to obtain one pulse output for one rotation of the rotary slit 2, and its output is connected to the switch 7. The switch 7 switches the output of the uppermost bit detection element MSB between the path for normal energization and the path for power failure.
The path of the switch 7 when normally energized is connected to the load resistor 8 and the synchronous circuit 10, and the output of the synchronous circuit 10 is branched into two, one of which is the highest one bi-turn absolute output.
t output, and the other is connected to the OR circuit 11.
The output of the OR circuit 11 is connected to the multi-revolution counter 13,
The multi-revolution absolute output of the multi-revolution counter 13 is connected to a storage device (not shown). The path at the time of power failure is connected to the load resistor 9 and the OR circuit 11. Further, the output of the power supply detection unit 6 is connected to the switch 7.

Further, the LED 3 and the uppermost bit detection element M
A power supply of a battery (not shown) is connected to the SB, the power supply detection unit 6, the switch 7, the OR circuit 11, the multi-rotation counter 13 and the storage device (not shown).

Next, the operation of this multi-turn absolute encoder will be described with reference to FIG.

During normal energization, the lower bit detection element LSB
-1, LSB-2, ..., Each b output by LSB-n
The it signal is input to the synchronization circuit 5, and the synchronization circuit 5
Then, the change timing of the signal of each bit is synchronized with the change timing of the signal of the lowest bit output from the lowest bit detection element LSB-1, and the signal from this synchronizing circuit 5 is used as a signal of the lower bit for one revolution. Used for output. Further, the power supply detection unit 6 detects the energization state of the synchronous circuit 10, and the signal from the power supply detection unit 6 causes the switch 7 to select the path for the normal energization, as shown in FIG. The signal from is input to the synchronizing circuit 10, and in this synchronizing circuit 10, the uppermost bit detection element M is detected.
The change timing of the signal from SB is synchronized with the change timing of the lower bit signal from the synchronizing circuit 5. The signal from the synchronizing circuit 10 is used as a one-bit absolute output as the most significant bit signal and is also input to the OR circuit 11, and the signal from the OR circuit 11 is input to the multi-rotation counter 13 as a count pulse. Then, multi-rotation counting is performed here, and the data is input to a storage device (not shown).

At the time of power failure, the lower bit detection element LSB-
1, LSB-2, ..., LSB-n and the synchronous circuits 5 and 10 are not energized, and only the minimum circuit necessary for storing the multi revolution count and the data thereof is a battery (not shown). Is energized by. The power supply detection unit 6 detects this power failure state, and the signal from the power supply detection unit 6 switches the switch 7 to the path at the time of power failure, and the output of the uppermost bit detection element MSB does not directly pass through the synchronous circuit 10. It is input to the circuit 11. Therefore, the output of the OR circuit 11 is input to the multi-revolution counter 13, and the multi-revolution counter 13
In the same manner as in the case of normal energization, multi-rotation counting is performed, and the data is input to a storage device (not shown).

Next, an embodiment of the multi-turn absolute encoder of the present invention will be described with reference to FIG.

In the multi-rotation absolute encoder of this embodiment, as shown in FIG. 2, a rotary slit 2 having an absolute code patterned is attached to an input shaft 1, and light from an LED 3 is transmitted through the rotary slit 2. The phototransistor array 4 converts the electric signal. Phototransistor array 4
Is a plurality of phototransistors LSB-1, ..., L
SB-n (lower bit detection element) and phototransistors MSB-A and MSB-B (uppermost bit detection element)
It consists of

Phototransistor LSB-1, ...
The output of the LSB-n is connected to the synchronizing circuit 5, and the output of the synchronizing circuit 5 is the lower bit output of the one-turn absolute output.

Phototransistors MSB-A, MSB-
B has a 90 ° phase difference, and each output of one pulse is obtained for one rotation of the rotary slit 2, and the output is connected to the switch 7, respectively. This switch 7 is a phototransistor MSB-
The outputs of A and MSB-B are switched to the route for normal energization and the route for power failure, respectively. The path of the switch 7 on the phototransistor MSB-A side during normal energization is connected to the load resistor 8A and the synchronous circuit 10A, and the synchronous circuit 10A
Is branched into two, one of which is the highest-order bit output of one-turn absolute output, and the other is connected to the OR circuit 11A. In addition, the phototransistor MSB-B
The normal energizing path on the side is connected to the load resistor 8B and the synchronous circuit 10B, and the output of the synchronous circuit 10B is the OR circuit 1.
1B is connected. The path at the time of power failure is the load resistor 9A and the OR circuit 1 on the phototransistor MSB-A side.
1A, and the phototransistor MSB-B side is connected to the load resistor 9B and the OR circuit 11B.
The outputs of the OR circuits 11A and 11B are connected to the direction discriminating circuit 12, the output of the direction discriminating circuit 12 is connected to the multi-revolution counter 13, and the multi-revolution absolute output of the multi-revolution counter 13 is a storage device (not shown). It is connected to the. Further, the output of the power supply detection unit 6 is connected to the switch 7.

Further, the LED 3 and the phototransistor MS
B-A, MSB-B, power supply detection unit 6, switch 7, OR circuits 11A and 11B, direction discrimination circuit 12, multi-rotation counter 13 and storage device (not shown), a battery (not shown) power source. Are connected.

Next, the operation of the multi-turn absolute encoder of this embodiment will be described with reference to FIG.

During normal energization, the phototransistors LSB-1, ..., LSB- of the phototransistor array 4 are
The signal of each bit output from n is input to the synchronization circuit 5,
In the synchronizing circuit 5, the change timing of the signal of each bit is the lowest bit output from the phototransistor LSB-1.
The signal from the synchronizing circuit 5 is used as the lower bit output for the one-revolution absolute output in synchronism with the change timing of the signal. Further, the power supply detection unit 6 detects the energized state, and the switch 7 is detected by a signal from the power supply detection unit 6.
2 selects a path for normal energization as shown in FIG. 2, and signals from the phototransistors MSB-A and MSB-B are input to the synchronizing circuits 10A and 10B.
In 10B, the change timing of the signals from the phototransistors MSB-A and MSB-B is the lower bi from the synchronization circuit 5.
It is synchronized with the change timing of the signal of t. And
The signal from the synchronous circuit 10A on the phototransistor MSB-A side is used as the highest-order bit output for one-turn absolute output, and is also input to the OR circuit 11A, and the signal from this OR circuit 11A is input to the direction discrimination circuit 12.
Entered in. The signal from the synchronizing circuit 10B on the phototransistor MSB-B side is input to the OR circuit 11B, and the signal from the OR circuit 11B is input to the direction discriminating circuit 12.
Entered in. The direction discriminating circuit 12 discriminates the rotation direction from both signals of the OR circuit 11A and the OR circuit 11B having a 90 ° phase difference, and generates up and down pulses (count pulses). The up and down pulses are input to the multi-revolution counter 13, multi-revolution counting is performed here, and the data is input to a storage device (not shown).

At the time of a power failure, the phototransistors LSB-1, ..., LSB-n of the phototransistor array 4 and the synchronous circuits 5, 10A, 10B are not energized, and multi-rotation count and data storage thereof are performed. Only the minimum circuitry required for power is energized by the battery (not shown). The power supply detection unit 6 detects this power failure state, and the signal from the power supply detection unit 6 switches the switch 7 to the path at the time of power failure, and the output of the phototransistor MSB-A and the output of the phototransistor MSB-B are synchronous circuits. 10A, 1
It is directly input to the OR circuits 11A and 11B without passing through 0B. Therefore, the outputs of the OR circuits 11A and 11B are input to the multi-revolution counter 13 through the direction discriminating circuit 12, and the multi-revolution counter 13 performs multi-revolution counting as in the case of normal energization, and the data is stored in the storage device ( (Not shown).

Further, since the maximum number of revolutions is lower during a power failure than during normal energization, in the multi-rotation absolute encoder of this embodiment, the load resistances 9A and 9B in the path during a power failure are the load resistances 8A in the path during normal energization. , 8B, and since the drive current of the LED 3 can be reduced during a power failure, the current consumption of the battery can be further reduced.

[0027]

According to the multi-rotation absolute encoder of the present invention, after the signal change timing of each bit is synchronized with the change timing of the lower bit signal during normal energization, the signal of each bit is output as one rotation absolute output. In addition to being used, in a multi-rotation absolute encoder that also uses the highest bit signal for multi-rotation counting, the power detection unit that detects the energized state and power failure state, and the signal from this power detection unit outputs the highest bit detection element And a switch that switches between the path for normal energization and the path for power failure,
The output on the path side when this switch is normally energized is the lower bit.
The synchronization circuit that synchronizes at the timing of the signal change, the OR circuit connected to the output of this synchronization circuit and the output of the path side of the above switch at the time of power failure, and the output from this OR circuit as the count pulse Since it has a multi-rotation counter that counts, only the minimum circuit necessary for storing the multi-revolution count and its data is energized by the battery at the time of power failure, and the current consumption of the battery can be reduced. .

Further, since the signal of the highest-order bit detection element passes through different paths during normal energization and during a power failure, different load resistors can be connected to each path, and during a power failure the response frequency is higher than during normal energization. Since the load resistance at the time of power failure can be increased and the LED drive current can be reduced at the time of power failure, the current consumption of the battery can be further reduced.

[Brief description of drawings]

FIG. 1 is a principle diagram of a multi-turn absolute encoder of the present invention.

FIG. 2 is a schematic configuration diagram showing an embodiment of a multi-turn absolute encoder of the present invention.

[Explanation of symbols]

6 Power Supply Detection Section 7 Switch 10, 10A, 10B Synchronous Circuit 11, 11A, 11B OR Circuit 13 Multi-Revolution Counter MSB Highest Bit Detection Element MSB-A, MSB-B Highest Bit Detection Element (Phototransistor)

Claims (1)

[Claims] 1. When the change timing of the signal of each bit is synchronized with the change timing of the signal of the lower bit at the time of normal energization, the signal of each bit is used for one-turn absolute output, and the signal of the highest bit is increased. In a multi-rotation absolute encoder that is also used for rotation counting, a power supply detection unit that detects the energization state and power failure state, and the signal from this power supply detection unit outputs the uppermost bit detection element to the normal energization path and the power failure path. Switch and the output on the path side when this switch is normally energized, the lower bit
The synchronization circuit that synchronizes with the signal change timing, the OR circuit connected to the output of this synchronization circuit and the output of the path side of the above switch at the time of power failure, and the output from this OR circuit as the count pulse A multi-rotation absolute encoder, comprising a multi-rotation counter for counting.