JPH06232406A - Substrate for semiconductor element - Google Patents

Substrate for semiconductor element

Info

Publication number
JPH06232406A
JPH06232406A JP3396793A JP3396793A JPH06232406A JP H06232406 A JPH06232406 A JP H06232406A JP 3396793 A JP3396793 A JP 3396793A JP 3396793 A JP3396793 A JP 3396793A JP H06232406 A JPH06232406 A JP H06232406A
Authority
JP
Japan
Prior art keywords
substrate
layer
semiconductor element
single crystal
porous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3396793A
Other languages
Japanese (ja)
Inventor
Akira Ishizaki
明 石崎
Shigetoshi Sugawa
成利 須川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP3396793A priority Critical patent/JPH06232406A/en
Publication of JPH06232406A publication Critical patent/JPH06232406A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To provide a substrate for a semiconductor element in which the potential of the conductive substrate can be easily controlled by taking out the continuity of electricity of the conductive substrate through a contact hole from a semiconductor layer side in the plural places of the circumferential edge part of the substrate. CONSTITUTION:This substrate is a layered product in which a single crystal Si layer 3 is stuck together to an Si substrate 1 through an SiO2 layer 2, and the other single crystal Si layer and SiO2 layer than the effective region to be used for a semiconductor element all are removed to form an SiO2 layer 2' by oxidizing a gate and to perform the element isolation and a polycrystalline Si is deposited to form a gate electrode 4. At the same time, ions are implanted into the source and the drain of an element and an Si substrate 1. After an insulating layer (SiO2 layer) is formed, contact holes 5, 5' are made in the insulating layer to perform the wirings 6, 6' thereof. Therefore, the plural contact holes 5' are formed in the circumferential edge part of the substrate 1 to take out the continuity of electricity of the conductive substrate 1, thereby being able to more uniformly control the potential of the conductive substrate 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、例えばTFT(薄膜ト
ランジスタ)を用いたアクティブマトリクス駆動型の液
晶表示装置など、光透過領域に半導体素子を有する装置
に用いる半導体素子基板に関する発明である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element substrate used in a device having a semiconductor element in a light transmitting region, such as an active matrix driving type liquid crystal display device using a TFT (thin film transistor).

【0002】[0002]

【従来の技術】絶縁層上に単結晶Si層を形成してなる
SOI(シリコンオンインシュレータ)の技術は、半導
体素子基板において、単結晶Siがα(アモルファス)
−Siや多結晶Siに比べて多くの優位点を有している
ことから広く研究され、近年注目されている薄膜トラン
ジスタ(TFT)等への利用が期待されている。
2. Description of the Related Art In the technology of SOI (silicon on insulator) in which a single crystal Si layer is formed on an insulating layer, in a semiconductor element substrate, single crystal Si is α (amorphous).
Since it has many advantages over -Si and polycrystalline Si, it has been widely studied and is expected to be used for a thin film transistor (TFT) or the like which has been attracting attention in recent years.

【0003】このSOIの製造方法としては、例えば、
単結晶Si基体(バルク)に酸素をイオン注入して単結
晶Si薄膜を分離形成するSIMOX(Separat
inby Implanted Oxigen)が知ら
れている。
As a method of manufacturing this SOI, for example,
SIMOX (Separat) for separately forming a single crystal Si thin film by ion-implanting oxygen into a single crystal Si substrate (bulk)
Inby Implanted Oxygen) is known.

【0004】また、本出願人は上記したSOI技術の一
つとして多孔質Siを用い、その表面に単結晶Siをエ
ピタキシャル成長させる方法を達成した。この方法によ
ると、ほとんど欠陥の無い単結晶Si基板が得られる。
本方法を簡単に説明する。
Further, the present applicant has achieved a method of epitaxially growing single crystal Si on the surface of porous Si as one of the SOI techniques described above. According to this method, a single crystal Si substrate having almost no defects can be obtained.
The method will be briefly described.

【0005】図4に多孔質Siを用いた単結晶Si基板
の製造工程を示した。先ず第1のSi基体11表面を多
孔質化し、多孔質Si層12を形成する(a)。この多
孔質Si層12表面にSiの単結晶3をエピタキシャル
成長させる(b)。一方、Si基板1を用意し、その表
面に絶縁性のSiO2 層2を形成し、該SiO2 層2と
上記単結晶Si層3を貼り合わせ(c)、多孔質化した
Si基体をエッチング除去しSi基板を得る(d)。
FIG. 4 shows a manufacturing process of a single crystal Si substrate using porous Si. First, the surface of the first Si substrate 11 is made porous to form a porous Si layer 12 (a). An Si single crystal 3 is epitaxially grown on the surface of the porous Si layer 12 (b). On the other hand, a Si substrate 1 is prepared, an insulating SiO 2 layer 2 is formed on the surface thereof, the SiO 2 layer 2 and the single crystal Si layer 3 are bonded (c), and the porous Si substrate is etched. It is removed to obtain a Si substrate (d).

【0006】[0006]

【発明が解決しようとする課題】SOIは上記のよう
に、半導体であるSi基板上に絶縁層を介して形成され
る。従って、SOIを用いて作製された半導体素子は、
このSi基板の電位の影響を受け、特性が低下する。通
常のLSI等の半導体素子基板の場合には、Si基板の
裏面に金属等の導電層を形成し、該導電層の電位を制御
していた。
As described above, the SOI is formed on the Si substrate which is a semiconductor via the insulating layer. Therefore, a semiconductor element manufactured using SOI is
The characteristics are deteriorated under the influence of the potential of the Si substrate. In the case of a normal semiconductor element substrate such as an LSI, a conductive layer made of metal or the like is formed on the back surface of a Si substrate, and the potential of the conductive layer is controlled.

【0007】しかしながら、半導体素子基板を表示装置
等に実装する上ではSi基板の裏面側で電位を制御する
よりも、半導体素子側にコンタクトを取り出す方が望ま
しい。
However, in mounting the semiconductor element substrate on a display device or the like, it is desirable to take out a contact on the semiconductor element side rather than controlling the potential on the back side of the Si substrate.

【0008】また、上記した本出願人が先に達成した多
孔質化Siを用いたSOI作製技術を、近年注目されて
いるTFTを用いたアクティブマトリクス型の液晶表示
装置の様に、液晶パネルの透光領域内に半導体素子を有
する装置に用いる場合には、図3に示した様に、表面に
SiO2 層を形成して透明化した基板に貼り合わせた
後、図4に示す如く半導体素子13を形成し(a)、透
明化したい領域についてはSi基板1をエッチング除去
してくりぬき部15形成し、透光領域とする(b)。こ
のくり抜き工程においては、SiO2 やSiN4 等絶縁
層14をSi基板裏面に形成してエッチング用のマスク
とするために、従来の裏面からコンタクトを取る方法で
は絶縁層を除去する工程が必要になり、煩雑である。
Further, the above-mentioned SOI fabrication technique using porous Si achieved by the applicant of the present invention is applied to a liquid crystal panel such as an active matrix type liquid crystal display device using a TFT, which has been attracting attention in recent years. When used in a device having a semiconductor element in the light-transmitting region, as shown in FIG. 3, after a SiO 2 layer is formed on the surface and bonded to a transparent substrate, as shown in FIG. 13 is formed (a), and the region to be made transparent is removed by etching the Si substrate 1 to form a hollow portion 15 to be a light transmitting region (b). In this hollowing process, the insulating layer 14 such as SiO 2 or SiN 4 is formed on the back surface of the Si substrate to serve as a mask for etching. Therefore, the conventional method of contacting from the back surface requires the step of removing the insulating layer. It is complicated.

【0009】本発明は、導電性基板を有する半導体素子
基板において、該導電性基板の電位制御を容易に行なう
ことを目的とする。
An object of the present invention is to easily control the potential of a conductive substrate in a semiconductor element substrate having the conductive substrate.

【0010】[0010]

【課題を解決するための手段】本発明は、導電性基板上
に、絶縁層を介して半導体層を形成してなる半導体素子
基板であって、該基板周縁部の複数箇所において、上記
半導体層側からコンタクトホールを通じて上記導電性基
板の導通を取り出したことを特徴とする半導体素子基板
である。本発明は半導体分野で広く用いられているSi
において好適に応用され、特に、前記したSOIに適し
た発明である。
The present invention is a semiconductor element substrate having a semiconductor layer formed on a conductive substrate with an insulating layer interposed between the semiconductor layer and the semiconductor layer at a plurality of positions on the periphery of the substrate. The semiconductor element substrate is characterized in that the conduction of the conductive substrate is taken out from the side through a contact hole. The present invention is widely used in the semiconductor field.
The invention is preferably applied to, and is particularly suitable for the SOI described above.

【0011】尚、前記した多孔質Siについて詳細に説
明する。多孔質Siは、Uhlir等によって1956
年に半導体の電解研磨の研究過程において発見された
[A.Uhlir,Bell Syst.Tech.
J.,vol 35,333(1956)]。また、ウ
ナガミ等は、陽極化成におけるSiの溶解反応を研究
し、HF溶液中のSiの陽極反応には正孔が必要であ
り、その反応は、次の様であると報告している[T.ウ
ナガミ:J.Electrochem.Soc.,vo
l.127,476(1980)]。
The above-mentioned porous Si will be described in detail. Porous Si is described in 1956 by Uhir et al.
It was discovered in the course of research on electropolishing of semiconductors in the year [A. Uhir, Bell System. Tech.
J. , Vol 35, 333 (1956)]. In addition, Unami et al. Studied the dissolution reaction of Si in anodization and reported that the anodic reaction of Si in HF solution requires holes, and the reaction is as follows [T. . Unagami: J. Electrochem. Soc. , Vo
l. 127, 476 (1980)].

【0012】 Si+2HF+(2−n)e+ →SiF2 +2H+ +ne- SiF2 +2HF→SiF4 +H2 SiF4 +2HF→H2 SiF6 又は、 Si+4HF+(4−λ)e+ →SiF4 +4H+ +λe- SiF4 +2HF→H2 SiF6 ここで、e+ 及びe- はそれぞれ、正孔と電子を表して
いる。また、n及びλは夫々Si1原子が溶解するため
に必要な正孔の数であり、n>2又はλ>4なる条件が
満たされた場合に多孔質Siが形成されるとしている。
Si + 2HF + (2-n) e + → SiF 2 + 2H + + ne - SiF 2 + 2HF → SiF 4 + H 2 SiF 4 + 2HF → H 2 SiF 6 or Si + 4HF + (4-λ) e + → SiF 4 + 4H + + λe - where SiF 4 + 2HF → H 2 SiF 6, e + , e -, respectively, represent the holes and electrons. Further, n and λ are the numbers of holes necessary for dissolving Si1 atoms, respectively, and porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

【0013】このように、多孔質Siを作成するために
は、正孔が必要であり、N型Siに比べてP型Siの方
が多孔質Siに変質し易い。しかし、N型Siも正孔に
注入があれば、多孔質Siに変質することが知られてい
る。[R.P.Holmstrom and J.Y.
Chi.Appl.Phys.Lett.vol.4
2,386(1983)]。
As described above, holes are required to form porous Si, and P-type Si is more likely to be transformed into porous Si than N-type Si. However, it is known that N-type Si is also transformed into porous Si if holes are injected. [R. P. Holmstrom and J. Y.
Chi. Appl. Phys. Lett. vol. Four
2, 386 (1983)].

【0014】このようにして作成された多孔質Siは、
単結晶Siの密度2.33g/cm3 に比べて、HF溶
液濃度を50〜20%に変化させることで、その密度を
1.1〜0.6g/cm3 の範囲に変化させることがで
きる。この多孔質Si層は、透過型電子顕微鏡による観
察によれば、平均約600Å程度の径の孔が形成され
る。その密度は単結晶Siに比べると、半分以下になる
にも関わらず、単結晶性は維持されており、多孔質層の
上部へ単結晶Siをエピタキシャル成長させることがで
きる。
The porous Si produced in this way is
By changing the HF solution concentration to 50 to 20% as compared with the density of single crystal Si of 2.33 g / cm 3 , the density can be changed to the range of 1.1 to 0.6 g / cm 3. . According to observation with a transmission electron microscope, pores having an average diameter of about 600 Å are formed in this porous Si layer. Despite its density being less than half that of single crystal Si, single crystallinity is maintained, and single crystal Si can be epitaxially grown on the upper part of the porous layer.

【0015】一般に単結晶Siを酸化すると、その体積
は約2.2倍に増大するが、多孔質の密度を制御するこ
とにより、その体積膨張を抑制することが可能となり、
基体の反りと、表面残留単結晶層に導入されるクラック
を回避できる。単結晶Siの多孔質Siに対する酸化後
の体積比Rは次の様に表すことができる。
Generally, when single-crystal Si is oxidized, its volume increases about 2.2 times, but it is possible to suppress the volume expansion by controlling the density of the porous material.
Warpage of the substrate and cracks introduced into the surface residual single crystal layer can be avoided. The volume ratio R of single crystal Si after being oxidized to porous Si can be expressed as follows.

【0016】R=2.2×(A/2.33) ここで、Aは多孔質Siの密度である。もし、R=1、
即ち酸化後の体積膨張がない場合には、A=1.06
(g/cm3 )となり、多孔質Siの密度を1.06に
すれば、体積膨張を抑制することができる。
R = 2.2 × (A / 2.33) where A is the density of porous Si. If R = 1,
That is, if there is no volume expansion after oxidation, A = 1.06
(G / cm 3 ), and if the density of porous Si is set to 1.06, volume expansion can be suppressed.

【0017】また、多孔質層はその内部に大量の空隙が
形成されているために、密度が半分以下に減少する。そ
の結果、体積に比べて表面積が飛躍的に増大するため、
その化学エッチング速度は、非多孔質Si層のエッチン
グ速度に比べて、著しく増速される。
Further, since the porous layer has a large amount of voids formed therein, its density is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
Its chemical etching rate is significantly enhanced compared to the etching rate of the non-porous Si layer.

【0018】本発明に係るSi基体の多孔質化の条件は
特に限定されない。例えば下記の条件が好ましく用いら
れる。
The conditions for making the Si substrate porous according to the present invention are not particularly limited. For example, the following conditions are preferably used.

【0019】 電流密度J=10−3〜10 A/cm 好ましくは10−2〜10−1A/cm 溶液=HF(49%):C OH:H O 多孔質層の膜厚=0.1〜100μm 好ましくは1〜10μm Porosity=20〜50%The current density J = 10 -3 ~10 0 A / cm 2 preferably 10 -2 ~10 -1 A / cm 2 solution = HF (49%): C 2 H 5 OH: H 2 O porous layer Film thickness = 0.1 to 100 μm, preferably 1 to 10 μm Porosity = 20 to 50%

【0020】[0020]

【実施例及び作用】以下、Siを例に挙げて本発明を具
体的に説明する。
EXAMPLES AND ACTION The present invention will be described in detail below by taking Si as an example.

【0021】図1に本発明の半導体素子基板の一実施例
の製造工程を示す。本図において、1はSi基板、2〜
2”は絶縁層としてのSiO2 層、3は単結晶Si層、
4はゲート電極、5はコンタクトホール、6、6’は配
線である。本図(a)は前記した図4(d)に相当す
る、単結晶Si層3をSiO2 層2を介してSi基板1
に貼り合わせた積層体である。半導体素子に用いる有効
領域以外の単結晶Si層及びSiO2 層を全て除去し、
ゲート酸化してSiO2 層2’を形成する(b)。次に
素子分離を行ない(c)、多結晶Siを堆積してゲート
電極4を形成すると同時に素子のソース、ドレインにイ
オン注入を行なう。この時同時にSi基板1にもイオン
注入を行ない、後述の配線5’のコンタクト性を高める
ことができる。次に及び絶縁層(SiO2 層)2”を形
成した後(d)、コンタクトホール5、5’を絶縁層に
穿って配線6、6’を接続する(e)。本図に示した様
に、(a)〜(b)の工程で不要な単結晶Si層を除去
する際に、SiO2 層まで除去したことにより、素子の
コンタクトホール5とSi基板のコンタクトホール5’
が同じ厚さの絶縁層に形成されることとなり、製造効率
が良い。従って、上記SiO2 層2を除去せずにそのま
ま残しておいても本発明の構成上何ら支障はない。
FIG. 1 shows a manufacturing process of an embodiment of the semiconductor element substrate of the present invention. In the figure, 1 is a Si substrate, 2 to
2 "is a SiO 2 layer as an insulating layer, 3 is a single crystal Si layer,
Reference numeral 4 is a gate electrode, 5 is a contact hole, and 6 and 6'are wirings. This figure (a) corresponds to the above-mentioned figure 4 (d), the single crystal Si layer 3 through the SiO 2 layer 2 Si substrate 1
It is a laminated body stuck to. All of the single crystal Si layer and the SiO 2 layer other than the effective area used for the semiconductor element are removed,
Gate oxidation is performed to form a SiO 2 layer 2 '(b). Next, element isolation is performed (c), polycrystalline Si is deposited to form the gate electrode 4, and at the same time, ion implantation is performed on the source and drain of the element. At this time, the Si substrate 1 is also ion-implanted at the same time, so that the contact property of the wiring 5 ′ described later can be improved. Next, and after forming the insulating layer (SiO 2 layer) 2 ″ (d), the contact holes 5 and 5 ′ are drilled in the insulating layer to connect the wirings 6 and 6 ′ (e). In addition, when the unnecessary single crystal Si layer is removed in the steps (a) and (b), the SiO 2 layer is also removed, so that the element contact hole 5 and the Si substrate contact hole 5 ′ are removed.
Are formed in the insulating layer having the same thickness, and the manufacturing efficiency is good. Therefore, there is no problem in the structure of the present invention even if the SiO 2 layer 2 is left as it is without being removed.

【0022】更に、図1に示した工程により得られた本
発明の半導体素子基板に、図2に示す如く絶縁層7及び
画素電極8を形成し、必要な透明領域においてSi基板
1をくり抜いて透明化すれば、液晶表示装置の駆動電極
基板が得られる。
Further, as shown in FIG. 2, an insulating layer 7 and a pixel electrode 8 are formed on the semiconductor element substrate of the present invention obtained by the process shown in FIG. 1, and the Si substrate 1 is hollowed out in a necessary transparent region. By making it transparent, a drive electrode substrate for a liquid crystal display device can be obtained.

【0023】図3に本発明の半導体基板の半導体素子側
から見た図を示す。本図においてA〜Dは各半導体素子
基板であり、通常、半導体素子基板はこの様に1枚のウ
エハから複数枚が同時に製造され、カットライン10で
切断されて分離される。9はSiエッジで、半導体素子
が形成された領域である。本発明においては、本図に示
す通り、基板周縁部に複数のコンタクトホール5’を形
成し、導電性基板の導通を取り出すことにより、導電性
基板の電位をより均一に制御することができる。特に、
SOIにおいては基板が半導体であって導電性が高くな
いため、1箇所だけで電位を制御することは難しく、同
一基板内で電位にむらができ易いため、本発明は望まし
く用いられる。
FIG. 3 shows a view of the semiconductor substrate of the present invention viewed from the semiconductor element side. In the figure, A to D are respective semiconductor element substrates, and normally, a plurality of semiconductor element substrates are simultaneously manufactured from one wafer in this way, and are cut and separated by a cut line 10. Reference numeral 9 denotes a Si edge, which is a region where a semiconductor element is formed. In the present invention, as shown in the figure, by forming a plurality of contact holes 5'in the peripheral portion of the substrate and taking out conduction of the conductive substrate, the potential of the conductive substrate can be controlled more uniformly. In particular,
In SOI, since the substrate is a semiconductor and its conductivity is not high, it is difficult to control the potential at only one place, and the potential is likely to be uneven within the same substrate, so the present invention is preferably used.

【0024】[0024]

【発明の効果】以上説明したように、本発明の半導体素
子基板は裏面の電位が均一に制御できるために、同一基
板内で半導体素子の特性にむらがなく、いずれの素子も
安定した動作を行なうことができる。従って、信頼性の
高い表示装置を得ることができる。しかも、本発明に係
る、導電性基板の導通は、通常の半導体素子の形成工程
において同時に作り込むことができるため、製造上新た
な工程を加える必要が無く、基板の製造設計及び歩留の
上からも非常に有用である。
As described above, in the semiconductor element substrate of the present invention, since the back surface potential can be uniformly controlled, the characteristics of the semiconductor elements are uniform in the same substrate, and all the elements can operate stably. Can be done. Therefore, a highly reliable display device can be obtained. Moreover, the conduction of the conductive substrate according to the present invention can be created at the same time in the normal semiconductor element forming process, so that it is not necessary to add a new process in manufacturing, and the manufacturing design and yield of the substrate can be improved. It is also very useful.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子基板の一実施例の製造工程
を示す図である。
FIG. 1 is a diagram showing a manufacturing process of an embodiment of a semiconductor element substrate of the present invention.

【図2】本発明の半導体素子基板を用いた液晶表示装置
の製造工程を示す図である。
FIG. 2 is a diagram showing a manufacturing process of a liquid crystal display device using the semiconductor element substrate of the present invention.

【図3】本発明の半導体素子基板の半導体素子側から見
た図である。
FIG. 3 is a view of the semiconductor element substrate of the present invention viewed from the semiconductor element side.

【図4】本発明に係る単結晶Siの製造工程を示す図で
ある。
FIG. 4 is a diagram showing a manufacturing process of single crystal Si according to the present invention.

【図5】本発明に係る単結晶Siを用いた液晶表示装置
の製造工程を示す図である。
FIG. 5 is a diagram showing a manufacturing process of a liquid crystal display device using single crystal Si according to the present invention.

【符号の説明】[Explanation of symbols]

1 Si基板 2〜2” SiO2 層 3 単結晶Si層 4 ゲート電極 5、5’ コンタクトホール 6、6’ 配線 7 絶縁層 8 画素電極 9 Siエッジ 10 カットライン 11 Si基体 12 多孔質化Si層 13 半導体素子 14 絶縁層 15 くり抜き部1 Si substrate 2 to 2 "SiO 2 layer 3 single crystal Si layer 4 gate electrode 5, 5 'contact hole 6,6' wiring 7 insulating layer 8 pixel electrode 9 Si edge 10 cut line 11 Si substrate 12 made porous Si layer 13 semiconductor element 14 insulating layer 15 hollow portion

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 導電性基板上に、絶縁層を介して半導体
層を形成してなる半導体素子基板であって、該基板周縁
部の複数箇所において、上記半導体層側からコンタクト
ホールを通じて上記導電性基板の導通を取り出したこと
を特徴とする半導体素子基板。
1. A semiconductor element substrate comprising a conductive substrate and a semiconductor layer formed on the conductive substrate with an insulating layer interposed between the conductive layer and the semiconductor layer. A semiconductor element substrate characterized by taking out the continuity of the substrate.
【請求項2】 半導体がSiであることを特徴とする請
求項1記載の半導体素子基板。
2. The semiconductor element substrate according to claim 1, wherein the semiconductor is Si.
JP3396793A 1993-02-01 1993-02-01 Substrate for semiconductor element Withdrawn JPH06232406A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3396793A JPH06232406A (en) 1993-02-01 1993-02-01 Substrate for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3396793A JPH06232406A (en) 1993-02-01 1993-02-01 Substrate for semiconductor element

Publications (1)

Publication Number Publication Date
JPH06232406A true JPH06232406A (en) 1994-08-19

Family

ID=12401268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3396793A Withdrawn JPH06232406A (en) 1993-02-01 1993-02-01 Substrate for semiconductor element

Country Status (1)

Country Link
JP (1) JPH06232406A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008283216A (en) * 2008-07-28 2008-11-20 Oki Electric Ind Co Ltd Semiconductor device, and manufacturing method thereof
JP2012134568A (en) * 1995-11-27 2012-07-12 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012134568A (en) * 1995-11-27 2012-07-12 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device
JP2008283216A (en) * 2008-07-28 2008-11-20 Oki Electric Ind Co Ltd Semiconductor device, and manufacturing method thereof

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