JPH06231579A - Data input circuit of semiconductor storage circuit - Google Patents

Abstract

PURPOSE:To prevent write time when data are inputted from being extended when the load capacity of the internal signal wire of a semiconductor storage circuit becomes large. CONSTITUTION:The drain and the source of a MOS transistor 16 with an one- shot pulse signal OS created from data input signal as an input are connected between the in-phase and opposite phase output signals which are created from the data input signal. Or the drain or the source of the MOS transistor is connected to the in-phase or opposite phase signal created from the data input signal, thus reducing the rising time and falling time of the output signal of a data input circuit and hence preventing write time to a storage circuit from being extended.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a data input circuit for a semiconductor memory circuit which operates at high speed.

[0002]

2. Description of the Related Art Generally, semiconductor memory circuits are used in memory devices such as super computers and workstations. FIG. 9 shows an example of a block diagram of a semiconductor memory circuit.

In FIG. 9, address buffers 21 and 2 are shown.
Reference numeral 2 is a circuit for transmitting an input (hereinafter referred to as an address) that determines an address for reading and writing of the memory circuit to the inside of the semiconductor memory circuit, and a row / column decoder circuit 2
The address of the memory circuit body 25 is determined by 3, 24.
The address includes A0 to An. The input / output data control circuits 27, 28 are circuits for transmitting write / read data to the memory circuit body 25 and for outputting from the memory circuit body 25. The memory circuit body 25 is
This circuit holds written data. The sense / switch circuit 26 is a circuit that amplifies the minute data read from the memory circuit body 25.

The structure and operation of the above-described data input circuit of the semiconductor memory circuit will be described with reference to FIGS. 5 and 6, the NOR circuits 1, 9, 11 and the inverter circuits 2, 4, 5, 6, 7, 8, 10, 12 and
A NAND circuit 3 and load capacitors 13 and 14 of output signals DBB and DB of the data input circuit are shown.

The data input circuit of the semiconductor memory circuit includes a data input signal (hereinafter referred to as signal DIN), a chip select signal (hereinafter referred to as signal CS), a write enable signal (hereinafter referred to as signal WE), and a signal. DB, D
It has a BB output signal.

The signal CS is a control signal for activating (low level) or inactivating (high level) the semiconductor memory circuit. The signal WE is a signal for controlling whether the semiconductor memory circuit is to be written (low level) or read (high level). The signals DB and DBB are output signals for transmitting the signal DIN to the memory circuit. The signal DB is an output signal in phase with the signal DIN, and the signal DBB is an output signal in phase with the signal DIN.

Next, the operation of the data input circuit of the semiconductor memory circuit will be described. First, the case where the semiconductor memory circuit is active (the signal CS is at the low level) and is in the written state (the signal WE is at the low level) will be described. Signal DIN
Signal changes from low level to high level, signal D
B also changes from the low level to the high level, and the signal DBB changes from the high level to the low level. Signal DB, DB
When B changes, high-level data is written in the memory circuit. Similarly, when the signal DIN changes from the high level to the low level, the signal DB also changes from the high level to the low level, and the signal DBB changes from the low level to the high level. When the signals DB and DBB change, low level data is written in the memory circuit. FIG. 6 is an internal waveform diagram of FIG. There is a time delay T'from the input of the data to the writing to the semiconductor memory circuit, that is, from the change of the signal DIN to the change of the signals DB and DBB. As the speed of peripheral devices of the semiconductor memory circuit increases, the semiconductor memory circuit also needs to operate at high speed. Therefore, it is preferable that the time T ′ is short. Therefore, conventionally, the load capacity 1
3 and 14, inverter circuits having a sufficiently large driving ability were used.

FIG. 7 shows a signal DIN for the circuit of FIG.
It is a circuit in which the signal DBB of the opposite phase is omitted. The operation of FIG. 7 is similar to that of FIG. 5, when the signal DIN changes from the low level to the high level, the signal DB also changes from the low level to the high level, and the high level data is written in the memory circuit. Further, when the signal DIN changes from the high level to the low level, the signal DB also changes from the high level to the low level, and the low level data is written in the memory circuit.

FIG. 8 is an internal waveform diagram of FIG. Similar to FIG. 6, there is a delay of time T'from the change of the signal DIN to the change of the signal DB.

When the semiconductor memory circuit is inactive (the signal CS is at the high level) or read (the signal WE is at the high level), both the signals DB and DBB are at the high level regardless of the signal DIN, and the inside of the memory circuit is , Not written.

[0011]

Generally, in the semiconductor memory circuit, the area of the semiconductor memory circuit element tends to increase as the degree of integration and capacity increase in recent years. As the area increases, the length of the signal line becomes longer and the load capacitance also increases. As for the output signals DB and DBB of the data input circuit (FIGS. 5 and 7) of the conventional semiconductor memory circuit described above, the load capacitance increases as the area increases. If the load capacitance becomes large, the charging and discharging time of the load capacitance becomes long, so that the rise and fall times of the output signal become long and the writing time to the memory circuit is delayed. Conventionally, an inverter circuit with a large driving capability was used, but it had the drawback of consuming a large amount of current.

An object of the present invention is to provide a data input circuit of a semiconductor memory circuit which can solve the above-mentioned drawbacks and shorten the rise and fall times of an output signal without increasing the current consumption. .

[0013]

The first structure of the present invention is as follows.
Data input of a semiconductor memory circuit including a first signal line that outputs an in-phase output signal that is formed from a data input signal and a second signal line that outputs an opposite-phase output signal that is formed from the data input signal The circuit is provided with means for bringing the first signal line and the second signal line close to the same potential.

According to a second aspect of the present invention, in the data input circuit of the semiconductor memory circuit having the first signal line for outputting the in-phase output signal generated from the data input signal, the potential of the first signal line is Is provided to make the intermediate potential between the first and second power supplies.

[0015]

The present invention will be described below with reference to the drawings. Figure 1
FIG. 3 is a circuit diagram showing a data input circuit of the semiconductor memory circuit of the first embodiment of the present invention. FIG. 2 is an internal waveform diagram of FIG.

In FIG. 1, the present embodiment shows a P channel M.
OS transistor 16 and one-shot pulse generation circuit 1
5 and are added. The other circuit parts are the same as those in FIG.

The one-shot pulse generation circuit 15 is a circuit for generating a one-shot pulse signal OS when the signal DIN changes from a low level to a high level and when the signal DIN changes from a high level to a low level. The drain and source of the P-channel MOS transistor that receives the one-shot pulse signal OS as a gate input are connected to the output signals DB and DBB of the data input circuit of the semiconductor memory circuit. While the one-shot pulse signal OS is being generated, the P-channel MOS transistor 16 is turned on to bring the potentials of the signal lines DB and DBB having a potential difference close to the same potential.

Next, the case where the semiconductor memory circuit is active (the signal CS is at the low level) and is in the written state (the signal WE is at the low level) will be described. When the signal DIN changes from the low level to the high level, the signal DB is initially at the low level and the signal DBB is at the high level, but the signal DI
When N changes, the signal DB becomes high level and the signal DBB becomes low level. At this time, if the load capacitances 13 and 14 are large, the rise and fall times of the signals DB and DBB become long. Therefore, as described above, the signal DI
When N changes, the one-shot pulse generation circuit 15 generates the one-shot pulse signal OS. This one-shot pulse signal OS is input, and signals DB and DBB are input.
When the P-channel MOS transistor 16 connected to is turned on, the potentials of the signals DB and DBB tend to approach the same potential. The P-channel MOS transistor 16 helps the signals DB and DBB to change from the high level to the low level or from the low level to the high level, and the rise and fall times of the signals DB and DBB can be shortened.

Conversely, when the signal DIN changes from the high level to the low level, the one-shot pulse generation circuit 15 similarly generates the one-shot pulse signal OS, and the potentials of the signals DB and DBB are set to the same potential. , The rise and fall times of the signals DB and DBB can be shortened. One-shot pulse signal O
By generating S and trying to bring the potentials of the signals DB and DBB close to the same potential, in FIG. 2, the delay from the change of the signal DIN to the change of the signals DB and DBB is the time T. . Therefore, by using the one-shot pulse signal OS, data can be written in the memory circuit in a time shorter than the time T'in FIG.

FIG. 3 is a circuit diagram showing a data input circuit of a semiconductor memory circuit according to the second embodiment of the present invention. FIG. 4 is an internal waveform diagram of FIG.

In FIG. 3, the second embodiment of the present invention is as follows.
FIG. 7 shows a one-shot generation circuit 15 and a P-channel MOS.
Transistor 17, N-channel MOS transistor 1
8 and inverter circuits 19 and 20 are added.

The P-channel MOS transistor 17 and the N-channel MOS transistor 18 are arranged such that, when they are turned on at the same time, the output potential becomes an intermediate potential between the power supply and the ground potential. Similar to FIG. 1, the one-shot pulse signal OS generated when the signal DIN changes is the N-channel MOS.
Transistor 18 and P-channel MOS transistor 1
It has been input to 7. This one-shot pulse signal O
By S, the P-channel MOS transistor 17 and N
The channel MOS transistor 18 is turned on at the same time to bring the signal DB close to an intermediate potential between the power supply and the ground potential. Figure 4
, The signal DB changes from the signal DIN by bringing the signal DB close to an intermediate potential between the power supply and the ground potential, and then the signal DB,
It takes time T until the DBB changes. Therefore, by using the one-shot pulse signal OS, writing to the memory circuit can be performed in a time shorter than the time T'in FIG.

As in the conventional example, the semiconductor memory circuit is inactive (signal CS is at high level) or read (signal WE).
Is high level), regardless of the signal DIN, the signals DB and DBB both become high level, and the inside of the memory circuit is not written.

In the above description, the case where there is one data input signal has been described as an example, but the present invention is not limited to this, and the same effect can be obtained in the case of multiple data input.

As described above, according to the present invention, the drain and source of the MOS transistor, which receives the one-shot pulse signal generated from the data input signal, are connected to the drain and source of the in-phase and anti-phase output signals generated from the data input signal. A data input circuit of a semiconductor memory circuit is obtained, characterized in that it is connected in between, or the drain or source of the MOS transistor is connected to an in-phase or anti-phase output signal generated from the data input signal.

[0026]

As described above, according to the present invention, the drain and source of a MOS transistor, which receives a one-shot pulse signal generated from a data input signal, outputs the in-phase and anti-phase signals generated from the data input signal. By connecting between the signals, the rise and fall times of the output signal of the data input circuit can be shortened, and the writing time to the memory circuit can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a data input circuit of a semiconductor memory circuit according to a first embodiment of the present invention.

FIG. 2 is an internal waveform diagram of the embodiment of FIG.

FIG. 3 is a circuit diagram showing a data input circuit of a semiconductor memory circuit according to a second embodiment of the present invention.

4 is an internal waveform diagram of the embodiment of FIG.

FIG. 5 is a circuit diagram showing an example of a data input circuit of a conventional semiconductor memory circuit.

6 is a conventional internal waveform diagram of FIG.

FIG. 7 is a circuit diagram showing another conventional example.

8 is an internal waveform diagram of the conventional example of FIG.

FIG. 9 is a block diagram of a semiconductor memory circuit.

[Explanation of symbols]

1,9,11 NOR circuit 2,4 to 8,10,12,19,20 Inverter circuit 3 NAND circuit 13,14 Load capacitance 15 One-shot pulse generation circuit 16,17 P-channel MOS transistor 18 N-channel MOS transistor 21, 22 address buffer circuit 23 row decoder circuit 24 column decoder circuit 25 storage circuit 26 column / switch circuit 27 input data control circuit 28 output data control circuit

Claims (3)

[Claims] 1. A semiconductor comprising a first signal line for outputting an in-phase output signal made from a data input signal and a second signal line for outputting an opposite-phase output signal made from the data input signal. A data input circuit of a semiconductor memory circuit, further comprising means for bringing the first signal line and the second signal line close to the same potential in the data input circuit of the memory circuit. 2. In a data input circuit of a semiconductor memory circuit having a first signal line for outputting an in-phase output signal generated from a data input signal, the potential of the first signal line is set to the first and second potentials. A data input circuit for a semiconductor memory circuit, characterized in that means for setting an intermediate potential of a power supply is provided. 3. The method according to claim 1, wherein the means has a one-shot pulse generation circuit that triggers on a data input signal.
A data input circuit of the semiconductor memory circuit according to.