JPH06230082A - Lsi inspection device and lsi inspection method - Google Patents

Abstract

PURPOSE:To specify a failure position in a short time without requiring labor of an operator. CONSTITUTION:Counting registers 5a, 5b, 5c and 5FT are arranged in DC testing circuits 3a, 3b and 3c and a function testing circuit 4 possessed by a tester 1, and count the number when a result of a test program of a DUT11 is judged continuously as failuter, and by means of comparators 7a, 7b, 7c and 7FT, it is compared with the number when the testing circuits 3a, 3b, 3c and 4 preset in registers 6a, 6b, 6c and 6FT for a reference value are estimated in failure, and a diagnosing program is carried out on the testing circuits 3a, 3b, 3c and 4 whose numbers coincide with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI inspection device and an LSI inspection method having a plurality of test circuits for testing a semiconductor device.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional LSI inspection apparatus. As shown in FIG. 3, a conventional LSI inspection apparatus (hereinafter, referred to as “tester”) 1 includes an LSI to be inspected (hereinafter, “D”).
UT ". ) 11 to the pin electronics 2 that directly transfers signals between the tester 1 and the tester 1, a DC test circuit 3 that measures and determines the electrical characteristics of the LSI and a function test circuit 4 that tests the logical function of the LSI.
And various test circuits are connected, and a tester controller 8 including a CPU for controlling the tester 1 and a memory (not shown) is connected via a data bus 9 for exchanging data. It is composed. In the tester 1, in order to determine whether or not the various test circuits are operating normally, a diagnostic program for diagnosing the tester 1 itself is executed to check whether the test circuit is good or bad.

In many cases, the above-mentioned diagnostic program is composed of a dozen to several tens of independently executable programs corresponding to various test circuits provided in the tester 1, and is usually scheduled by an operator. Or all the test circuits provided in the tester 1 are executed on a non-periodical basis according to the operator's judgment.

When executing a diagnostic program for a specific circuit, it is assumed by the operator which test circuit is defective, and a diagnostic program for each test circuit is selected and executed. Also, tester 1
When the operating temperature range set by the temperature detection function provided inside is exceeded, the diagnostic program is automatically executed by the program of the tester 1.

[0005]

However, as described above, it takes a very long time to execute the diagnostic program for all the test circuits, and it is rare that a failure occurs in all the test circuits. Usually 1-2
Since it is almost the case that there are only a few failures, the time is wasted except when the diagnostic program is executed for these failed test circuits.

Further, it is possible to reduce the wasteful time for executing the diagnostic program for a normal test circuit by executing the diagnostic program for a specific test circuit at the operator's discretion. Experience with various tests and tester knowledge is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a tester and an LSI inspection method which can end a diagnostic program required for a test circuit in a short time without requiring labor by an operator.

[0008]

According to an LSI inspection method of the present invention as set forth in claim 1, in an LSI inspection device having a plurality of semiconductor device test circuits, a test result of the semiconductor device is obtained for each test circuit. If it is determined that the semiconductor device is defective, the count operation is performed, and if the test result of the semiconductor device is determined to be good, the first data holding unit that performs the clear operation and the predetermined value are set. Second
It is characterized by comprising data holding means and comparing means for comparing the data value of the data holding means of the first data holding means with the data value of the second data holding means.

An LSI inspection method of the present invention according to claim 2 uses the LSI inspection device according to claim 1,
When the test results of the plurality of semiconductor devices are consecutively determined to be defective, the first data holding unit holds the data value of the number of times judged to be defective, and the data value is held in the second data holding unit. When the two data values match, a diagnosis is made only to the test circuit corresponding to the first data holding means holding the data value. The program is executed, the test of the semiconductor device is continued when the result of the diagnostic program is good, and the test of the semiconductor device by the LSI inspection device is ended when the result of the diagnostic program is bad. It is characterized by that.

[0010]

By using the above-described present invention, it is possible to specify a test circuit in which the test result for the LSI has continuously failed more than the number of times when it is estimated that the test circuit has a failure. It is possible to execute the corresponding test circuit diagnostic program.

[0011]

The present invention will be described in detail below based on an example.

FIG. 1 illustrates three DCs according to one embodiment of the present invention.
FIG. 2 is a configuration diagram of an LSI inspection device having a test circuit and one function test circuit, and FIG. 2 is an LSI inspection process diagram using the LSI inspection device. In FIG. 1, a pin electronics 2 for directly passing signals between an LSI to be inspected (hereinafter referred to as “DUT”) 11 and a tester 1.
DC test circuit (hereinafter "DCT circuit") connected to
Say. ) 3 _a, 3 _b, 3 _c and function test circuit (hereinafter referred to as "FT circuit".) 4 associated with the one-to-one basis, by using the DCT circuit 3 _a, 3 _b, 3 _c and FT circuit 4 As a result of testing the DUT11, the DUT11 was continuously
“Counting registers” 5 _a , 5 _b , 5 _c, and 5 _FT for counting the number of times that is determined to be defective are provided via the data bus 9. Counting registers _5a , _5b , _5c
And 5 _FT are cleared (set to 0) by the tester controller 8 when the tester 1 is reset and when the test result is judged to be good, and when it is judged to be bad, Similarly, the tester controller 8 causes the DCT circuit 3 _a related to the defective test content,
3 _b, 3 values of _c and count register 5a corresponding to the FT circuit 4, 5 _b, 5 _c and 5 _FT is incremented by 1. Also,
The count register 5 _a, 5 _b, 5 _c and 5 counted value in _FT, corresponding DCT circuit 3 _a, 3 _b, 3 _c
And the values of the reference value registers 6 _a , 6 _b , 6 _c and 6 _FT that hold the reference values for estimating that the FT circuit 4 is out of order are the count registers 5 _a , 5 _b , 5 _c and 5 _{The FT} value is compared with the comparators 7 _a , 7 _b , 7 _c and 7 _FT . If they match, “1” is output, and if they do not match, “0” is output via the data bus 9. Can be read by the tester controller 8. The numeral 10 indicates a numerical value setting switch.

Next, an LSI inspection process using the LSI inspection apparatus 1 according to the present invention will be described with reference to FIGS. 1 and 2. First, when the tester 1 is activated, a monitor unit for controlling the entire tester 1 and inputting / outputting data by a keyboard or a CRT is activated (automatic activation by a boot ROM or the like). After that, in m1, the CRT display and keyboard input are performed in order to set the processing contents or various initial data settings, and the test preparation of the LSI is started.

Next, in m2, the reference value register 6
DC for _a , 6 _b , 6 _c and 6 _FT individually or collectively
A value serving as a reference for estimating the failure of the T circuits _3a , _3b , _3c and the FT circuit 4 is set. In addition, the numerical setting switch 10
When setting in hardware, such as using
Read the value by the tester controller 8, the reference value register 6 _a, it is set to 6 _b, 6 _c and 6 _FT. When the above process is completed, the test program of the LSI is activated in m3, and the monitor unit is put in the standby state in the next m4.

Next, at t1, the activated LSI test program directs DC to one DUT 11.
The test # 1 is executed, and the result of the DC test # 1 is determined at T2. The result of DC test # 1 is good (PAS
In the case of S), the following DC test # 2 is executed on the DUT 11 at t3. In addition, defective (FAI
L), in tf1, DCT circuit used in DC test _{# 1 3 a, 3 b,} 3 Count register 5 corresponds to the _{c a,} 5 _b, 5 a value of _c +1 is increased. At this time, the comparators 7 _a , 7 _b , and 7 _c automatically perform comparison processing with the values of the reference value registers 6 _a , 6 _b , and 6 _c , and m5
In reads the value of the comparator _{7 a, 7 b, 7 c} "1"
Is detected. Bad test result (F
If it becomes AIL), at tf, the subsequent test program is terminated, and the monitor unit is restarted and terminated. When the detection result in m5 is “0”, the LSI test program is executed again with another DU.
Execute for T11. Wherein step is carried out continuously a predetermined number of times, the detection result is "1" and since the comparator 7 _a in m5, 7 _b, 7 DCT circuit corresponding to _c 3 _a, 3 _b,
Start the diagnostic program suitable for 3 _c, again, the monitor enters a standby state.

Next, at m9, according to the execution result of the diagnostic program, the DCT in which the diagnostic program is executed is executed.
When the circuits 3 _a , 3 _b , and 3 _c are determined to be defective, CR is performed at m10 to prompt the operator to repair the tester 1.
"FAIL" is displayed on T, and processing such as stopping all tester functions is performed. However, the processing content after the defect determination is set by a program of an arbitrary monitor.

If the test circuit is determined to be good as a result of the diagnostic program, it is estimated that the DUT 11 on which the test program was executed in the above step was defective, and therefore the LSI test is continued. Therefore, m3
Return to the LSI test program to another DUT11
Run against. Hereafter, the same process is performed in DC test # 2
~ #N and function test (t5).

It should be noted that at tp, all one DUT
If the LSI test result for 11 is good (PASS), the counting registers 5 _a , 5 _b , 5 _c and 5 _FT
Is cleared (set to 0), and the test program is executed on another DUT 11 via m4, m5, and m3.

In the above embodiment, the reference value register 7
_a , 7 _b , 7 _c and 7 _FT are DCT circuits 3 _a , 3 _b , 3 _c and F
Although the reference value register is provided corresponding to the T circuit 4, it is not necessary to provide one reference value register for the test circuit, and only one reference value register may be provided.

[0020]

As described above in detail, by using the present invention, the diagnostic program for the test circuit is executed without requiring the operator's trouble and logically estimating the failure location. Therefore, it is possible to effectively identify the failure location in a very short time.

Further, since the test circuit can be automatically diagnosed whenever an abnormality occurs, the reliability of the LSI inspection apparatus is also improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an LSI inspection apparatus according to an embodiment of the present invention.

FIG. 2 is an inspection process diagram using the same LSI inspection apparatus.

FIG. 3 is a configuration diagram of a conventional LSI inspection device.

[Explanation of symbols]

1 LSI inspection apparatus 2 pin electronics _{3 a, 3 b, 3 c} DC test circuit 4 _a, 4 _b, 4 _c function test circuit _{5 a, 5 b, 5 c} , 5 FT count register 6 _a, 6 _b, 6 _c , 6 _FT reference value register 7 _a , 7 _b , 7 _c , 7 _FT comparator 8 tester controller 9 data bus 10 numerical setting switch 11 LSI under test

Claims (2)

[Claims] 1. An LSI inspection device having a plurality of semiconductor device test circuits, wherein a count operation is performed for each of the test circuits when a test result of the semiconductor device is determined to be defective.
When the test result of the semiconductor device is determined to be good, a first data holding unit for performing a clear operation, a second data holding unit with a predetermined value set, and a data value of the first data holding unit And an comparing unit for comparing the data value of the second data holding unit with each other. 2. When the LSI device according to claim 1 is used and the test results of the plurality of semiconductor devices are determined to be consecutively defective, the first data holding unit is provided with the number of times of failure. The data value held in the second data holding means is compared with the data value held in the second data holding means, and the two data values are held when the two data values match. A diagnostic program is executed for the test circuit corresponding to the first data holding means, and if the result of the diagnostic program is good, the test of the semiconductor device is continued and the result of the diagnostic program is defective. The LSI inspection method is characterized by terminating the test of the semiconductor device by the LSI inspection device.