JPH06226618A - Semiconductor wafer polishing method - Google Patents

Abstract

PURPOSE:To prevent trouble such as chipping of a semiconductor wafer held by a carrier between upper and lower disks when polished on both sides by holding the wafer in a hole in the carrier, together with the second annular carrier. CONSTITUTION:Semiconductor wafers 3 held in holes 7A... in a carrier 7 are laid between upper and lower disks 1, 2 mutually reverse-turned. The carrier 7 is autorotated and revolved in accordance with a difference in rotating number between a sun vehicle 5 and an internal gear 6, and the wafers 3 are autorotated in the holes 7A to be polished on both sides. In such a polishing method, each wafer 3 is borne by the second annular carrier 8 and stored in the hole 7A in the carrier 7. The annular carrier 8 is thus functioned as a shock absorber during the autorotation of the wafer 3 to absorb shock applied from the hole 7A in the carrier 7 to the wafer 3 so that the wafer 3 is prevented from chipping when polished.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for polishing a semiconductor wafer.

[0002]

2. Description of the Related Art Semiconductor wafers for integrated circuits are required to have even higher wafer flatness as the degree of integration increases. A double-sided polishing method as shown in FIG. 2 is widely adopted for manufacturing a high flatness wafer.

That is, as shown in FIG.
A wafer 3 and a carrier 4 for holding the wafer 3 are interposed between the upper and lower platens 1 and 2. The carrier 4 is shown in FIG.
As shown in, the plate is provided with a plurality of holes 4A for accommodating wafers.

The upper and lower platens 1 and 2 rotate in opposite directions, both surfaces of the wafer 3 come into surface contact with the upper and lower platens 1 and 2, and the carrier 4 is caused by the difference in the rotational speeds of the sun wheel 5 and the internal gear 6. Revolve around the earth. Further, the wafer 3 is rotating in the carrier 4. These rotation ratios are set to appropriate values, and the wafer is polished flat by this planetary operation. Above all, it is considered that the rotation of the wafer 3 in the carrier 4 is particularly important, and a clearance of 0.5 to 1 mm is usually provided between the outer diameter of the wafer 3 and the inner diameter of the hole of the carrier 4 to increase the degree of freedom of rotation of the wafer. Has been.

Examples of this type of polishing technique include those disclosed in JP-A-1-257564, JP-A-1-271170, JP-A-3-196965, and JP-A-3-47754.

[0006]

Although the polishing technique of FIG. 2 as described above can achieve high flatness, it has the following problems.

That is, when the object to be processed is a compound semiconductor, the compound semiconductor has a characteristic that the mechanical strength is weak. Therefore, when the wafer rotates in the carrier during polishing, the edge surface of the wafer is the carrier of the carrier. The wafer is likely to be chipped or chipped due to collision with the inner surface of the wafer storage hole. This phenomenon is more prominent in double-sided polishing in which the frictional force between the surface plate and the wafer is large.

It is an object of the present invention to solve the above-mentioned problems of the prior art and to provide a method for polishing a semiconductor wafer which is free from chipping and chipping while maintaining high flatness.

[0009]

SUMMARY OF THE INVENTION The gist of the present invention is to set a carrier between an upper and a lower platen and a semiconductor wafer housed in a hole provided in the carrier, and rotate the upper and lower platens to cause the semiconductor wafer to rotate. In the method for polishing both sides of the semiconductor wafer, the semiconductor wafer is housed together with the second carrier in a state where the semiconductor wafer is fitted in the hole of the carrier into the inner diameter of the annular second carrier, and both sides of the semiconductor wafer are polished. It is in.

[0010]

According to the wafer polishing method having the above-described structure, the semiconductor wafer is housed in the hole of the original carrier in a protected state by being fitted into the inner diameter of the second carrier (annular carrier) during polishing. When the wafer rotates in the hole, the annular carrier serves as a buffer to reduce the impact force of the carrier applied to the wafer from the hole. as a result,
It is possible to prevent the occurrence of chipping and chipping of the wafer during double-side polishing of the wafer.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG.

FIG. 1A is a schematic side sectional view showing an example of an apparatus for use in the double-sided polishing method of the present invention, and FIG. 1B is a plan view of a carrier according to the present embodiment. The same reference numerals as those in the above-described conventional example indicate the same or common elements.

That is, 1 and 2 are upper and lower platens, 3 is a wafer, 5 is a sun wheel, and 6 is an internal gear. In this embodiment, instead of the carrier 4 described in the conventional example, a carrier 7 and a second carrier are provided. The carrier 8 is used.

A plurality of holes 7A are provided in the carrier 7 in the circumferential direction, and the second carrier 8 has an annular shape (for example, a donut shape) along the outer diameter of the semiconductor wafer 3, and the inner diameter of the annular carrier 8 is large. The wafer 3 is fitted in the wafer 7, and the wafer 3 and the annular carrier 8 are housed in the hole 7 A of the carrier 7.

In this state, the wafer 3 is set so as to be interposed between the upper and lower platens 1 and 2 in a surface contact state, the upper and lower platens 1 and 2 rotate in opposite directions to each other, and the carrier 7 is connected to the sun wheel 5. Both sides of the wafer 3 are polished by the rotation of the internal gear 6 and the rotation of the second carrier 8 and the wafer 3 in the hole 7A.

For example, the semiconductor wafer 3 has a diameter of 100 m.
The device used was a so-called 12B type (surface plate diameter φ863 mm, carrier diameter φ28).
3.6 mm). The second annular carrier 8 has an inner diameter φ
100.1 mm, outer diameter φ120 mm, and the hole diameter of the carrier hole 7A is φ121 mm.

Here, the semiconductor wafer 3 is sliced in advance from a single crystal ingot to a thickness of 800 μm and chamfered,
The double-side lapping up to 700 μm was subjected to double-side polishing using the above-mentioned polishing apparatus.

As a result of performing double-side polishing on the wafer 3 by this method, chipping and chipping of the wafer could be reduced from 5% to 2% as compared with the conventional polishing method. Further, the flatness achieved TTV ≦ 2 μm, which is the same level as the conventional one.

The annular carrier (second carrier) 8
Difference between the inner diameter of the wafer 3 and the outer diameter of the wafer 3 smaller than this inner diameter is +
If it is 0.1 mm or less, the difference between the inner diameter of the hole 7A of the carrier 7 and the outer diameter of the annular carrier 8 smaller than this inner diameter is +0.5 to
When it was 1 mm or less, particularly good polishing results were obtained.

[0020]

According to the double-sided polishing method of the present invention, it is possible to significantly reduce the occurrence of chipping and chipping while ensuring high-flatness double-sided polishing of semiconductor wafers.

[Brief description of drawings]

FIG. 1 is a schematic side sectional view and a plan view of a wafer double-side polishing apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic side sectional view and a plan view showing an example of a conventional wafer double-side polishing apparatus.

[Explanation of symbols]

 1 Upper surface plate 2 Lower surface plate 3 Semiconductor wafer 5 Sun wheel 6 Internal gear 7 Carrier 7A Carrier hole 8 Second carrier (annular carrier)

Claims (2)

[Claims] 1. A method of setting a carrier between upper and lower platens and a semiconductor wafer housed in a hole provided in the carrier, and polishing both surfaces of the semiconductor wafer by rotating the upper and lower platens. A method of polishing a semiconductor wafer, wherein the semiconductor wafer is housed together with the second carrier in a state where the semiconductor wafer is fitted in the inner diameter of an annular second carrier, and both sides of the semiconductor wafer are polished. 2. The method according to claim 1, wherein the difference between the inner diameter of the annular carrier (second carrier) and the outer diameter of the semiconductor wafer smaller than this inner diameter is +0.1 mm or less, and the inner diameter of the hole of the carrier and this A method for polishing a semiconductor wafer, wherein a difference between the outer diameter of the annular carrier having an inner diameter smaller than +0.5 to 1 mm is set.