JPH06225281A - Television signal high efficiency encoder and its decoder - Google Patents

Abstract

PURPOSE:To compress the data quantity of picture data by removing the redundancy of a level direction by watching the local correlation of a picture. CONSTITUTION:One field of a digital television signal is divided into the blocks of (6 picture elements X 3 lines). The maximum value MAX and the minimum value MIN of each block is detected. A subtraction circuit 49 forms a dynamic range DR which is the difference of the maximum value and the minimum value. A subtraction circuit 50 forms difference data DTI of each picture element data and the minimum value MIN in the block. The dynamic range DR and the piece of data DTI are provided for an endoder 5 to be encoded by a variable quantization bit number corresponding to the size of the dynamic range DR so as to generate an encoding code signal DT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coding apparatus and a decoding apparatus for processing digital television signals, for example, in a field.

[0002]

2. Description of the Related Art As a method of encoding a television signal by in-field processing, there are known some methods for reducing the average number of bits per pixel or the sampling frequency for the purpose of narrowing the transmission band. .

As an encoding method for lowering the sampling frequency, the image data is thinned to 1/2 by sub-sampling, and the positional relationship between the sub-sampling points and the sub-sampling points used at the time of interpolation is shown (that is, above or below the interpolation points It is proposed to transmit a flag indicating which of left and right sub-sampling data is used).

As one of the encoding methods for reducing the average number of bits per pixel, DPCM (differential PC)
M) is known. DPCM quantizes and transmits this difference signal, paying attention to the fact that the correlation between adjacent pixels of a television signal is high and the difference between adjacent pixels is small.

As another encoding method for reducing the average number of bits per pixel, the screen of one field is subdivided into minute blocks, and the compressed encoding code and the level distribution of the data in the blocks are calculated. Some transmit mean and standard deviation.

[0006]

In the coding method that attempts to reduce the sampling frequency by using sub-sampling, the sampling frequency is halved, which may cause aliasing distortion. The DPCM has a problem that a coding error propagates to subsequent coding.

The method of encoding in block units has a drawback that block distortion occurs at boundaries between blocks.

An object of the present invention is to provide a high-efficiency coding apparatus for a television signal, which does not have the problems of the above-mentioned conventional techniques such as the generation of aliasing distortion, the propagation of errors, and the occurrence of block distortion. is there.

The present invention also relates to a high efficiency coding device having a variable number of quantization bits. The conventionally known variable-length coding has the drawback that it requires information on data delimiters, requires complicated control, and has a poor compression rate.

Therefore, another object of the present invention is to provide a high-efficiency coding apparatus for a television signal of a variable length coding system which has a small restoration error and a good compression rate.

[0011]

According to the present invention, a maximum value MAX of a plurality of pixel data and a minimum value of a plurality of pixel data included in a block formed by a plurality of pixels in at least one field of a digital television signal. Value MIN
And a means for detecting the dynamic range DR of the block from the maximum value MAX and the minimum value MIN,
Means for forming modified input data modified to have a relative level relationship based on a value defining the dynamic range DR, and a dynamic range DR defined by the number of quantization bits of a digital television signal.
The range of possible values is divided into a plurality of levels in the level direction, 0 or 1 bit is allocated to the range having the smallest dynamic range DR, and 1 is allocated to the remaining range in the direction in which the dynamic range DR increases. The number of bits that increases by each bit is assigned, and the number of bits assigned to the range to which the dynamic range DR of the detected block belongs is determined as the number of quantization bits for each block.
Encoding means for encoding the modified input data by the number of quantization bits, dynamic range DR information, and maximum value MA
A high-efficiency coding apparatus for a television signal, comprising: a transmission means for transmitting at least two of X and the minimum value MIN as an additional code together with an output signal of the coding means.

[0012]

Since the television signal has a correlation in the horizontal direction and the vertical direction, the level change range of the pixel data included in the same block is small in the stationary part. Therefore, if the data DTI is quantized by the value defining the dynamic range DR, for example, the number of quantization bits determined by the dynamic range DR of the data DTI after removing the minimum level shared by the pixel data in the block,
The number of quantization bits is reduced on average due to the correlation of pixels in the block, and the data transmission bandwidth can be made narrower than the original one. Even in the variable length coding method, by transmitting the additional code for each block, it is not necessary to insert a special code indicating the division of data, and the compression rate is improved and the control is simplified. be able to.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an encoder according to an embodiment of the present invention as a whole. For example, an NTSC digital television signal in which one sample is quantized into 8 bits is input to an input terminal indicated by 1. This digital television signal is supplied to the cascade connection of the line delay circuits 2 and 3 and the cascade connection of the five sample delay circuits 11 to 15.

A cascade connection of five sample delay circuits 21 to 25 is connected to the connection point of the line delay circuits 2 and 3.
The output terminal of the line delay circuit 3 is connected to a cascade connection of five sample delay circuits 31 to 35. Line delay circuits 2 and 3 having a delay amount of one line period and sample delay circuits 11 to 15, 21 to 25 and 3 having a delay amount equal to the sampling period of the input digital television signal.
1 to 35, it is possible to simultaneously obtain pixel data of one block from the output terminals of each delay circuit.

In FIG. 2, reference numeral 10 indicates one block, and the solid line indicates the nth consecutive current field,
The (n + 1) th and (n + 2) th lines are shown, and the broken lines show the lines of other fields. One block of (3 lines × 6 pixels) is configured by 6 pixels included in each of the 3 lines of the current field.
When the pixel data of the (n + 2) th line is supplied to the input terminal 1, the pixel data of the (n + 1) th line is generated at the output of the line delay circuit 2, and the pixel data of the nth line is generated at the output of the line delay circuit 3. Pixel data is produced. The six pixel data of each line are taken out respectively between the input terminal, the output terminal and each stage of the cascade connection of the sample delay circuit.

Six pieces of pixel data of the same line, which are taken out by the cascade connection of the sample delay circuits 11 to 15, are supplied to the selection circuits 16, 17 and 18 two by two. The 6 pieces of pixel data of the same line extracted by the cascade connection of the sample delay circuits 21 to 25 are selected by the selection circuits 26 and 2 two by two.
7 and 28. Six pieces of pixel data of the same line extracted by the cascade connection of the sample delay circuits 31 to 35 are supplied to the selection circuits 36, 37 and 38 in pairs. These selection circuits compare the levels of two input pixel data, output the pixel data of the higher level to one output terminal, and output the pixel data of the lower level to the other output terminal. It is a digital level comparison circuit configured as described above.

One output terminal of the selection circuits 16 and 17 is connected to the input terminal of the selection circuit 41, and the other output terminal of the selection circuits 16 and 17 is connected to the input terminal of the selection circuit 51. One output terminal of the selection circuits 18 and 26 is connected to the input terminal of the selection circuit 42, and the selection circuits 18 and 26 are connected.
The other output terminal of is connected to the input terminal of the selection circuit 52. One output terminal of the selection circuits 27 and 28 is connected to the input terminal of the selection circuit 43, and the other output terminal of the selection circuits 27 and 28 is connected to the input terminal of the selection circuit 53.
One output terminal of the selection circuits 36 and 37 is the selection circuit 44.
, And the other output terminals of the selection circuits 36 and 37 are connected to the input terminal of the selection circuit 54.

The selection circuits 41 to 44 are digital level comparison circuits configured to compare the levels of two input pixel data and selectively output only the pixel data of a higher level. The selection circuits 51 to 54 are
The digital level comparison circuit is configured to compare the levels of two input pixel data and selectively output only the pixel data of a smaller level.

The outputs of the selection circuits 41 and 42 are supplied to the selection circuit 45. Selection circuit 43 and selection circuit 4
4 outputs are supplied to the selection circuit 46. The outputs of the selection circuit 45 and the selection circuit 46 are supplied to the selection circuit 47. The output of the selection circuit 47 and the higher level output of the selection circuit 38 are supplied to the selection circuit 48. Selection circuit 45, 4
6, 47, and 48, like the selection circuits 41 to 44, selectively output pixel data of a higher level. Therefore, the block 1 is connected to the output terminal of the selection circuit 48.
Among the 18 pixel data in 0, the pixel data of the maximum level MAX occurs.

The outputs of the selection circuits 51 and 52 are supplied to the selection circuit 55. Selection circuit 53 and selection circuit 5
4 outputs are supplied to the selection circuit 56. The outputs of the selection circuits 55 and 56 are supplied to the selection circuit 57. The output of the selection circuit 57 and the smaller level output of the selection circuit 38 are supplied to the selection circuit 58. Selection circuits 55, 5
Similarly to the selection circuits 51 to 54, reference numerals 6, 57 and 58 are for selectively outputting pixel data of a smaller level. Therefore, the block 1 is connected to the output terminal of the selection circuit 58.
Among the 18 pixel data in 0, the pixel data of the minimum level MIN is generated.

The output of the selection circuit 48 and the output of the selection circuit 58 are supplied to the subtraction circuit 49. The subtraction circuit 49 performs an operation of (maximum level MAX-minimum level MIN), and an 8-bit dynamic range DR is obtained at the output terminal 6. The minimum level MIN is taken out to the output terminal 7 and supplied to the arithmetic circuit 50.

The subtraction circuit 50 includes a sample delay circuit 35.
The pixel data PD generated at the output of is supplied via the delay circuit 4. The delay circuit 4 has a delay amount equal to the delay caused by detecting the maximum level MAX and the minimum level MIN as described above. 8-bit pixel data DTI from which the minimum level has been removed is obtained at the output of the subtraction circuit 50.

The pixel data DTI after the dynamic range DR and the minimum level removal are supplied to the encoder block 5. The encoder block 5 determines the number of quantization bits according to the dynamic range DR, encodes the pixel data DTI after the minimum level removal by the determined number of quantization bits (1 bit to 8 bits), and encodes the pixel data DTI. The code DT is generated at the output terminal 8. The specific configuration of the encoder block 5 will be described later.

As described above, the dynamic range DR and the minimum level MIN as additional data are obtained at the output terminals 6 and 7 of the encoder shown in FIG. 1, and the encoded code is obtained at the output terminal 8. Although not shown, a buffer memory is connected to the output of the encoder, and the additional data DR, MIN and encoded code DT of one block are transmitted. The encoded code DT and the additional data DR and MIN are
The error correction code is encoded and transmitted as serial data (or recorded in a recording medium).

Of course, as a pre-process for the encoder, it is also effective to scan-convert line scan input data into block-end scan data before processing. At this time, the process for returning the block-unit scan data to the line scan data may be performed after the decoder.

Some examples of the form of transmission data are shown in FIG. In FIG. 3A, an independent error correction code is encoded in each of the data parts including the minimum level MIN, the dynamic range DR, and the encoded code, and the parity of each error correction code is added and transmitted. The length of the data portion composed of this encoded code DT is (m bits × 18) (m is the dynamic range D of the block).
It is the length of the quantization bit number determined by R). FIG. 3B shows
The minimum level MIN and the dynamic range DR are each encoded with an independent error correction code, and the parity of each error correction code is added. FIG. 3C shows that the error correction code common to both the minimum level MIN and the dynamic range DR is encoded and its parity is added.

As is apparent from FIG. 3, since the dynamic range information, that is, the dynamic range DR is inserted and transmitted for each block, it is not necessary to insert a special code indicating block division. .

As shown in FIG. 4, when the quantization bit number is 8 bits, the level of the television signal is (0 to 25).
There are 256 possible cases of 5). However, in the stationary part except the non-stationary part such as the contour of the object, the level distribution of the pixels in one block is concentrated in a fairly narrow level range as shown in FIG. Therefore, even if the number of quantization bits is variable from 1 to 8 bits, the number of quantization bits is 7 bits or less in most cases, and the average number of bits per pixel can be reduced.

The encoder block 5 described above includes a subtractor 4
An encoded code DT in which the number of quantization bits is varied from 1 bit to 8 bits is generated according to the dynamic range DR from 9.

FIG. 5 shows an example of the configuration of the encoder block 5. In FIG. 5, the 8-bit dynamic range DR is supplied to the priority encoder 63 from the input terminal 61. The DTI after removal of the 8-bit minimum level is supplied to the bit selection circuit 64 from the input terminal indicated by 62. The priority encoder 63 outputs 3-bit outputs C2, C1, C corresponding to the highest position where "1" is set among the 8-bit dynamic range DR.
Generates 0.

The highest position where "1" stands indicates the value of the dynamic range DR. For example, when the MSB (most significant bit) of the dynamic range DR is at the highest position where "1" is set, the dynamic range is (128 to 255) and the LSB (least significant bit) is set to "1". At the highest position, the dynamic range is (0 to 1).

The bit selection circuit 64 selects and outputs a predetermined number of bits from the LSB of the data DTI according to the outputs (C2, C1, C0) of the priority encoder 63. The 8 bits of data DTI are sequentially (X
7, X6, X5, X4, X3, X2, X1, X0), the output of the bit selection circuit 64 of 1 to 8 bits is generated as the encoded code DT as shown in the table below. Further, when all the data in the block is 0, if the coding code is given to the entire block and the coding code is not given to each pixel, further compression can be performed.

[0033]

[Table 1]

Since the correlation of pixels in one block is strong as described above, the dynamic range DR of each block is
It will be small in most cases. Therefore, the amount of transmission data can be reduced. Of course, without transmitting the 8-bit dynamic range DR itself, the 3-bit output of the priority encoder 63 (C2, C1, C0)
Is transmitted, an even higher compression rate can be realized.

The encoder block described above is a reversible coding system capable of making the restoration error zero. However, the configuration may be such that a visually undetectable error (for example, an error of up to 2 bits of the LSB and its upper bits) is allowed. That is, the lower 2 bits may be truncated to form an encoded code DT having a length of 6 bits or less. The relationship between the dynamic range DR and the encoded code DT in this case is as shown in the table below.

[0036]

[Table 2]

FIG. 6 shows another configuration of the encoder block 5. In the configuration shown in FIG. 6, the encoded code DT is 4
The compression ratio is suppressed to a bit or less to increase the compression rate.

Priority encoder 6 in FIG.
Similarly to the encoder block shown in FIG. 5, the 3 and bit selection circuit 64 generates an encoded code in which the number of quantization bits is changed according to the dynamic range DR. The 3-bit output of the priority encoder 63 is supplied to one input terminal of a digital comparison circuit 66. The 3-bit configuration (011) is supplied from the terminal 67 to the other input terminal of the comparison circuit 66. The output of the comparison circuit 66 controls the multiplexer 68. The encoded code DT is taken out to the output terminal 8 of the multiplexer 68.

The multiplexer 68 is supplied with the output of the bit selection circuit 64 and the output of the ROM 65 in which a data table for compressing the number of quantization bits is stored. The multiplexer 68 selects one input as the encoded code DT according to the output of the comparison circuit 66. That is, the output code (C
2, C1, C0) is (111) (110) (101)
In either case of (100), the output of the bit selection circuit 64 is selected by the multiplexer 68, and the output code of the priority encoder 63 is (011) (010).
In either case of (001) (000), the output of the ROM 65 is selected by the multiplexer 68.

The ROM 65 evenly divides the dynamic range DR into (2 ⁴ = 16) level ranges, determines which level range the data DTI is included in, and a 4-bit code corresponding to the level range. Is to be read.

The encoding operation of the ROM 65 will be described. However, for simplification of description, the number of quantization bits is not 4 bits but 2 bits, and the dynamic range is divided into 4.

The pixel data PD including the minimum level in one block belongs to the dynamic range DR from the minimum level MIN to the maximum level MAX as shown in FIG. The ROM 65 stores the data DT after the minimum level is removed.
A 2-bit encoded code is output according to which level range I divides the dynamic range DR into four.

The ROM 65 divides the dynamic range into equal parts according to the number of quantization bits, and the median values L0 and L of the respective areas are divided.
1, L2, L3 are used as the values at the time of decoding. This encoding method can reduce quantization distortion. On the other hand, pixel data having the minimum level MIN and the maximum level MAX always exist in one block. Therefore, in order to increase the number of coded codes having an error of 0, the dynamic range DR is divided into (2 ^m −1) (where m is the number of quantization bits) as shown in FIG.
N may be the representative level L0 and the maximum level MAX may be the representative level L3.

The output of the bit selection circuit 64 is a reversible coding system capable of making the restoration error zero. The output of the ROM 65 is an irreversible encoding output. However, the quantizing distortion is 4 when the dynamic range DR is 128, which is almost no problem from the viewpoint of vision. Instead of the ROM 65, a configuration using a level comparison circuit or a configuration using a divider is also possible.

As described above, in the configuration for decoding encoded data, the dynamic range DR is identified by the dynamic range information, that is, the 3-bit output of the priority encoder 63, and this identification corresponds to the bit selection circuit 64. And the decoder corresponding to the ROM 65 is switched.

In the above description, the encoded code DT, the information of the dynamic range DR, and the minimum level MIN are transmitted. However, the minimum level MIN and the maximum level MAX may be transmitted as the additional code, or the information of the dynamic range DR and the maximum level MAX.
May be transmitted.

Furthermore, the present invention can be applied to the case where the block is one-dimensional. As shown in FIG. 10, for example, 16 consecutive pixels on the same line may be set as one block. An encoder for a one-dimensional block will be described with reference to FIG.

In FIG. 9, reference numeral 71 denotes an input terminal to which a digital television signal is input in 8-bit parallel. The input digital television signal is input to the delay circuit 7
3 is supplied to the subtraction circuit 74.

Reference numeral 72 denotes an input terminal to which a sampling clock synchronized with the input digital television signal is supplied. This sampling clock is supplied to the counter 79 and the registers 80 and 81 as clock pulses. The counter 79 is a hexadecimal counter, and a block clock is generated at its output for every 16 pixel data. This block clock is supplied to the registers 80 and 81 as a pulse for initial setting. Further, it is supplied to the latches 85 and 86 as a latch pulse.

The registers 80 and 81 can input and output 8-bit parallel data. The output data of one register 80 is supplied to one input terminal of the selection circuit 82, and the output data of the other register 81 is supplied to one input terminal of the selection circuit 83. An input digital television signal is supplied to the other input terminals of the selection circuits 82 and 83.

The selection circuit 82 is the structure of a digital level comparison circuit for selecting and outputting a higher level one of the two input data. The selection circuit 83 has a configuration of a digital level comparison circuit for selecting and outputting one of the two input data having a smaller level. Selection circuit 8
The output data of 2 is supplied to one input terminal of the subtraction circuit 84 and is also supplied to the input terminal of the register 80.
The output data of the selection circuit 83 is supplied to the other input terminal of the subtraction circuit 84 and the input terminal of the register 81.

In this example, one block is composed of 16 continuous pixel data on the same line, as shown in FIG. The block clock from the counter 79 is generated at the beginning of each block, and the registers 80 and 81 are generated.
The initial settings for are made. The register 80 is loaded with a code of all "0" bits as an initial value, and the register 81 is loaded with a code of all "1" bits as an initial value.

The pixel data at the head of one block is selected by the selection circuits 82 and 83 and stored in the registers 80 and 81. Next pixel data and registers 80 and 81
Is compared with the pixel data stored in, the data of the higher level of both is output from the selection circuit 82, and the data of the lower level of the both is output from the selection circuit 83. . Thereafter, the levels are sequentially compared in one block, and the one having the highest level among the 16 pixel data is taken out to the output terminal of the selection circuit 82 and set to 1
The minimum level of the 6 pixel data is the selection circuit 8
3 is taken out to the output terminal.

In the subtraction circuit 84, (maximum level-minimum level) is calculated, and the dynamic range of the block is detected at the output terminal of the subtraction circuit 84. The dynamic range DR output from the subtraction circuit 84 is the latch 8
The minimum level MIN which is stored in 5 and is output from the selection circuit 83 is stored in the latch 86. The dynamic range DR stored in the latch 85 is the encoder block 75.
Is supplied to. Minimum level MI stored in latch 86
It is taken out to the output terminal 77 of N and the subtraction circuit 74
Is supplied to the other input terminal.

The subtraction circuit 74 is supplied with the pixel data PD whose timing is adjusted by the delay circuit 73. Therefore, the data DTI from which the minimum level MIN is removed is generated at the output terminal of the subtraction circuit 74. This data DTI is supplied to the encoder block 75. The encoder block 75 has the same configuration as the encoder block 5 described above. The dynamic range DR and the variable-length encoded code DT are taken out from the output terminals 76 and 78 of the encoder block, respectively.

[0056]

According to the present invention, the amount of data to be transmitted can be reduced and the transmission band can be narrowed by utilizing the correlation of pixels in a block. Further, according to the present invention, since the number of quantization bits is adaptively determined by the dynamic range, a uniform image with good distortion can be obtained. Further, according to the present invention, since the data delimiter can be identified by the additional code, a special code indicating the data delimiter is not necessary despite the variable length, which improves the compression rate and improves the encoder and decoder configurations. It is possible to simplify.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a schematic diagram used to describe a block that is a unit of encoding processing.

FIG. 3 is a schematic diagram used to describe a plurality of examples of the structure of transmission data.

FIG. 4 is a schematic diagram used for explaining a level distribution of pixel data in one block.

FIG. 5 is a block diagram of an example of an encoder block.

FIG. 6 is a block diagram of another example of an encoder block.

FIG. 7 is a block diagram for explaining an encoding method of an encoder block.

FIG. 8 is a schematic diagram for explaining another encoding method of the encoder block.

FIG. 9 is a block diagram of another example of an encoder to which the present invention can be applied.

FIG. 10 is a schematic diagram for explaining another example of the encoder to which the present invention can be applied.

[Explanation of symbols]

1 Digital Television Signal Input Terminals 2, 3 Line Delay Circuit 5 Encoder Block 6 Dynamic Range DR Output Terminal 7 Minimum Level MIN Output Terminal 8 Encoding Code DT Output Terminal 10 Blocks 11-15, 21-25, 31 ~ 35 sample delay circuit

Claims (2)

[Claims] 1. A means for detecting a maximum value of a plurality of pixel data and a minimum value of the plurality of pixel data included in a block composed of a plurality of pixels in at least one field of a digital television signal, Means for detecting the dynamic range of the block from the maximum value and the minimum value, and means for forming modified input data modified to have a relative level relationship based on a value defining the dynamic range, The range of possible values of the dynamic range defined by the number of quantization bits of the digital television signal is divided into a plurality of levels in the level direction, and 0 or 1 bit is assigned to the range having the smallest dynamic range, For the remaining range, increase by 1 bit in the direction of increasing the dynamic range. The number of bits to be assigned to the range to which the dynamic range of the detected block belongs is determined as the number of quantization bits for each block, and the modified input data is encoded by the number of quantization bits. And a transmission means for transmitting at least two of the dynamic range information, the maximum value and the minimum value as an additional code together with the output signal of the encoding means. High-efficiency encoder for television signals. 2. A maximum value and a minimum value of a plurality of pixel data included in a block formed of a plurality of pixels in at least one field of a digital television signal, and at least information of dynamic range of the block. The range of possible values of the dynamic range defined by the two additional codes and the number of quantization bits of the digital television signal is divided into a plurality of values in the level direction, and the range with the smallest dynamic range is 0. Alternatively, 1 bit is allocated, and to the remaining range, the number of bits that increases by 1 bit in the direction of increasing the dynamic range is allocated, and the number of bits allocated to the range to which the dynamic range of the block belongs is Determined as the number of quantization bits for each block, and Less than the original number of quantized bits obtained by encoding the modified input data obtained by modifying the plurality of pixel data with the quantized bit number so as to have a relative level relationship based on the dynamic range. In a high-efficiency code decoding device that transmits a coded code signal having a number of bits, in order to convert the coded code signal into a representative level from the dynamic range indicated by the additional code and the number of quantized bits for each block. And a conversion means that is coupled to the conversion means and forms a restoration level based on the reference pixel data.