JPH0622355B2 - Line setting circuit - Google Patents

Description

The present invention relates to a line setting circuit of a synchronous multiplex converter in a digital transmission line network.

(Prior Art) Conventionally, as a technology in such a field, "Transmission Facility Design of Digital Network" by Teranishi et al. (Telecommunication Association, P18)
1-188,) and Nakahama et al., "Out-of-town digital sync terminal system" (Nippon Telegraph and Telephone Public Corporation, Facility Bureau, "Facilities", Vol. 33, No. 11)
No., P95-106). Less than,
The explanation will be given according to these.

In the digital transmission line network, it becomes possible to set the line in time by replacing the time slot on the digital multiplex level, instead of the spatial line setting by the distribution rack which has been conventionally performed in the analog transmission line network. The synchronous multiplex conversion device as disclosed in the above document is put to practical use.

Synchronous multiplex converter is 1.544Mb / s or 6.312Mb / s
The s digital transmission line is terminated, the line is set in units of 6 channels (line setting unit), the line is terminated in the same unit, and it is connected to the digital exchange by the 8.192 Mb / s or 2.048 Mb / s intra-station interface. It The line setting function of the synchronous multiplex converter uses a line setting circuit (T
It is realized by SI (Time Slot Interchanger), and the semi-fixed time switch is realized by having a configuration in which this time slot interchange order can be controlled from the outside.

The digital transmission path accommodated by the synchronous multiplex converter is 1.54
4Mb / s primary group transmission line and 6.312Mb / s secondary group transmission line, and the channel capacity of each transmission line interface is
There are 24 and 96 channels, respectively, when converted to 64 Kb / s telephone channels. On the other hand, the interface with the exchange is performed by the intra-station interface of 2.048 Mb / s or 8.192 Mb / s, and the channel capacity of each intra-station interface is 30 channels and 120 channels, respectively.

Depending on the transmission line and the interface conditions in the station, in the synchronous multiplex converter, in addition to the above-mentioned transmission line termination function, line setting function, line termination function, and in-station interface function, conversion of the signal speed and channel capacity of each interface is required. A multiple conversion function is required.

Next, the configuration of a circuit that implements line setting and multiplex conversion in the synchronous multiplex converter will be described. After that, in order to prevent the explanation from becoming complicated, the transmission line interface is set to 6.31.
Although the 2Mb / s secondary group interface and the intra-station interface are limited to 8.192Mb / s intra-station interface, the present invention can be applied in the same manner when other transmission line interfaces and intra-station interfaces are accommodated. Needless to say.

FIG. 2 is a block diagram showing an example of the configuration of the line setting and multiplex conversion function units of the synchronous multiplex conversion device.
A circuit for performing line setting in the station direction (R direction) is shown. In FIG. 2, INi (i = 1 to 40) is 6.31 respectively.
Received from the 2Mb / s secondary group transmission line interface,
This is an input signal (line) consisting of a 96-channel multiplex signal whose speed has been converted to 8.192 Mb / s. In addition, OUTi (i =
1 to 32) are output signals consisting of 120-channel multiplexed signals each having a signal rate of 8.192 Mb / s, and are sent to the intra-station interface. The line setting function unit shown in FIG. 2 has 96 channels of input signal INi (i = 1 to 40) × 40.
Book, total 3840 channels (= 640 handling groups:
HG) signals are first multiplex-converted into 120 channels x 32 lines, and then these signals are subjected to line setting by time slot replacement to output 120 channel multiplex signals x 32 lines (line ) OUTi (i = 1 to 32)
As.

The details will be described below with reference to FIG.

In FIG. 2, 1 to 8 are sent from the transmission line side 5
A multiplex conversion circuit that converts a 96-channel multiplex signal (line) into four 120-channel multiplex signals (line)
It is called a 5/4 conversion circuit. ). With these 5/4 conversion circuits 1-8, 40 96 circuits sent from the transmission line side
Input signal INi (i = 1 to 4) composed of channel multiplexed signals
0) is multiplexed and converted into a signal composed of 32 120-channel multiplexed signals. 9 is a line setting circuit (TSI), and 5 /
For the 120 120-channel multiplexed signals converted by the 4 conversion circuits 1 to 8, the line is set by replacing the time slot for each HG (6 channels), and the output signal OUT
A 120-channel multiplexed signal is transmitted to each of i (i = 1 to 32).

In the above description, the multiplexing conversion from the transmission line to the in-station direction (R direction) and the line setting are described, but the configuration from the in-station to the transmission line direction (S direction) is completely the same as the R direction, that is, 4/5. It is realized by a conversion circuit and a line setting circuit.

The line setting circuit 9 has a function of changing the temporal order of input data and outputting the data, so that some memory function is required. The basic structure is shown in FIG. In FIG. 3, 10 is a data memory and 11 is a data memory 10.
, 12 is an address counter, 13 is a write address, 14 is an address control memory, 15 is a read address, and 16 is an output of the data memory 10. The data IN arriving at the input 11 of the data memory 10 is sequentially (sequentially) supplied to the data memory 10 according to the write address 13 output from the address counter 12.
Written in. The write address 13 is also given to the address control memory 14 at the same time, and the address control memory 14 gives to the data memory 10 the read address 15 previously written corresponding to the given address 13. The data memory 10 reads the data at the output 16 according to the read address 15 and sets it as the data OUT. That is, the phase conversion information between the input and output of the data memory 10 is stored in the address control memory 14, and the order of reading data from the data memory 10 is random according to this phase conversion information.

FIG. 4 shows a conventional line setting circuit, and the line setting capacity of this circuit is 3840 channels. Input signal (line)
IN1 to IN4 are 8 Mb / s octet parallel signals each having a capacity of 960 channels (8 Mb / s serial signals after 5/4 conversion are serial-parallel converted), and are multiplexed by the multiplexing unit (MUX) 18. 32 Mb / s
It becomes an octet parallel signal. This signal is sequentially written in the data memory unit (DM) 19, the channel arrangement is changed by the address control memory (ACM) 20 and read out, and four 8Mb / s octet parallel signals are separated by the separation unit (DEMUX) 21. The output signals (lines) OUT1 to 4 are separated. Therefore, the data memory unit (DM) 1 that stores all input information of 3840 channels
The function of 9 is very important. Normally, the N (normal) system memory unit 19-1 and the E (emergency) system memory unit 19-
2 systems of 2 are prepared, and when some trouble such as parity abnormality occurs in the data memory unit during N system operation, E
Switch to the system side to improve the reliability of the device.

(Problems to be Solved by the Invention) However, in the device having the above configuration, the data memory unit has a fast operation speed, for example, ECL with large power consumption.
It has to be composed of a memory, and also an external circuit has to use an ECL circuit. Further, since the N-type and E-type data memory units having the same channel capacity are provided as a redundant configuration, the amount of hardware is doubled, which is uneconomical. Furthermore, there is a problem in that the increase in hardware and the decrease in reliability cannot be avoided because the multiplexing unit and the separation unit are provided outside the data memory unit.

The present invention eliminates the above-mentioned problems such as the need for a high-speed memory, the increase in hardware due to the N system and the E system, the increase in the hardware of the external circuit, and the use of a general-purpose CMOS memory. It is an object of the present invention to provide a highly reliable line setting circuit with low power consumption that can reduce the amount of hardware.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention has m multiplexed inputs and n multiplexed outputs, respectively, and has an input digital signal. In the line setting circuit of the synchronous multiplex converter that performs line setting by exchanging time slots of multiplexed signals, 1 / of the total line setting capacity
n line setting data memory circuits each having a capacity of n and to which the m inputs are respectively connected, and the same capacity as the line setting data memory circuits, and the m inputs are A spare data memory circuit to be connected, a signal selection circuit for selectively connecting the n line setting data memory circuits and the spare data memory circuits to the n outputs, respectively, and Of n pieces of read control information for respectively controlling reading from the line setting data memory circuit and an address control circuit for transmitting switching information for switching control of the signal selection circuit, and usually the n pieces of read control information. To each of the n line setting data memory circuits, and the signal selecting switching information for connecting the n line setting data memory circuits to each of the n outputs. If any of the n line setting data memory circuits has a fault, the read control information of the faulty line setting data memory circuit is given to the spare data memory circuit. At the same time, the switching information for switching the line setting data memory circuit in which the failure has occurred to the spare data memory circuit is given to the signal selecting circuit.

(Operation) According to the present invention, the signal on the line is directly written in parallel to the n line setting data memory circuits and the spare data memory circuits, and normally, the n line setting data memory circuits are set. The contents of the data memory circuit are read in accordance with the read control information to perform time slot conversion and output as a signal having a transmission speed similar to the original signal. When a failure occurs in any one of them, the signal selection circuit selects a spare data memory circuit in place of the data memory circuit in which the failure has occurred, and the content is read.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.
The input signals (lines) IN1 to IN4 are 8 Mb / s octet parallel signals, each of which has a signal of 960 channels, and the line setting total capacity, here 1/4 of 3840 channels.
Setting data memory circuit 24-1 having a capacity of
To 24-4 are introduced in parallel. The spare data memory circuit 25 is composed of the same circuit as the data memory circuit 24, and like the data memory circuit 24, the input signal IN1
~ IN4 is introduced. Data memory circuits 24-1 to 24-1
The operations of 24-4 and 25 are basically the same as those described with reference to FIG. 3, but in each data memory circuit, the input signal IN
The signals of 1 to IN4 are respectively transferred to dedicated data memory units (D
M) Sequentially write to 26-1 to 26-4. Therefore, all 3840 channels of the input signal are the data memory unit 2
It is stored in 6-1 to 26-4. Data memory unit 26-
The read from 1 to 26-4 is performed by the address control circuit 27.
Address Control Memory (ACM) 28-1 and 2
The read control information 29-1 to 29-4 of 8-4 is given to the data memory units 26-1 to 26-4 and is performed. The information read from the data memory units 26-1 to 26-4 is an arbitrary one of 8 Mb by the selection circuit (SEL) 30.
The output signal 31 is selected for each bit of / s. Therefore, in one of the data memory circuits 24-1 to 24-4, any 960 channels out of the 3840 channels are time slot converted and read out. A circuit setting circuit for 3840 channels can be realized with four circuits. The operating speed of this data memory circuit is 8 Mb / s for writing and 8 Mb / s for reading.
Since it is s, a general-purpose CMOS memory can be used with low power consumption in any circuit system of the parallel type double buffer circuit and the series type double buffer circuit.

The spare data memory circuit 25 performs the same operation as the other data memory circuits 24-1 to 24-4, but the way of giving the read control information 29-5 for reading is different. Information 3 such as data memory section failure information and forced switching command information sent from each of the data memory circuits 24-1 to 24-4
The read control information 29-5 is selected by the selection circuit (SEL) 35 by the control circuit (CONT) 34 that receives 2 and sends the appropriate switching information 33. The selected read control information 29-5 is stored in the spare data memory circuit 25.
Given to.

Therefore, the failed data memory circuits 24-1 to 24-4
The read control information given to the faulty circuit is given to the spare data memory circuit 25, and the same function as that of the faulty data memory circuit is achieved.

Further, the switching information 33 is given to the signal selection circuit (SEL) 36. In the signal selection circuit 36, the data memory circuit 24
Four output signals read from -1 to 24-4,
One signal read from the spare circuit is switched by the switching information 33 and four output signals OUT1 to OUT
Send as 4.

These switching functions can be switched without interruption by controlling by considering the operation frame of the line setting circuit.

(Effects of the Invention) As described above, according to the present invention, n line setting data memory circuits having a capacity of 1 / n of the line setting total capacity and the same capacity as the line setting data memory circuits are provided. A signal selection circuit for connecting spare data memory circuits each having m lines to m inputs and selectively connecting the n line setting data memory circuits and the spare data memory circuits to n outputs respectively. A circuit and an address control circuit for sending n pieces of read control information for controlling reading from the n pieces of data memory circuits for line setting and switching information for switching control of the signal selection circuit are provided, and usually The n pieces of read control information are given to the n pieces of line setting data memory circuits, respectively, and the n pieces of line setting data memory circuits are provided to the n outputs, respectively. The switching information to be connected is given to the signal selection circuit, and the n
When a failure occurs in one of the line setting data memory circuits, the read control information of the failed line setting data memory circuit is given to the spare data memory circuit and the failure occurs. Since the switching information for switching the line setting data memory circuit to the spare data memory circuit is given to the signal selection circuit, a plurality of inputs respectively multiplexed to a plurality of outputs respectively multiplexed, Not only the time slots of signals can be exchanged for line setting, but also the line setting memory can be configured in parallel so that it can be processed at low speed, and general-purpose CMOS memory can be used. Since it is not necessary to multiplex the signals, a large-scale external circuit is unnecessary.

Also, as a redundant configuration, it does not require a memory of the same capacity as the line setting total capacity as in the conventional case, and is 1 / of the line setting total capacity.
Since it is only necessary to provide a memory having the same capacity as the memory for setting the line of n, there is an advantage that the entire hardware amount can be reduced and a highly reliable circuit with low power consumption can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a line setting circuit of the present invention, FIG. 2 is a block diagram showing a line setting and multiple conversion function section of a synchronous multiplex converter, and FIG. 3 is a basic configuration of the line setting circuit. FIG. 4 is a block diagram showing a configuration of a conventional line setting circuit. 24-1 to 24-4 ... Data memory circuit for line setting, 25 ... Spare data memory circuit, 26-1 and 26-2
6-4 ... Data memory unit, 27 ... Address control circuit, 28-1 to 28-4 ... Address control memory, 29-1 to 29-5 ... Read control information, 33 ...
Switching information, 36 ... Signal selection circuit.

Front Page Continuation (72) Inventor Yoichi Ito 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Abe Senetsu 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. Incorporated (72) Inventor Noriyuki Terada 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Inside Nihon Telegraph and Telephone Corporation (56) Reference JP 59-19497 (JP, A) JP 59-154895 (JP, A)

Claims (1)

[Claims] 1. Synchronous multiplexing having m multiplexed inputs and n multiplexed outputs, respectively, and performing channel setting by exchanging time slots of input digital multiplexed signals. In the line setting circuit of the converter, n line setting data memory circuits each having a capacity of 1 / n of the line setting total capacity and each of which is connected to the m inputs, and the line setting data. A spare data memory circuit having the same capacity as that of the memory circuit, to which the m inputs are connected, and the n line setting data memory circuits and the spare data memory circuits are selectively selected by the n circuits. A signal selection circuit connected to each output of the book, and a switching control for switching the n pieces of read control information and the signal selection circuit for controlling the reading from the n number of data memory circuits for line setting. Address control circuit for transmitting replacement information. Normally, the n pieces of read control information are supplied to the n pieces of line setting data memory circuits, respectively, and the n pieces of line setting data memory circuits are provided. Switching information to be connected to each of the n outputs is given to the signal selection circuit, and when a failure occurs in any of the n data memory circuits for line setting, the data memory for line setting in which the failure has occurred Circuit read control information is given to the spare data memory circuit, and switching information for switching the faulty line setting data memory circuit to the spare data memory circuit is given to the signal selection circuit. A line setting circuit characterized in that