JPH0622237B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0622237B2 JPH0622237B2 JP58222040A JP22204083A JPH0622237B2 JP H0622237 B2 JPH0622237 B2 JP H0622237B2 JP 58222040 A JP58222040 A JP 58222040A JP 22204083 A JP22204083 A JP 22204083A JP H0622237 B2 JPH0622237 B2 JP H0622237B2
- Authority
- JP
- Japan
- Prior art keywords
- base
- region
- etching
- emitter
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000005530 etching Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims 3
- 239000000377 silicon dioxide Substances 0.000 claims 3
- 238000001312 dry etching Methods 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 239000012495 reaction gas Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置の製造方法に関し詳しくはバイポー
ラ型シリコンＬＳＩに好適な、高速でかつ微細な半導体
装置を製造できる半導体装置の製造方法に関するもので
ある。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for a bipolar silicon LSI capable of manufacturing a fine semiconductor device at high speed. is there.
第１図は、従来のバイポーラトランジスタの断面構造を
示したものである。従来の構造のトランジスタは、いわ
ゆるプレーナ技術によつて作られている。すなわち、ｐ
型基板１−１４上にＮ型埋込層１−１２を設け、ｎ型エ
ピタキシヤル層１−１３を成長する。その後素子間分離
用酸化膜１−１を形成し、ｎ型エピタキシヤル層内にｐ
型ベース層１−６、また、ベース層内にｎ型エミッタ層
１−７を設ける。なお、１−１３は、コレクタ層であ
る。この様につくられた造造では、酸化膜に順次穴あけ
をして不純物を拡散してゆくために酸化膜の穴の大きさ
よりも大きな拡散領域が形成される。特に、エミツタ領
域１−７の周囲は、ベース領域の表面の不純物濃度の高
い領域と接しているため、接合容量ＣTEが大きくなつて
いる。この大きな容量のため、トランジスタの動作速度
が遅くなる。この傾向は、メモリ回路の様に、エミツタ
領域を並列に接続した回路に、トランジスタを応用した
ときに著しくなる。FIG. 1 shows a sectional structure of a conventional bipolar transistor. Transistors of conventional structure are made by so-called planar technology. That is, p
An N-type buried layer 1-12 is provided on the mold substrate 1-14, and an n-type epitaxial layer 1-13 is grown. After that, an oxide film 1-1 for element isolation is formed, and p is formed in the n-type epitaxial layer.
The type base layer 1-6 and the n-type emitter layer 1-7 are provided in the base layer. In addition, 1-13 is a collector layer. In the fabrication made in this manner, holes are sequentially formed in the oxide film to diffuse impurities, so that a diffusion region larger than the size of the holes in the oxide film is formed. In particular, since the periphery of the emitter region 1-7 is in contact with the region of the surface of the base region having a high impurity concentration, the junction capacitance C TE is large. This large capacitance slows the operating speed of the transistor. This tendency becomes remarkable when the transistor is applied to a circuit in which the emitter regions are connected in parallel like a memory circuit.
また、従来の構造のトランジスタでは、ベース領域の内
部にエミツタ領域が均一に形成されているため、ベース
電極１−８と真性ベース領域１−６′との間の抵抗が大
きい。この抵抗（ベース抵抗）は、ベース領域の拡散深
さが浅くなるほど大きくなる。トランジスタの速度を向
上させるためには、エミツタ領域とベース領域の拡散深
さを双方とも浅く形成しなければならない。しかし、ベ
ース領域を浅くすると、同時にベース抵抗も高くなり、
思つた程の高速化は得られない。Further, in the transistor having the conventional structure, since the emitter region is uniformly formed inside the base region, the resistance between the base electrode 1-8 and the intrinsic base region 1-6 'is large. This resistance (base resistance) increases as the diffusion depth of the base region decreases. In order to improve the speed of the transistor, both the emitter region and the base region must be formed with a shallow diffusion depth. However, if the base region is made shallow, the base resistance also increases,
You can't get the speed you want.
また、従来の技術によりベースのコンタクト穴を明ける
と、ベース電極１−８とコレクタ領域１−１３とが短絡
するおそれがある。すなわち、従来のトランジスタは、
より小さく作ろうとするため、ベース・コンタクト穴を
分離用酸化膜の端にオーバラツプして取り出している。
酸化膜に穴をあける時、エミチング時間が長いと、分離
用酸化膜にも深く穴があき、ベース領域下のコレクタ領
域にまで到達して、ベース電極とコレクタ領域とが短絡
する。この傾向は、ベース領域の深さが浅い高速なトラ
ンジスタほど著しい。Further, when the contact hole of the base is formed by the conventional technique, the base electrode 1-8 and the collector region 1-13 may be short-circuited. That is, the conventional transistor is
In order to make it smaller, the base contact hole is taken out by overlapping the edge of the isolation oxide film.
If the emitting time is long when the hole is formed in the oxide film, the separation oxide film also has a deep hole, reaching the collector region below the base region and short-circuiting the base electrode and the collector region. This tendency is remarkable in a high-speed transistor having a shallow base region.
本発明の目的は、上記従来の欠点を無くした、エミツタ
・ベース接合間の接合容量の少い、かつベース抵抗の小
さなトランジスタの製造方法を提供することにある。It is an object of the present invention to provide a method of manufacturing a transistor having a small junction capacitance between an emitter and a base junction and a small base resistance, which eliminates the above-mentioned conventional drawbacks.
上記目的を達成するため、本発明は、Ｃ，ＨおよびＦを
含み、Ｆ対Ｈの比がほぼ２以下のガスを反応ガスとして
用いると、Ｓｉ3Ｎ4を極めて高い選択比でドライエツチ
することができ、ＣＨ3ＦおよびまたはＣＨ2Ｆ2を用い
ると、とくに極めて好ましい結果が得られる、という新
規な知見にもとづいている。In order to achieve the above object, the present invention provides dry etching of Si 3 N 4 with an extremely high selectivity by using a gas containing C, H and F and having an F to H ratio of about 2 or less as a reaction gas. Based on the novel finding that particularly highly favorable results are obtained with CH 3 F and / or CH 2 F 2 .
このような知見にもとづき、上記ガスによつてＳｉ3Ｎ4
をドライエツチすることによつて、接合容量を減少さ
せ、ベース抵抗を下げることが可能となつた。すなわ
ち、本発明は、Ｓｉ3Ｎ4のエツチング速度がシリコン酸
化膜ＳｉＯ２およびシリコン膜よりも著しく大きい上記
反応ガスを用いたドライエツチング技術を用いることに
よつて初めて可能となつた。Based on such knowledge, the above gas is used to produce Si 3 N 4
It was possible to reduce the junction capacitance and the base resistance by dry etching. That is, the present invention was made possible only by using the dry etching technique using the above reaction gas in which the etching rate of Si 3 N 4 is significantly higher than that of the silicon oxide film SiO 2 and the silicon film.
第２図に本発明によるトランジスタの構造の一例を示
す。本発明では、エミツタ２−７とベース領域２−６の
表面に段差を設け、エミツタ領域２−７の周囲を酸化膜
２−２で囲うことによつて、エミツタ２−７とベース２
−６間の接合容量を減少させている。また、本発明の構
造を実現するために用いられるドライエツチング技術を
用いることによつて、ベース領域のコンタクト穴をコレ
クタ領域と短絡させない様にあけることが出来る。ま
た、外部ベース領域は、真性ベース領域に比べ深く拡散
されているので、ベース抵抗が低減されている。FIG. 2 shows an example of the structure of the transistor according to the present invention. In the present invention, a step is provided on the surfaces of the emitter 2-7 and the base region 2-6 and the periphery of the emitter region 2-7 is surrounded by the oxide film 2-2.
The junction capacitance between −6 is reduced. Further, by using the dry etching technique used to realize the structure of the present invention, it is possible to prevent the contact hole in the base region from being short-circuited with the collector region. Further, since the external base region is diffused deeper than the intrinsic base region, the base resistance is reduced.
第３図は、本発明による構造を実現するための製造工程
を示したものである。なお、本発明の思想を明確にする
ために、エピタキシヤル工程や埋込層形成工程は省略
し、トランジスタの動作に不可欠なベース領域、エミツ
タ領域の形成工程を示した。FIG. 3 shows a manufacturing process for realizing the structure according to the present invention. In order to clarify the concept of the present invention, the epitaxial process and the buried layer forming process are omitted, and the forming process of the base region and the emitter region, which are indispensable for the operation of the transistor, are shown.
第３図(a)：分離用酸化膜２−１を形成した後、エミツ
タ領域となる部分以外のシリコン表面を従来のエツチン
グ技術を利用して削り、凸型の領域を形成する。FIG. 3 (a): After forming the isolation oxide film 2-1, the silicon surface other than the portion to be the emitter region is shaved by the conventional etching technique to form a convex region.
第３図(b)：薄い酸化膜２−２、シリコンナイトライド
膜２−３を形成し、エミツタ領域となる部分をホトレジ
スト膜２−４でおおつて、シリコンナイトライド膜２−
３を後に説明するドライエツチング法で削る。なお、こ
のときのホトレジストの寸法は、エミツタ領域よりもや
や大きめで良く、正確な寸法合せは必要としない。FIG. 3 (b): A thin oxide film 2-2 and a silicon nitride film 2-3 are formed, and a portion which becomes an emitter region is covered with a photoresist film 2-4.
3 is ground by the dry etching method described later. The size of the photoresist at this time may be slightly larger than that of the emitter region, and accurate size matching is not required.
第３図(c)：ホトレジスト膜２−４を除去し、再び上記
ドライエツチング法を利用して、シリコンナイトライド
膜を除去すると、凸型領域の周囲にのみシリコンナイト
ライド膜２−５が残る。凹型の領域２−ＧＢの分離用酸
化膜に接する部分にはナイトライド膜はなくなり、ベー
ス・コンタクト穴を大きくあけることができる。FIG. 3 (c): When the photoresist film 2-4 is removed and the silicon nitride film is removed again using the dry etching method, the silicon nitride film 2-5 remains only around the convex region. . The portion of the concave region 2-GB that is in contact with the isolation oxide film has no nitride film, and a large base contact hole can be formed.
第３図(d)：表面より、イオン打込み法等によりベース
領域２−６を形成し、次にエミツタ領域２−７を形成す
る。その後電極配線を行うと、第２図に示した様な素子
構造が得られる。FIG. 3 (d): From the surface, a base region 2-6 is formed by an ion implantation method or the like, and then an emitter region 2-7 is formed. After that, electrode wiring is performed to obtain an element structure as shown in FIG.
本実施例では、新しいドライエツチング法を利用するこ
とによつて、凸型エミツタ領域の周囲にのみシリコンナ
イトライド膜を残し、エミツタ・ベース容量の低減と、
ベースコンタクト穴を大きくあけることに成功した。ま
た、従来のドライエツチング技術の様に、ベースコンタ
クト穴をあけるとき、分離用の酸化膜をオーバにエツチ
ングすることがないため、歩留り良くベース電極の配線
をすることができる。In the present embodiment, by utilizing the new dry etching method, the silicon nitride film is left only around the convex type emitter region, and the emission base capacitance is reduced,
We have succeeded in making a large base contact hole. Further, unlike the conventional dry etching technique, when the base contact hole is opened, the oxide film for isolation is not overetched, so that the base electrode can be wired with high yield.
以下に本発明において用いたドライエツチングの方法を
詳細に述べる。The dry etching method used in the present invention will be described in detail below.
このドライエツチングは、上記のようにＣ，ＨおよびＦ
を含み、Ｆ対Ｈの比がほぼ２以下であるガスを反応ガス
として用いるものであるが、便宜上、極めて好ましい結
果が得られるＣＨ3Ｆ，ＣＨ2Ｆ2を用いた場合について
説明する。This dry etching is performed with C, H and F as described above.
A gas containing F and having an F to H ratio of about 2 or less is used as the reaction gas, but for convenience, the case of using CH 3 F, CH 2 F 2 which gives extremely preferable results will be described.
周知のように、シリコンもしくはその化合物のドライエ
ツチングは、たとえば、ＣＦ４，ＣＦ４＋Ｏ２，Ｎ
Ｆ３，ＳＦ６，ＣＨＦ３，ＣＦ4＋Ｈ2などを反応ガスと
して用いて行なわれた。As is well known, dry etching of silicon or its compound is performed by using, for example, CF 4 , CF 4 + O 2 , N.
F 3 , SF 6 , CHF 3 , CF 4 + H 2 and the like were used as reaction gases.
しかし、Ｓｉ，ＳｉＯ２およびＳｉ3Ｎ4のエツチング速
度を比較すると、ＣＦ４，ＣＦ４＋Ｏ２，ＮＦ３もしく
はＳＦ６を用いた場合は、Ｓｉのエツチ速度が最も大き
く、Ｓｉ3Ｎ4，ＳｉＯ２の順で反応速度は小さくなる。However, comparing the etching rates of Si, SiO 2 and Si 3 N 4 , when CF 4 , CF 4 + O 2 , NF 3 or SF 6 is used, the etching rate of Si is the highest and Si 3 N 4 , The reaction rate decreases in the order of SiO 2 .
また、反応ガスとしてＣＨＦ３もしくはＣＦ４＋Ｈ２を
用いると、ＳｉにくらべてＳｉＯ２とＳｉ3Ｎ4のエツチ
ング速度が大きくなるが、ＳｉＯ２とＳｉ3Ｎ4のエツチ
ング速度比は、ほぼ２〜３程度にすぎなかつた。When CHF 3 or CF 4 + H 2 is used as the reaction gas, the etching rate of SiO 2 and Si 3 N 4 is higher than that of Si, but the etching rate ratio of SiO 2 and Si 3 N 4 is almost 2 It was only ~ 3.
そのため、Ｓｉ3Ｎ４を選択的にエツチする際には、Ｃ
Ｆ２＋Ｏ２やＳＦ６が反応ガスとして用いられてきた
が、この場合、Ｓｉのエツチング速度が大きいため、下
地のＳｉがエツチされるのを防止するため、Ｓｉ3Ｎ4膜
と下地Ｓｉの間に、ＳｉＯ２膜を形成しなければなら
ず、しかも、ＳｉＯ２とＳｉ3Ｎ4の選択比が小さいた
め、上記ＳｉＯ２膜を厚くする必要があつた。Therefore, when selectively etching Si 3 N 4 , C
Although F 2 + O 2 and SF 6 have been used as a reaction gas, in this case, since the etching rate of Si is high, the Si 3 N 4 film and the underlying Si are prevented from being etched to prevent etching of the underlying Si. In between, a SiO 2 film has to be formed, and since the selection ratio of SiO 2 and Si 3 N 4 is small, it is necessary to thicken the SiO 2 film.
すなわち、従来は、ＳｉやＳｉＯ２に対して、高い選択
比をもつてＳｉ3Ｎ4膜を選択的にドライエツチすること
が困難となつていた。That is, conventionally, it has been difficult to selectively dry etch the Si 3 N 4 film with a high selection ratio with respect to Si or SiO 2 .
そこで本発明では、特に反応ガスとして従来のドライエ
ツチングでは用いられていなかつたＣＨ2Ｆ2およびもし
くはＣＨ3Ｆを用い、Ｓｉ3Ｎ4の高選択ドライエツチン
グを行なつた。本発明では一般に平行平板型ＲＩＥ（Re
active Ion Etching）と呼ばれる装置を用い、真空容
器内の高周波電極上に石英板を介して半導体基板を設置
し、真空容器内を１×１０-5Ｔorr以下に排気した後Ｃ
Ｈ2Ｆ2ガスを導入して圧力を０．０３Torrに保持した。
しかる後周波数１３．５６ＭＨｚの高周波電力を高周波
電極に印加し、プラズマを発生させＳｉ3Ｎ4をエツチン
グした。このとき高周波電力は約５００Ｗに保持した
が、Ｓｉ3Ｎ4とＳｉＯ２のエツチング速度比は約２０、
Ｓｉ3Ｎ4とＳｉまたはpoly Ｓｉとのエツチング速度比
は約２５とＳｉ3Ｎ4だけが高選択でエツチングできた。
またＳｉ3Ｎ4のエツチング速度は約３０ｎｍ／分であ
り、本実施例では約５分間エツチングしたが、ＳｉＯ２
やＳｉはほとんどエツチングされることがなかつた。Therefore, in the present invention, highly selective dry etching of Si 3 N 4 is performed by using CH 2 F 2 and / or CH 3 F which has not been used in the conventional dry etching as a reaction gas. In the present invention, the parallel plate type RIE (Re
Using a device called active ion etching, a semiconductor substrate is placed on a high-frequency electrode in a vacuum container through a quartz plate, and the inside of the vacuum container is evacuated to 1 × 10 −5 Torr or less.
H 2 F 2 gas was introduced to maintain the pressure at 0.03 Torr.
Thereafter, high frequency power having a frequency of 13.56 MHz was applied to the high frequency electrode to generate plasma and etch Si 3 N 4 . At this time, the high frequency power was kept at about 500 W, but the etching speed ratio of Si 3 N 4 and SiO 2 was about 20,
The etching speed ratio between Si 3 N 4 and Si or poly Si was about 25, and only Si 3 N 4 could be etched with high selection.
The etching speed the Si 3 N 4 is about 30 nm / min, although the present embodiment has been etched for about 5 minutes, SiO 2
Almost no silicon or Si was etched.
以上述べた如く、本発明によれば、バイポーラトランジ
スタの接合容量の大幅低減と、ベース抵抗の減少、ベー
スコンタクトのコレクタ短絡防止等に飛躍的な効果があ
る。As described above, according to the present invention, the junction capacitance of the bipolar transistor is greatly reduced, the base resistance is reduced, and the collector short circuit of the base contact is prevented.
なお、本発明で述べてあるｐ型領域とｎ型領域と互に変
えても、本発明による構造は実現できることは言うまで
もない。It goes without saying that the structure according to the present invention can be realized even if the p-type region and the n-type region described in the present invention are mutually changed.
第１図は従来のバイポーラ素子断面図、第２図は本発明
の一実施例を示す断面図、第３図は本発明の一実施例を
示す工程図である。 １……酸化膜、２……薄い酸化膜、３……ナイトライド
膜、４……ホトレジスト、５……ナイトライド膜、６…
…ベース領域、７……エミツタ領域、８……ベース電
極、９……エミツタ電極、１０……コレクタ電極、１１
……コレクタ取出し領域、１２……埋込層、１３……コ
レクタ領域、１４……基板。FIG. 1 is a sectional view of a conventional bipolar device, FIG. 2 is a sectional view showing an embodiment of the present invention, and FIG. 3 is a process drawing showing an embodiment of the present invention. 1 ... oxide film, 2 ... thin oxide film, 3 ... nitride film, 4 ... photoresist, 5 ... nitride film, 6 ...
... base region, 7 ... emitter region, 8 ... base electrode, 9 ... emitter electrode, 10 ... collector electrode, 11
...... Collector extraction area, 12 …… Buried layer, 13 …… Collector area, 14 …… Substrate.
Claims (2)
板の表面をエッチして凸部を形成する工程と、二酸化シ
リコン膜および窒化シリコン膜を積層して形成する工程
と、上記二酸化シリコン膜を異方性エッチし、上記二酸
化シリコン膜のうち、上記凸部の側部上に形成された部
分を残し、他の部分は除去する工程と、Ｃ、ＨおよびＦ
を含み、Ｆ対Ｈの比がほぼ２以下であるガスをエッチン
グガスとして用いたエッチングによって上記窒化シリコ
ン膜の露出された部分を除去する工程と、上記半導体基
板の表面領域内に第１導電型を有する不純物をドープし
てベースを形成する工程と、上記凸部の表面領域内に上
記第１導電型とは逆の第２導電型を有する第２の不純物
をドープして、上記凸部内に上記ベースの上面に接して
エミッタを形成する工程を少なくとも有することを特徴
とする半導体装置の製造方法。1. A step of etching a surface of a semiconductor substrate other than a portion where an emitter is to be formed to form a convex portion, a step of stacking a silicon dioxide film and a silicon nitride film, and forming the silicon dioxide film. A step of anisotropically etching, leaving a portion of the silicon dioxide film formed on the side portion of the convex portion and removing the other portion, C, H and F
And removing the exposed portion of the silicon nitride film by etching using a gas having an F to H ratio of about 2 or less as an etching gas; and a first conductivity type in a surface region of the semiconductor substrate. And forming a base by doping an impurity having a second conductivity type with a second impurity having a second conductivity type opposite to the first conductivity type in the surface region of the protrusion, A method of manufacturing a semiconductor device, comprising at least a step of forming an emitter in contact with an upper surface of the base.
なる群から選ばれることを特徴とする特許請求の範囲第
１項記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the gas is selected from the group consisting of CH 3 F and CH 2 F 2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58222040A JPH0622237B2 (en) | 1983-11-28 | 1983-11-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58222040A JPH0622237B2 (en) | 1983-11-28 | 1983-11-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60115261A JPS60115261A (en) | 1985-06-21 |
| JPH0622237B2 true JPH0622237B2 (en) | 1994-03-23 |
Family
ID=16776139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58222040A Expired - Lifetime JPH0622237B2 (en) | 1983-11-28 | 1983-11-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0622237B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54128683A (en) * | 1978-03-27 | 1979-10-05 | Ibm | Method of fabricating emitterrbase matching bipolar transistor |
| JPS5674962A (en) * | 1979-11-21 | 1981-06-20 | Semiconductor Res Found | Semiconductor device |
| JPS5680161A (en) * | 1979-11-29 | 1981-07-01 | Ibm | Bipolar transistor |
-
1983
- 1983-11-28 JP JP58222040A patent/JPH0622237B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54128683A (en) * | 1978-03-27 | 1979-10-05 | Ibm | Method of fabricating emitterrbase matching bipolar transistor |
| JPS5674962A (en) * | 1979-11-21 | 1981-06-20 | Semiconductor Res Found | Semiconductor device |
| JPS5680161A (en) * | 1979-11-29 | 1981-07-01 | Ibm | Bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60115261A (en) | 1985-06-21 |
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