JPH06188252A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To reduce the area of base-emitter junction and base width by converting the conductivity type of a major semiconductor layer region, exposed in a trench extending from a second insulator layer to the surface of the major semiconductor layer, into a second conductivity type, and etching the oxide film on the major semiconductor layer using the oxide film on the side wall of the trench as a mask. CONSTITUTION:A trench extending to the surface of an n<->type SiC layer is formed in a CVD SiO2 layer 5, and an ion is implanted through the trench to invert the conductivity type of the SiC layer. AB-doped p-type polysilicon layer 8 which will be rapidly oxidized is deposited on the resultant p-type SiC region. The polysilicon layer 8, except for that on the side wall of the trench, is thermally oxidized into a SiO2 layer 8a. The SiO2 layer 2a and SiC layer 2 at the bottom of the trench is removed using the resultant SiO2 layer as a mask. A p-doped n-type polysilicon layer 9 is deposited on the trench region, including the side face of a p-type SiC region 6, and a heat treatment is performed. As a result, a p-type SiC base region 6a, including an n<+>-type SiC emitter region 10, is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor, and more particularly to a method for manufacturing a lateral bipolar transistor formed on an insulating substrate.

[0002] In recent years, with the progress of information society, the required information processing amount has been increasing. In order to increase the speed of the integrated circuit, which is the heart of the information processing apparatus, it is necessary to reduce the wiring capacitance and parasitic resistance as well as the speed of the transistor that is the key device. The main force for high-speed calculation is
It is a bipolar transistor.

[0003]

2. Description of the Related Art To increase the speed of bipolar transistors,
Techniques such as shallow junction formation, high-concentration doping, and polysilicon wiring are used in a self-aligned structure in order to reduce the junction capacitance and the lead wiring resistance.

The structure around the base and emitter of a bipolar transistor in a typical conventional integrated circuit is shown in FIG.
A cross-sectional view is shown in FIG. Such a structure can be produced as follows.

First, a buried collector region 52 is formed at a predetermined position of a p-type Si substrate 50 by selective doping, and an epitaxial layer 51 made of n-type Si is grown on the buried collector region 52.

Next, a thick field oxide film 53 for element isolation is formed by thermal oxidation by using a selective oxidation technique using Si ₃ N ₄ as a mask, for example. Next, an n-type impurity is diffused through an opening for collector contact formed in a field oxide film (not shown) to form a diffusion region reaching the collector buried layer 52.

Further, a SiO ₂ layer 55, a polysilicon layer 57 for a base extraction electrode and a SiO ₂ layer 61 are deposited by CVD. Polysilicon layer 57 for base extraction electrode
Is doped with p-type impurities so as to have a sufficiently low resistance, and is patterned so as to remain only in a necessary portion.

Next, a mask is formed on the surface and SiO _{2 is} added.
The layer 61 / polysilicon layer 57 / SiO ₂ layer 55 is etched to provide openings of predetermined size for forming a base and an emitter at predetermined positions. This opening is formed on the epitaxial layer 51.
Penetrate to the surface. Boron or the like is ion-implanted into this opening to form a p-type region. Further, a p-type polysilicon layer doped with acceptor impurities is deposited in the region including the opening. Next, after applying a resist on the entire surface, anisotropic etching of the resist is performed to leave the resist only inside the opening.

Next, anisotropic plasma etching of polysilicon is performed using SiCl ₄ + Cl ₂ gas or the like to remove the polysilicon in the flat portion exposed from the resist,
Further, after removing the polysilicon remaining between the opening and the resist by about 2000 to 5000 Å from the upper layer, the resist is removed and anisotropic etching of the polysilicon is performed again to leave the polysilicon remaining at the bottom of the opening. Are removed by etching. Thus 2000 ~ 5 than the top of the opening
A sidewall 59 of polysilicon that is lower by about 000Å is formed.

Next, the oxide film 63 is formed by the CVD method. Next, anisotropic dry etching is performed using CF ₄ + H ₂ gas to remove the oxide film at the bottom of the opening leaving a CVD oxide film of a predetermined thickness only on the side wall of the opening.
Expose. A doped polysilicon layer 65 containing a high concentration of donor impurities is deposited on this opening.

When heat treatment is performed, donor impurities such as arsenic are diffused from doped polysilicon 65 to form n type emitter region 49, and at the same time acceptor impurities contained in sidewall polysilicon 59 are epitaxial layer 51. To form a p-type external base region 47. Further, this heat treatment activates the previously ion-implanted boron to form the internal base region 48.

The SiO ₂ layer 61 on the field oxide film 53
An opening of a predetermined size is provided at a predetermined position to expose the base lead-out electrode polysilicon layer 57 and the Si substrate surface of a collector contact region (not shown). By depositing an electrode metal such as Al or W on the surface and patterning it, an emitter electrode 67, a base electrode 69 and a collector electrode (not shown) are formed, and the structure shown in FIG. 3 is obtained.

[0013]

In the above-mentioned conventional technique, the pn junction area of the base and the emitter depends on the opening area patterned by using the photolithography technique. Therefore, it is practically difficult to form a finer and finer bonding area than the accuracy of photolithography.
There are restrictions on the reduction of the base-emitter capacitance C _BE and the base-collector capacitance C _BC .

The depth of the base region has been determined by the ion implantation technique. However, even if an attempt is made to make the depth of the base region shallower than before, in order to secure the beam current at the time of ion implantation at a practical level, the acceleration energy at the time of ion implantation may be lowered to a certain level or less. Difficulty, which has made it difficult to form a shallow base by ion implantation.

Further, a so-called channeling phenomenon is known in which ions penetrate between atoms of a Si substrate and ions are deeply implanted into the Si substrate at a voltage higher than the acceleration voltage. This phenomenon is caused by a low acceleration voltage. Since it is relatively remarkable, it is difficult to make the base region shallow also in this sense.

Further, in order to reduce the capacitance between elements and wiring more than ever, a so-called SOI using an insulating substrate is used.
Adoption of (Semiconductor on Insulator) is considered desirable.

An object of the present invention is to provide a new manufacturing method capable of reducing the base / emitter junction area and the base width in the formation of a lateral bipolar transistor having an SOI structure in order to further increase the speed of the bipolar transistor.

[0018]

A method of manufacturing a bipolar transistor according to the present invention comprises a step of preparing a substrate having a first conductivity type main semiconductor layer on an insulating substrate, and a first step on the main semiconductor layer. Stacking the insulating layer, the first conductive layer, and the second insulating layer in this order, and providing an opening of a predetermined size that extends from the second insulating layer to the surface of the main semiconductor layer. A step of converting the main semiconductor layer region exposed by the opening to a second conductivity type to form a base region, and an oxidation rate under the same conditions in the opening as compared with the first semiconductor. Of a second conductor layer having a larger thickness, a step of forming an oxide film of the second conductor on the side wall surface by thermal oxidation, and a step of forming the second conductor on the side wall of the opening. Using the oxide film as a mask, the main And a step of etching the oxide film of the conductor layer, and forming an emitter region comprising a first conductivity type impurity into the opening of the main semiconductor layer.

[0019]

The base width can be determined not by the accuracy of photolithography but by the thickness of the side wall deposition layer of the opening.

The base / emitter junction area is not determined by photolithography but can be determined by the film thickness of the semiconductor layer having the SOI structure. Of course, it is possible to combine the characteristics of the small parasitic capacitance peculiar to the lateral bipolar transistor of the SOI structure and the increase of the collector current capability due to the increase of the peripheral length of the emitter (emitter formation in the peripheral portion for the emitter electrode).

The present invention will be described in detail below based on examples.

[0022]

1 and 2 are sectional views showing the main manufacturing steps of an SOI structure lateral bipolar transistor according to an embodiment. In this embodiment, a manufacturing process of a bipolar transistor using SiC will be described.

First, epitaxial n is formed on the insulating substrate 1.
^The -type SiC layer 2 is laminated. As the insulating substrate 1, for example, sapphire or the like can be used, but as a larger area and a simple method, SiO ₂ thickly formed on the Si substrate by a thermal oxidation process can be used.

For manufacturing such a substrate, the SiC layer epitaxially grown on the Si substrate and the oxide film formed on the Si substrate are brought into close contact with each other and bonded by heating or the like.
The Si substrate on the SiC layer side may be etched off. The growth of the n ⁻ -type SiC layer can be performed as follows, for example.

To remove the natural oxide film on the surface of the Si substrate
To H₂Heat treatment at 1000 ° C for 10 minutes in the atmosphere
U Then C₃H₈+ H₂1000 ° C for 30 minutes in the atmosphere
Heat treatment is performed between the two to form a carbonized layer on the Si substrate surface.
After that, SiHCl₃+ C ₃H₈+ H₂9 in the atmosphere
Heat treatment is performed at 00 to 1000 ° C., and Si is placed on the Si substrate.
The epitaxial layer of C is formed. Furthermore, Epita
A slight flow of phosphorus-based gas during the growth of the axial layer
Therefore, the carrier concentration is 10¹⁵-10¹⁶cm^-3N-type SiC
To get

Since the surface of the growth layer is very flat, β-Si
When the growth surface of C is pressed against the SiO ₂ thermal oxide film and heated in a hydrogen stream, β-SiC and SiO ₂ are directly bonded.
After that, a structure shown in FIG. 1A can be obtained by attaching a protective film on the back surface of the Si wafer which is the substrate of SiO ₂ and etching only the Si wafer which is the substrate of β-SiC. Buffer S
Since the composition of iC gradually changes from that of Si, it can be removed by this etching process.

The base / emitter junction area of the lateral bipolar transistor is determined by the thickness of the n ^-- type SiC layer 2. For example, this thickness may be 100-30 as described above.
Choose 00A.

Next, as shown in FIG. 1B, next, n ⁻ type Si is used.
A CVD SiO ₂ layer 3 having a thickness of about 2000 A is formed on the C layer 2. Further thereon, a B-doped p-type polysilicon layer 4 having a thickness of about 3000 A is deposited.

A photolithographic mask is formed and Cl ₂
CVD SiO ₂ by dry etching using gas
The B-doped polysilicon layer 4 is anisotropically etched and patterned using the layer 3 as a stopper. Further thereon, a SiO ₂ layer 5 having a thickness of about 3000 A is deposited by CVD.

Next, as shown in FIG. 1C, CVDSi is used.
An opening made of a resist of a predetermined size is formed at a predetermined position of the O ₂ layer 5 by using a normal photolithography technique.
Then, using anisotropic dry etching, n ⁻ -type SiC
Form an opening that reaches the surface of layer 2.

CF ₄ + H ₂ gas is used for reactive ion etching (RIE) of the CVD SiO ₂ layers 3 and 5, and Cl ₂ + BCl ₂ gas is used for RIE of the polysilicon layer 4. Ion implantation for inverting the conductivity type of SiC is performed from this opening. For example, Al ions 7 may be dosed at 3 × 10 ¹³ cm ^-2 at an acceleration voltage of 20 KeV.
Of course, it is possible to implant other acceptor impurities.

Β-SiC on the insulating substrate exposed in the opening
Since all layers need only be p-converted, the ion acceleration voltage can be easily controlled without requiring high accuracy. As a result,
As shown in (C), p-type SiC region 6 is formed in this region.

As shown in FIG. 1D, a B-doped p-type polysilicon layer 8 is deposited thereon to a thickness of 100 to 3000A. Compared with β-SiC, polysilicon has a high oxidation rate.

Next, as shown in FIG. 2A, Cl ₂ +
Anisotropic dry etching is performed by RIE using BCl ₂ gas to remove the polysilicon layer 8 on the side wall of the opening while leaving the polysilicon layer 8 on the side wall of the opening.

As shown in FIG. 2 (B), in a wet atmosphere, for example, at 900 ° C., about 100 minutes, 1000
When ℃ to about 10 minutes thermal oxidation in the case of polysilicon layer 8 of the opening side wall, from the surface to about 2000A is SiO ₂ turned into a thermal oxide SiO ₂ layer 8a is formed.

On the other hand, SiC has a property that it is much more stable than Si and is less likely to be oxidized.
The thickness of the oxide film formed on C is 1/1 of that of polysilicon.
It is about 0 and about 200A.

When SiC is oxidized, most of the carbon component evaporates as CO ₂ , so that the oxide film component becomes the carbon-containing SiO ₂ layer 2a. As shown in FIG. 2C, anisotropic dry etching is then performed using RIE to remove the SiO ₂ layer 2a at the bottom of the opening and the SiC layer 2 (p-type SiC layer 6) below it. At this time, the thermally oxidized SiO ₂ layer 8a on the side wall becomes a mask pattern.

The thickness of the SiO ₂ layer 2a depends on the thermal oxidation S on the side wall.
Since it is about 1/10 of the iO ₂ layer 8a, the SiO ₂ layer 2
The etching of a can be carried out by wet etching with a normal aqueous solution of hydrofluoric acid without substantially affecting the side wall SiO ₂ layer 8a.

As shown in FIG. 2D, the next exposed p
A P-doped n-type polysilicon layer 9 is deposited in the opening region including the surface of the type SiC region 6 side. The side surface of the p-type SiC layer is covered with the n-type polysilicon layer 9.

When an appropriate heat treatment, for example, a heat treatment at 1100 ° C. for 5 seconds is performed, phosphorus is laterally diffused from the P-doped polysilicon layer 9 to the p-type SiC region 6 and n ⁺ -type SiC is formed.
The emitter region 10 and the p-type SiC base region 6a composed of the rest are simultaneously formed.

In this step, without using the P-doped polysilicon layer 9, first, undoped polysilicon is deposited, and then donor impurity ions such as P or As ions are deposited at 60K.
Ion implantation may be performed at about 1 × 10 ¹⁶ cm ⁻² at eV. This ion implantation can be simultaneously performed on the n ⁻ -type SiC layer 2 in the collector electrode opening which is not touched in the above steps.

If the heat treatment is performed after the ion implantation, P
Alternatively, As ions can be diffused to form an n ⁺ -type SiC region. In this way, the emitter region 1
0, base region 6a, collector regions 2 and 14 are formed simultaneously.

Finally, the base electrode region, the collector electrode region and the like are opened, and a metal such as Al is vapor-deposited to form the base electrode 11, the emitter electrode 12 and the collector electrode 13. Is obtained.

When viewed from above, the shape of the transistor is such that the emitter, the base, the n ⁻ type (collector) region, and the collector are arranged concentrically or in a square ring shape from the center. The SiC used in this example is drawing attention as a future transistor material. FIG. 4 compares drift velocities of electrons in semiconductors, which are promising transistor materials, as a function of electric field strength.

III-V group compound semiconductors such as GaAs and I
nP is a group IV element S in a region where the electric field strength is relatively low.
It has a larger drift velocity than i, IV, and compound semiconductor SiC, and is excellent in high speed. However, in the high electric field intensity region, the electron transits to the upper subband (L valley) and the effective mass increases, so that the drift velocity decreases.

In the region of 10 ⁵ V / cm or higher, SiC is advantageous. In a highly integrated IC, if the size of each element is miniaturized and the power supply voltage is the same as the conventional one, driving under a high electric field is inevitable, but in this case, SiC is advantageous.

Further, β-SiC has a bandgap twice that of Si and is strong against high temperature operation and large current drive, so that a high temperature resistant device that operates even at high temperature and a high breakdown voltage device with high breakdown voltage can be formed.

Furthermore, SiC has an important feature that it has a thermal conductivity three times or more that of Si and has a low dielectric constant. These characteristics are the reasons why SiC is evaluated to be excellent as the ultimate IC material driven under severe conditions.

In the above embodiments, Si is used as the semiconductor material.
C, Si was used as the second conductive material. As a combination of materials having greatly different oxidation rates under the same conditions, other than this, for example, Si as a semiconductor material and W as a conductive material
Alternatively, WSi ₂ can be used.

When these two conductive materials were subjected to wet oxidation at 1000 ° C., the oxide film thickness on Si was 700 A after 80 minutes of thermal oxidation, whereas W or WSi ₂
Above, an oxide film thickness of 2600A is obtained.

Therefore, if W (or WSi ₂ ) is used in place of the B-doped polysilicon layer 8 and an n ⁻ -type Si layer is used in place of the n ⁻ -type SiC layer 2 in the step of FIG. In the step 2 (B), a thick oxide film is obtained on the side wall of the opening and a thin oxide film is formed on the bottom of the opening, as in the previous embodiment.

Therefore, in the step of FIG. 2C, the insulating substrate 1 can be easily exposed at the bottom of the opening by anisotropic etching without damaging the shape of the opening. It is a major point of the present invention to use a combination of a transistor active region forming material and an opening side wall forming material having different oxidation rates.

Other material combinations include C (diamond) or BN (semiconductor material) and Si (conductive material).
Etc. are possible. In addition, in the above-mentioned embodiment, the conductivity type of the semiconductor material at the bottom of the opening, that is, the conversion of the n ⁻ type SiC layer 2 into the p type SiC region 6 by ion implantation was performed before forming the side wall of the conductive material.

However, since the sample is kept at a constant high temperature in the side wall forming step and the subsequent thermal oxidation step, there is a possibility of causing lateral diffusion of the p-type impurity. In such a case, the step of converting the conductivity type of the main semiconductor layer is performed after the sidewall forming step,
Alternatively, it is preferably performed after the thermal oxide film forming step.

Further, in the above-mentioned embodiment, after the thermal oxidation process of the side wall and the bottom of the opening, the oxide film at the bottom of the opening and the semiconductor layer in the region immediately below are removed by etching, and then polysilicon 9 is formed. The impurities contained in this material were laterally diffused.

However, as shown in FIG. 5, after the thermal oxidation step, only the thin thermal oxide film at the bottom of the opening is removed by etching, the n ⁺ type polysilicon layer 9 is deposited on the thin thermal oxide film, and the opening is formed by diffusion. The p-type SiC region 6 at the bottom is converted to the first conductivity type (in the case of the previous embodiment, the cross section of the p-type SiC is changed to the n ⁺ -type SiC).
It is also possible to form the emitter and base regions by heat treatment after converting to the region 15. The same method is possible when using other materials.

Alternatively, unlike the previous embodiment, the conductivity conversion of the first semiconductor layer at the bottom of the opening is changed last, that is, as shown in FIG.
It can also be performed in the step (D). In this case, the semiconductor layer (n ⁻ -type SiC) at the bottom of the opening is left unetched, and the second conductivity type impurity (acceptor impurity) is first ion-implanted to thermally diffuse in the lateral direction.
A base region is formed, and then a high-concentration first conductivity type impurity (donor impurity) is ion-implanted and thermally diffused in the lateral direction again to form an emitter region. afterwards,
For example, P-doped n-type polysilicon 9 may be deposited and a metal electrode may be formed thereon. Further, the P-doped n-type polysilicon 9 may be omitted.

Further, as shown in FIG. 2C, after removing the p-type semiconductor region in the opening, an n-type semiconductor may be epitaxially grown on the side wall of the p-type semiconductor region. Further, although β-SiC is used in the above embodiment, SiC having another crystal structure may be used.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various changes, improvements, combinations and the like can be made.

[0060]

As described above, according to the present invention,
Since the base / emitter junction area is determined only by the film thickness of the growth layer without using patterning by photolithography, C _CB and C _BE can be reduced, which contributes to speeding up.

Further, the base width can be determined by the thickness of the side wall, and the base width can be made narrower than before. This also contributes to speeding up. By adopting the SOI structure, the matching property with the MOS transistor is improved and the Bi-CMOS circuit is easily formed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the first half of a bipolar transistor manufacturing process according to an embodiment.

FIG. 2 is a cross-sectional view showing the latter half of the bipolar transistor manufacturing process according to the embodiment.

FIG. 3 is a structural cross-sectional view around a base and an emitter of a conventional bipolar transistor.

FIG. 4 is a graph of calculation results showing the electric field dependence of the electron drift velocity of a semiconductor material for transistor structure.

FIG. 5 is a cross-sectional view showing another embodiment of the present invention.

[Explanation of symbols]

1 Insulating Substrate 2 n ^- Type SiC Layer 2a SiO ₂ Layer 3 CVDSiO ₂ Layer 4 p-type Polysilicon Layer 5 CVDSiO ₂ Layer 6 p-type SiC Region 6a p-type SiC Base Region 7 Al Ion 8 p-type Polysilicon Layer 8a Heat Oxide SiO ₂ layer 9 n-type polysilicon layer 10 n ⁺ type SiC emitter region 11 base electrode 12 emitter electrode 13 collector electrode 14 n ⁺ type SiC collector region 47 external base region 48 internal base region 49 emitter region 50 p-Si substrate 51 Epitaxial layer 52 Embedded collector region 53 Field oxide film 55 SiO ₂ layer 57 Polysilicon layer 59 (for base extraction electrode) Side wall polysilicon 61, 63 SiO ₂ layer 65 Doped polysilicon layer 67 Emitter electrode 69 Base electrode

Claims (6)

[Claims] 1. A step of preparing a substrate having a first conductivity type main semiconductor layer on an insulator substrate, and a first insulator layer, a first conductor layer and a second layer on the main semiconductor layer. Stacking the insulating layers in this order, providing an opening of a predetermined size that extends from the second insulating layer to the surface of the main semiconductor layer, and exposing the main semiconductor layer region by the opening. To a second conductivity type to form a base region, and a sidewall made of a second conductor layer having a higher oxidation rate under the same conditions as that of the first semiconductor is provided in the opening. A step of forming an oxide film of a second conductor on the side wall surface by thermal oxidation, and a main semiconductor generated by the thermal oxidation using the oxide film of the second conductor on the side wall of the opening as a mask. The step of etching the oxide film of the layer, and the first conductivity type impurity Method of manufacturing a bipolar transistor comprising the steps of: an emitter region formed in the opening portion of the main semiconductor layer containing. 2. The method of manufacturing a bipolar transistor according to claim 1, further comprising the step of etching the main semiconductor layer below the oxide film of the main semiconductor layer in the opening, after the step of etching. 3. The method of manufacturing a bipolar transistor according to claim 1, wherein the main semiconductor layer is SiC and the second conductor layer is polysilicon. 4. A step of preparing a substrate having a first conductivity type main semiconductor layer on an insulator substrate, and a first insulator layer, a first conductor layer and a second layer on the main semiconductor layer. The step of stacking the insulating layers in this order, the step of providing an opening of a predetermined size that extends from the second insulating layer to the surface of the main semiconductor layer, and the step of comparing the opening with the first semiconductor. A sidewall of a second conductor layer having a higher oxidation rate under the same conditions, a step of forming an oxide film of a second conductor on the sidewall surface by thermal oxidation, and a sidewall of the opening sidewall. Using the oxide film of the second conductor as a mask, the step of etching the oxide film of the main semiconductor layer generated by the thermal oxidation, and the base region of the second conductivity type and the emitter region of the first conductivity type as the main semiconductor layer. Of the bipolar transistor including the step of forming in the opening of Production method. 5. A step of preparing a substrate having a first semiconductor layer of a first conductivity type on an insulating substrate, and a first insulator layer, a first conductor layer and a second layer on the main semiconductor layer. The step of stacking the insulating layers in this order, the step of providing an opening of a predetermined size that extends from the second insulating layer to the surface of the main semiconductor layer, and the step of comparing the opening with the first semiconductor. A sidewall of a second conductor layer having a higher oxidation rate under the same conditions, a step of forming an oxide film of the second conductor on the surface of the sidewall by thermal oxidation, and a main semiconductor of the opening Converting the layer region to a second conductivity type and forming a base region; and an oxide film of the main semiconductor layer formed by the thermal oxidation using the oxide film of the second conductor on the sidewall of the opening as a mask. Etching the first conductive type emitter region to the main semiconductor layer. Method of manufacturing a bipolar transistor comprising the steps of forming the mouth portion. 6. A step of preparing a substrate having a first semiconductor layer of a first conductivity type on an insulating substrate, and a first insulator layer, a first conductor layer and a second layer on the main semiconductor layer. The step of stacking the insulating layers in this order, the step of providing an opening of a predetermined size that extends from the second insulating layer to the surface of the main semiconductor layer, and the step of comparing the opening with the first semiconductor. A side wall made of a second conductor layer having a higher oxidation rate under the same conditions, and converting the main semiconductor layer region exposed by the opening to a second conductivity type to form a base region. A step of forming an oxide film of a second conductor on the side wall surface by thermal oxidation, and a main semiconductor generated by the thermal oxidation using the oxide film of the second conductor on the side wall of the opening as a mask. The step of etching the oxide film of the layer, and the first conductivity type impurity Method of manufacturing a bipolar transistor comprising the steps of: an emitter region formed in the opening portion of the main semiconductor layer containing.