JPH0622237A - Multi-screen television receiver and its memory device - Google Patents

Abstract

PURPOSE:To reduce the memory capacity in a video signal processing circuit by using a frame memory used to produce a frame delay signal in common for a memory used for a time axis compression circuit of an input video signal. CONSTITUTION:The television receiver is provided with plural field memories 54-56 storing an inter-frame interpolation signal for an input video signal and introducing its delay signal to form the memory device to obtain the frame delay signal and the input video signal whose time axis is compressed from the delay signal. Furthermore, the video signal for a small pattern is used for the input video signal and the video signal for the small pattern introduced from the memory device and whose time axis is compressed is inserted to the video signal of the master pattern to obtain a multi-screen television signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-screen television receiver capable of displaying a plurality of screens on a common display surface at the same time and a memory device used for the same.

[0002]

2. Description of the Related Art As a method for compressing a transmission signal band of a television signal, a multi-subsample transmission method using interfield and interframe offset subsampling is known. Then, as one of the multiple sub-sample transmission methods, MUSE (Multiple Su
b-Nyquist Sampling Encodi
ng) is disclosed in, for example, JP-A-61-2648.
It is proposed as described in Japanese Patent Publication No. 89.

FIG. 7 shows the configuration of a signal processing circuit (encoder) on the transmitting side. In the figure, input terminal 1
The input signal supplied to the A / D converter 2 is 48.6.
It is sampled at a sampling frequency of MHz and converted into a digital signal. FIG. 8A shows the signal band at this time. In FIG. 8, the horizontal axis represents the horizontal component H and the vertical axis represents the vertical component V.

The output signal of the A / D converter 2 shown in FIG. 7 is supplied to the interfield prefilter 3. In the inter-field pre-filter 3, as the processing of the still image area, the high frequency component in the diagonal direction of the screen is removed as shown in FIG. 8B.

The output signal of the inter-field pre-filter 3 is supplied to the sub-sampling circuit 4. In this sub-sampling circuit 4, inter-field offset sub-sampling is performed at a sampling frequency of 24.3 MHz. In this case, the signal in the band of 12.15 MHz or higher is folded back, and the signal band becomes as shown in FIG. 8C.

Further, the output signal of the sub-sampling circuit 4 is supplied to the sampling frequency conversion circuit 5, and the sampling frequency thereof is from 24.3 MHz to 32.4 MHz.
Is converted to. In this case, the signal band remains as shown in FIG. 8C.

On the other hand, the output signal of the A / D converter 2 is supplied to the intra-field pre-filter 6. In the in-field pre-filter 6, as processing of the moving image area,
As shown in D, the band is limited to 12.15 MHz.

The output signal of the in-field pre-filter 6 is supplied to the sampling frequency conversion circuit 7,
The sampling frequency is from 48.6 MHz to 32.4
Converted to MHz. In this case, the signal band remains in the state shown in FIG. 8D.

The sampling frequency conversion circuit 5 is also provided.
The output signals of 7 and 7 are supplied to the linear mixing circuit 8. Further, the output signal of the A / D converter 2 is supplied to the motion detection circuit 9. In this motion detection circuit 9, the absolute value of the interframe difference is subjected to non-linear processing to detect the amount of motion. Then, the detection signal of this motion detection circuit 9 is supplied to the linear mixing circuit 8 as a control signal, and this linear mixing circuit 8
Then, the output signals of the sampling frequency conversion circuits 5 and 7 are mixed at a ratio according to the motion amount.

The output signal of the linear mixing circuit 8 is supplied to the sub-sampling circuit 10. In this subsampling circuit 10, interframe offset subsampling is performed at a sampling frequency of 16.2 MHz. In this case, the signal band as shown in FIG. 8C of the still image system is as shown in FIG. 8E by folding back the band of 8.1 MHz or more.

On the other hand, in the signal band of the moving picture system as shown in FIG. 4D, the band of 8.1 MHz or more is folded back to be as shown in FIG.

Further, the output signal of the sub-sampling circuit 10 is converted into an analog signal by the D / A converter 11 and then led to the output terminal 13 via the transmission line filter 12 and sent out to the transmission line. This transmission line filter 12 is supposed to have a cosine roll-off characteristic at 8.1 MHz.

MU transmitted from the transmitting side shown in FIG.
A multi-screen television receiver that receives an SE transmission signal and interpolates between frames to generate a small-screen video signal has already been filed, and FIG. 9 is a block diagram thereof.

In FIG. 9, the digitized first M
The USE transmission signal is supplied to the interframe interpolation circuit including the switch 21 and the frame memory 22 via the terminal 20. The switch 21 switches between an input signal from the terminal 20 and a frame delay signal from the frame memory 22 to perform interframe interpolation. The inter-frame interpolated signal is supplied to the inter-field interpolating circuit including the field memory 24 and the interpolating circuit 25, and inter-field interpolated to form a still image signal.

On the other hand, the signal from the terminal 20 is supplied to the field interpolating circuit 26 and field-interpolated to form a moving picture signal. The signal interpolated between frames is directly supplied to one terminal of the motion detection circuit 23, and further supplied to the other terminal via the frame memory 22. Then, the motion detection signal is formed by the inter-frame difference between these two signals. The motion detection signal, the still image signal from the interpolation circuit 25, and the moving image signal from the field interpolation circuit 26 are supplied to the linear mixing circuit 27, and the still image signal and the moving image signal are linearized according to the motion detection signal. Are mixed to form a first video signal. With the above signal processing circuit 28, M
Normal signal processing of the USE receiver is performed.

On the other hand, the digitized second MUSE transmission signal is supplied to the interframe interpolation circuit including the switch 40 and the frame memory 41 via the terminal 29. The switch 40 switches between the input signal from the terminal 29 and the frame delay signal from the frame memory 41 to perform interframe interpolation. By this inter-frame interpolation processing, the folding component of FIG. 8E showing the signal band of the still image system of the MUSE transmission signal is 1
The signal band is restored up to 2.15 MHz and becomes the signal band shown in FIG. 10A.

Further, the folding component of FIG. 8F showing the signal band of the moving image system of the MUSE transmission signal is not restored and remains the folding signal band as shown in FIG. 10B. But,
The deterioration of the S / N ratio of the video signal due to the folding back of the signal band is largely influenced by the still image portion having a large folding component to the low frequency band. Therefore, according to this circuit, most of the deterioration of the S / N of the video signal is eliminated by reducing the aliasing component to the low frequency band by the inter-frame interpolation processing. The signal interpolated between frames forms a second video signal via the time base compression circuit 32.

A small screen signal processing circuit has been disclosed in which the small screen field memory included in the time axis compression circuit 32 is composed of three pieces so that the memory read address does not overtake the write address. Filed as "TV receiver". The memory included in the time axis compression circuit 32 of the circuit shown in FIG. 9 will be described as a three-field memory, but a two-field memory, a four-field memory, or the like does not constitute a small-screen signal processing circuit having an appropriate image quality. it can.

The second MUSE transmission signal supplied from the terminal 29 is also supplied to the second control circuit 33, and is written in the memory included in the time axis compression circuit 32 in synchronization with the synchronization signal included in this signal. Timing is generated, and the inter-frame interpolation signal supplied to the time axis compression circuit 32 is written in the memory in response to the write timing signal.

First MUS supplied from one terminal 20
The E transmission signal is supplied to the first control circuit 31, the read timing to the memory is generated in synchronization with the synchronization signal included in the signal, and the memory of the time axis compression circuit 32 is responsive to the read timing signal. The time axis compressed signal is read to form a second video signal. The circuit 42 in this portion corresponds to a portion that performs signal processing for a small screen.
The first video signal and the second video signal are supplied to the insertion circuit 35, and a dual-screen high-definition television signal in which the second video signal is included in a small area of the first video signal is output to the terminal 36. To do.

[0021]

According to the above configuration, the small screen signal processing circuit requires the frame memory of the interframe interpolating circuit and the plurality of field memories used for the time axis compression circuit, and thus the required memory capacity is large. There is a problem that the circuit configuration becomes complicated and expensive. An object of the present invention is to reduce the required memory capacity and the circuit scale.

[0022]

In order to solve the above problems, the present invention uses an interframe interpolated signal as an input signal and sequentially stores the input signal for each field.
A memory means composed of a plurality of field memories for deriving a delay signal of the input signal, a first switching means for deriving a frame delay signal from the delay signal derived by the memory means, an input video signal and the frame delay. Second switching means for switching the signal to derive the inter-frame interpolation signal, and third switching means for deriving the data from the field memory which is not being written among the delay signals derived from the memory means. , And a time axis compression circuit for time axis compression of the pixel data derived by the third switching means.

In a multi-screen television receiver in which a second television screen based on the second video signal is displayed as a small screen on a part of the first television screen based on the first video signal, The memory device that uses the second video signal as an input video signal; first control means that controls reading of data from the memory device with a clock that is synchronized with a synchronization signal of the first video signal; A small screen signal processing circuit comprising second control means for controlling writing of data to the memory device with a clock synchronized with the synchronizing signal of the second video signal is provided, and a small screen signal processing circuit derived from the small screen signal processing circuit is provided. The second video signal for the screen is the first
The configuration is such that an insertion circuit for inserting into the video signal of is provided.

[0024]

Since the present invention has the above-mentioned structure, the input video signal is switched to the frame delay signal by the second switching means and becomes an interframe interpolating signal, which is repeatedly stored in a plurality of field memories successively for each field. A delay signal is derived from the plurality of field memories, and the delay signal is guided to the first switching means to derive the frame delay signal.

On the other hand, the delay signals from the plurality of field memories are led to the third switching means to derive a plurality of pixel data from the field memory which is not being written,
A time axis compression circuit compresses the time axis of this signal to derive a signal obtained by compressing the time axis of the input video signal. Therefore, the plurality of field memories described above can be used as a memory for deriving a frame delay signal, and can also be used as a memory of a circuit for compressing the time axis of an input video signal.

If the memory device is used in the small screen signal processing circuit of the multi-screen television receiver, the second video signal for the small screen becomes the input video signal of the memory device.
Then, in the plurality of field memories in the memory device, the second video signal is written by the second control means at a clock synchronized with the synchronizing signal of the second video signal, and the first control means performs the first video signal. The second video signal is read at the clock synchronized with the sync signal of the video signal.

The data of the second video signal read from the plurality of field memories is derived via the first switching means as a frame delay signal for producing an interframe interpolation signal, and at the same time, the third switching circuit. Is introduced to the time axis compression circuit and the time axis is compressed as a small screen signal. Then, the time-axis-compressed second video signal for the small screen is guided to the insertion circuit and inserted into the first video signal to become a multi-screen video signal.

[0028]

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, parts corresponding to the configuration shown in FIG. 9 described as the above-mentioned conventional example are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, 50 is a second screen signal which is a small screen image signal.
Video signal and the frame delay signal 5 of the second video signal
2 is a 3 field memory circuit for switching between 2 and performing inter-frame interpolation, and compressing the second video signal on the time axis to derive a second video signal 53 suitable for a small screen video signal. A small-screen signal processing circuit for the second video signal, which includes the three-field memory circuit 50, the first control circuit 31, the second control circuit 33, and the switch 40.

In FIG. 1, the digitized first M
The USE transmission signal is supplied to the terminal 20, the signal processing circuit 28 performs the usual signal processing of the MUSE receiver as in the conventional example, and the first video signal is output from the linear mixing circuit 27.

On the other hand, the digitized second MUSE transmission signal is supplied to one terminal of the switch 40 via the terminal 29. The frame delay signal 52 from the 3-field memory circuit 50 is supplied to the other terminal of the switch 40. The switch 40 switches both of the above signals to perform interframe interpolation and supplies the output to the 3-field memory circuit 50.

The three-field memory circuit 50 forms the frame delay signal 52 and the time-compressed second video signal 53. The terminals 20, 2
The first and second MUSE transmission signals supplied from 9 are the first
It is also supplied to the control circuit 31 and the second control circuit 33, respectively, and generates a timing signal in synchronization with the synchronization signal included in the signal. The first control circuit 31 and the second control circuit 33 control the reading and writing of the 3-field memory 50 using the timing signals.

Next, details of the three-field memory circuit 50 will be described in detail with reference to the block diagram shown in FIG. In FIG. 2, reference numerals 54, 55 and 56 are field memories, and each of the field memories 54, 55 and 56 is provided with three blocks 1, 2 and 3, respectively.
There are three sub-blocks 1-, 1-, 1 in 2 and 3, respectively.
-, 2-, 2-, 2-, 3-, 3-, 3-
To provide. Therefore, a total of 27 sub-blocks are provided for each of the field memories 54, 55, 56.

The output side terminal of the switch 40 is connected to the input terminals of each of the sub-blocks 1--3.
The outputs of the sub blocks 1 to 3 in the blocks 1, 2 and 3 of the field memory 54 are the switches 61.
Of the sub-blocks 1 to 3 in each of the blocks 1, 2, and 3 of the field memory 55 to the terminal of the switch 61, and each of the blocks 1, 2, and 3 of the field memory 56. The output of each of the sub-blocks 1 to 3 in FIG.
Connected to the terminal. Then, the output of the switch 61 is led to the output terminal 53 as a second video signal for a small screen through the two-dimensional LPF circuit 62.

Also, the first sub-blocks 1-, 2- in each of the blocks 1, 2, 3 of the field memory 54.
, 3-outputs of the switches 57-1, 57-2, 57- constituting the block 57 of the switching circuit, respectively.
3 and the outputs of the second sub-blocks 1-, 2-, 3- of the blocks 1, 2, 3 are connected to the switches 57-1, 57-2, 57-3, respectively.
Of the third sub-block 1-, 2-, 3- of the blocks 1, 2, 3 respectively connected to the second terminal of the switch 57-1, 57-2, 57-3. 3 terminals. And each of the above switches 57
The output terminals of -1, 57-2, and 57-3 are connected to the input terminals of the switch 57-0 that constitutes the block 57, respectively.

The outputs of the sub-blocks 1 to 3 in the other field memories 55 and 56 are also blocks 58 and 5 which constitute switching circuits provided corresponding to the field memories as in the case of the field memory 54.
9 switches 58-1, 58-2, 58-3 and 59
-1, 59-2, 59-3, and the output of each switch is connected to each input terminal of the switches 58-0, 59-0 provided for each of the blocks 58, 59.

Then, the respective switches 57-0, 58-
The frame delay signals derived at the output terminals of 0 and 59-0 are connected to the input terminals a, b and c of the switch 60, respectively.
The output terminal is led to the input terminal b of the switch 40.

The 3-field memory circuit 50 has the above-mentioned structure, and its operation will be described below. First of all, horizontal,
A case where the second video signal is formed by compressing the time axis to 1/3 in the vertical direction will be described with reference to FIGS. 1 to 5.

As shown in FIG. 3A1, the MUSE transmission signal is supplied to the a-side terminal of the switch 40 in a clock unit of 16.2 MHz. Since the MUSE transmission signal is subjected to line offset sub-sampling, for example, when signals of odd-numbered pixels are transmitted on the X-th line, the X-th pixel is transmitted.
In the +1 line, signals of even-numbered pixels are sent. In the figure, X to X + 2 represent line numbers, and the numbers represent pixel numbers. Hereafter, this is repeated by changing the line.

On the other hand, the terminal on the side b of the switch 40 is shown in FIG.
A frame delay signal 52 in units of 32.4 MHz clock is supplied as shown in FIG. FIG. 3C1 shows the switch 40
Of the switching timing signal, the H level and the L level are switched in a clock unit of 32.4 MHz, and the phase thereof is inverted by the line change. For example, when it is at H level, the signal on the a side is selected, and when it is at the L level, the signal on the b side is selected. Therefore, the switch 40 outputs the signal interpolated between frames as shown in FIG. 3D1. The inter-frame interpolation signal D1 is a 3-field memory circuit 50.
Input to the field memories 54, 5 as shown in FIG.
5,56.

The above field memories 54, 55, 56
Is composed of blocks 1, 2, and 3, and each block is composed of sub-blocks. Writing to each of the above field memories 54, 55 and 56 is performed by a write timing signal from the second control circuit 33 shown in FIG. Each field memory 54, 5
5, 56 are nine sub-blocks 1-, 1-, 1-
, 2-, 2-, 2-, 3-, 3-, 3-
However, the address ranges of the sub-blocks 1 to 3 are the same, and the same address of all sub-blocks can be designated at the same time.

Assuming that the inter-frame interpolation signal D1 is first written in the field memory 54, the WA (write address) of blocks 1, 2, and 3 in the Xth line.
The signal is updated as Y, Y + 1, Y + 2, ... In 10.8 MHz clock units as shown in FIG. 3E1. Note that Y, Y + 1, Y + 2, ... Represent address numbers.

The next X + 1th and X + 2th addresses also specify the same address as the Xth line in a clock unit of 10.8 MHz. On the subsequent X + 3 to X + 5 lines, the address is designated in order from the address Y'following the address last designated on the X to X + 2 lines. The address is updated as described above until the end of the field.

On the other hand, blocks 1, 2, and 3 are shown in FIG.
1, WE (write enable) signals indicated by H1 are supplied. At line X, as shown in FIG. 3F1, 32.4M
Sub-block 1 of block 1 in Hz clock units
, 1-, 1- are sequentially write-enabled.
This is repeated every three clock cycles.

In the next X + 1th line, the block 1 is unenabled as shown in FIG. 3F1, and the sub-blocks 2-, 2-, 2- of the block 2 are sequentially arranged in units of a clock of 32.4 MHz as shown in FIG. 3G1. Write enable is enabled. This is repeated every three clock cycles.

In the subsequent X + 2 line, the block 2 is unenabled as shown in FIG. 3G1, and the sub-blocks 3-, 3-, 3- of the block 3 are sequentially written in the unit of 32.4 MHz clock as shown in FIG. 3H1. It will be enabled. This is repeated every three clock cycles.

In the subsequent X + 3 line, the block 3 is unenabled, and the block 1 is again write enabled. After that, the operation of the Xth to X + 2th lines is repeated in a 3-line cycle until the end of the field. Therefore, in the X-th line of the interframe interpolation signal of FIG. 3D1, 1, 4 ′, 7,
The signal of ... Is shown in FIG.
2 ', 5, 8', ...
Is written to sub-block 1- as shown at J1,
The signals of 3, 6 ', 9, ... Are written in sub-block 1- as shown in FIG. 3K1.

In the X + 1th line, 1 ', 4, 7', ...
.. signals are sub-block 2-as shown in FIG.
, And the signals of 2, 5 ', 8, ...
Is written to sub-block 2- as shown in 3 ', 3',
The signals 6, 9 ', ... Are written in the sub-block 2-, as shown in N1 of FIG.

The Xth inter-frame interpolated signal shown in FIG. 3D1
In the +2 line, the signals 1, 4, 4 ', 7, ...
Is written in sub-block 3- as shown in 1,
The signals 2 ', 5, 8', ... Are written in the sub-block 3-as shown in P1 of FIG.
The signal of * is written in the sub-block 3-as shown in Q1 of the same figure.

Thereafter, the inter-frame interpolated signal shown in FIG.
It is repeatedly written to a few. When the writing of the signal of one field is completed, the signal of the next field is written in the field memory 55 as described above, and the signal of the next field is written in the field memory 56 as described above. After that, the field memories 54, 55, and 5 are carried out at a 3-field cycle.
6 is repeatedly written.

Each of the field memories 54, 55 and 56 has two systems of read address lines and read data lines, and they can be read out asynchronously with each other. The first read system that forms the frame delay signal 52 is controlled by the read timing signal from the second control circuit 33. In the Mth field in which the field memory 54 is being written, the frame delay signal is read from the field memory 55. In the M-th feed, the switching timing signals of the switches 58-1 to 58-3 cause 32.4 MHz for each line as shown in FIG. 4R1.
Select terminal ,, repeatedly in clock units of.

On the other hand, as the switching timing signal of the switch 58-0, as shown in FIG. 4S1, the respective terminals are selected in the Xth to X + 2th lines. Thereafter, this is repeated with a 3-line cycle until the end of the field, and the frame delay signal 101 is formed as shown in FIG. 4T1.

In the (M + 1) th field in which the field memory 55 is being written, the frame delay signal is read from the field memory 56. In the (M + 1) th field, each line is set to 32. by the switching timing signals of the switches 59-1 to 59-3 as shown in FIG. 4U1.
The terminal is repeatedly selected in units of 4 MHz clock.

On the other hand, the switching timing signal of the switch 59-0 selects the respective terminals on the lines X to X + 2 as shown in FIG. 4V1. Thereafter, this is repeated with a 3-line cycle until the end of the field, and the frame delay signal 102 is formed as shown in FIG. 4W1.

In the (M + 2) th field in which the field memory 56 is being written, the frame delay signal is read from the field memory 54. In the (M + 2) th field, as shown in FIG. 4X1, 32.
The terminal is repeatedly selected in units of 4 MHz clock.

On the other hand, the switching timing signal of the switch 57-0 selects the respective terminals on the lines X to X + 2 as shown in FIG. 4Y1. Thereafter, this is repeated with a 3-line cycle until the end of the field, and the frame delay signal 100 is formed as shown in FIG. 4Z1. Switch 6
The switching timing signal of 0 selects terminals b, c, and a in the Mth to M + 2th fields, respectively, as shown in FIG. 4A2. After that, this is repeated with a cycle of three fields, and the first
The frame delay signal 52 is formed from the read system of.

On the other hand, the second read system for forming the second video signal 53 shown in FIG. 1 is controlled by the read timing signal from the first control circuit 31. Data for 9 pixels of the sub-blocks 1 to 3 of the field memories 54 to 56 are respectively supplied to the terminals to of the switch 61 shown in FIG. One of the terminals (1) to (3) is selected by the switching timing signal of the switch 61, and the data for 9 pixels from the field memory which is in the same field as the first video signal and is not being written is supplied to the two-dimensional LPF circuit 62. To do.

The two-dimensional LPF circuit 62 adds the product of the supplied horizontal and vertical 3 × 3 9 pixel data as shown in FIG. 5 by the respective coefficients shown in FIG. The two-dimensional LPF is configured by calculating the data of one pixel compressed in the time axis to 1/3. The output of the two-dimensional LPF circuit 62 is supplied to the terminal 53 as a second video signal. The first video signal and the second video signal are supplied to the insertion circuit 35, and a dual-screen high-definition television signal in which the second video signal is included in a small area of the first video signal is output to the terminal 36. To do.

Next, in general, M '/ M (however, M'<M) in the horizontal direction and N '/ N (however, N'<N) in the vertical direction.
The configuration of the 3-field memory when the time axis is compressed to form the second video signal will be briefly described with reference to FIGS. 1 and 6. However, M, M ′, N, and N ′ are natural numbers.

A signal interpolated between frames is output from the switch 40 in the same manner as in the first embodiment. The inter-frame interpolation signal is input to the 3-field memory circuit 150 and supplied to the field memories 154, 155, 156. Each field memory has blocks 1, 2, ...
, N, and each block is composed of sub-blocks, ..., M.

The inter-frame interpolation signal is the second control circuit 3
In accordance with the write timing signal from 3, the field memories 154, 155, and 156 are sequentially written in the field memories on a field-by-field basis. In each of the field memories 154, 155, and 156, the signal of each field is sequentially written as blocks 1, 2, ..., N on a line-by-line basis, and is repeated every N line cycles.

Further, the signal of each line is sequentially written in sub-blocks, ..., M in units of a clock of 32.4 MHz, and is repeated in M clock cycles. The first read system that forms the frame delay signal 52 is controlled by the read timing signal from the second control circuit 33. Switches 157-1, 157-2, ..., 1
57-N, switches 158-1, 158-2, ...
158-N, switches 159-1, 159-2, ...
.. 159-N forms signals on each line by repeatedly selecting signals from its input terminals, each sub-block supplied to M, ..., M in units of 32.4 MHz clock To do.

Switches 157-1, 157-2, ...
.157-N, switches 158-1, 158-2 ,.
...., 158-N, switches 159-1, 159-2,
The output signal of 159-N is the switch 157-0,
Input terminals 158-0, 159-0, ..., N
Is supplied to. Switches 157-0, 158-0, 15
.., N are repeatedly selected in units of lines to form signals 163, 164, 165 of the respective fields.

The switch 160 selects the field signals 163, 164, 165 supplied to the input terminals a, b, c in field units to form the frame delay signal 52.

On the other hand, the second video signal 53 forming the second video signal 53 is formed.
The read system of is controlled by a read timing signal from the first control circuit 31. Data for N × M pixels of the sub blocks 1 to NM of the field memories 154 to 156 are supplied to the terminals ˜ of the switch 161 respectively. One of the terminals (1) to (3) is selected by the switching timing signal of the switch 161, and the data for N × M pixels from the field memory in the same field as the first video signal and not being written is two-dimensionally LP.
It is supplied to the F circuit 162.

The two-dimensional LPF circuit 162 forms N ′ × M ′ pixel data from the N × M pixel data and stores it in a memory (not shown). The data of the N'line stored in this memory is output to the terminal 53 over the N'line at an appropriate timing. In this way, the second video signal 5
3 is formed. Then, the first video signal and the second video signal are supplied to the insertion circuit 35, and a dual-screen high-definition television signal in which the second video signal is included in a small area of the first video signal is supplied to the terminal 36. Output to.

[0066]

Since the present invention has the above-mentioned configuration, the frame memory of the interframe interpolating circuit used in the small screen signal processing circuit and the plural field memories of the time axis compression circuit can be shared, so that the memory can be used. The capacity can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an embodiment of a main part of the present invention.

FIG. 3 is a time chart used for explaining the operation of the present invention.

FIG. 4 is a time chart used for explaining the operation of the present invention.

FIG. 5 is an operation explanatory diagram of the two-dimensional LPF used in the present invention.

FIG. 6 is a block diagram of another embodiment of the main part of the present invention.

FIG. 7 is a block diagram of a signal processing circuit on the transmission side.

FIG. 8 is a diagram showing a signal band of each unit used for explaining the operation of the signal processing circuit on the transmission side.

FIG. 9 is a configuration diagram of a conventional example.

FIG. 10 is a diagram showing a signal band used for explaining an operation of a conventional example.

[Explanation of symbols]

 31 first control circuit 33 second control circuit 35 insertion circuit 40 switch 50 3 field memory circuit 51 small screen signal processing circuit 54, 55, 56 field memory 57, 58, 59 block 60 switch 61 switch 62 two-dimensional LPF

Claims (2)

[Claims] 1. A memory means comprising a plurality of field memories for sequentially and repeatedly storing the input signal for each field using an interframe interpolated signal as an input signal, and the memory means. First switching means for deriving a frame delay signal from the derived delay signal, and second for deriving the interframe interpolation signal by switching between the input video signal and the frame delay signal.
Of the delay signal derived from the memory means, third switching means for deriving data from the field memory which is not being written, and pixel data derived from the third switching means. A memory device comprising a time axis compression circuit for time axis compression. 2. A multi-screen television receiver in which a second television screen based on a second video signal is displayed as a small screen on a part of a first television screen based on a first video signal. The memory device according to claim 1, wherein the second video signal is used as an input video signal, and reading of data from the memory device is performed using the first video signal.
And a second control means for controlling the writing of data to the memory device with a clock synchronized with the synchronization signal of the second video signal. A multi-screen television including a small-screen signal processing circuit, and an insertion circuit for inserting a small-screen second video signal derived from the small-screen signal processing circuit into the first video signal. John receiver.