JPH06217351A - Device for calculating correction value for mis-convergence - Google Patents

Abstract

PURPOSE:To exactly obtain a correction value for mis-convergence by reading test pattern data from a storage section synchronously with clock signals of the number equal to the number of dots of a liquid crystal display panel so as to allow the device to cope with one dot of the liquid crystal display panel. CONSTITUTION:A selector 11 selects any of a horizontal drive signal, a vertical drive signal from a synchronizing signal generator 9, a PLL circuit 10 and a liquid crystal projector 1 and a sampling clock of the same number as the number of dots of the liquid crystal panel. An address counter 12 generates an address based on the selection and reads a test pattern synchronously with the sampling clock from a ROM 13 for each of R, G, B colors to generate a digital video signal. An analog video signal converted in a timing of a sampling clock at a D/A converter 14 is fed to a liquid crystal display panel 8 and an RGB encoder 15 and a composite video signal is generated by a composite synchronizing signal and a subcarrier from the synchronizing signal generator received simultaneously. Thus, a video image is surely displayed in the unit of one dot and mis-convergence is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a convergence deviation correction value calculating device for calculating a convergence deviation correction value of a liquid crystal projector.

[0002]

2. Description of the Related Art A liquid crystal projector is configured to project an image on a screen according to light transmitted through a liquid crystal panel incorporated therein. In such a liquid crystal projector, convergence deviation and focus deviation occur due to the fixed positions of the liquid crystal panel and other optical parts. The influence of such convergence and focus shift directly appears in the projected image. Therefore, in order to eliminate such convergence deviation, in the production line of the liquid crystal projector, the adjustment operator adjusts the fixed position of the above-mentioned component while watching the projected image, or shoots the projected image with, for example, a video camera. After converting into an electric signal, signal processing is performed to calculate a deviation correction value, and the adjusting operator adjusts the fixed position of the component based on the calculated value as described above. Alternatively, an image corrected based on the calculated value is projected by the liquid crystal projector.

FIG. 7 is a schematic diagram showing the configuration of a conventional convergence deviation correction value calculation device used when performing an adjusting operation for correcting convergence deviation of a liquid crystal projector. Signal generator 2 for generating test pattern signals
Are connected to the liquid crystal projector 1 via the composite synchronizing signal line L ₁ and the composite video signal line L ₂ . The liquid crystal projector 1 is adapted to project an image on the screen 3. There are provided video cameras 4a, 4b, 4c ... 4n for individually shooting images projected on the screen 3 at different positions on the screen 3. 4n, so that the signals photoelectrically converted by the video cameras 4a, 4b, 4c ... 4n are stored in the image storage means 5a, 5b, 5c ... 5n provided corresponding to the respective video cameras 4a, 4b, 4c ... 4n. I have to. The video data read from the image storage means 5a, 5b, 5c ... 5n is input to the deviation correction data creating means 6 which calculates the correction value of the convergence deviation.

Next, the operation of this convergence deviation correction value calculation device will be described. When synchronizing the signal of the test pattern with the external signal, the synchronizing signal is received from the liquid crystal projector 1 and the signal of the test pattern is synchronized based on the synchronizing signal. Then, the liquid crystal projector 1 projects an image on the screen 3, and the image is recorded by the video camera 4
Take pictures with a, 4b, 4c ... 4n. The photographed video data is stored in the image storage means 5a, 5b, 5c ... 5n and is digitized once. Then, based on this video data, the deviation correction data creating means 6 calculates the convergence deviation correction value.
By using the deviation correction value calculated in this way, the burden on the adjustment operator is reduced. In addition, it is possible to automate the adjustment of convergence deviation on the production line.

[0005]

However, since the video signal of the test pattern, which is the reference for calculating the convergence deviation, is not such a fine signal that can drive one dot of the liquid crystal panel of the liquid crystal projector, As shown in FIG. 8, even if a video signal of a test pattern that can drive only one dot is created by the phase shift between the horizontal drive signal, the vertical drive signal and the sampling clock, two dots are driven together and the image is projected. To be done. Therefore, the accuracy of the data that corrects the convergence error decreases,
There is a problem that the convergence deviation cannot be adjusted accurately. The present invention has been made in view of the above problems, and an object of the present invention is to provide a convergence deviation correction value calculation device capable of accurately adjusting the convergence deviation of a liquid crystal.

[0006]

A convergence deviation correction value calculating device according to the present invention uses a test pattern for confirming a deviation of convergence in a liquid crystal projector that projects an image in accordance with light transmitted through a liquid crystal panel. The signal from the signal generator, the convergence deviation correction value calculating device for calculating the convergence deviation correction value based on the image projected by the liquid crystal projector, the signal generator, A clock is provided in synchronism with a horizontal drive signal and a vertical drive signal that determine a drive start dot position of the liquid crystal panel, and a clock having the same number of clocks as the number of dots of one horizontal line of the liquid crystal panel is given within the period of the horizontal drive signal. And generates a clock related to the clock given by the LCD projector. A test signal read from the liquid crystal projector in synchronization with a clock generated from the liquid crystal projector or a clock generated by the sync signal generator, and a read test. It is characterized in that it is configured to generate an image for one dot of a liquid crystal panel by an image signal of pattern data.

[0007]

The liquid crystal projector gives a clock to the signal generator which is synchronized with the horizontal drive signal and the vertical drive signal and has the same number of clocks as the number of dots of one horizontal line of the liquid crystal panel within the period of the horizontal drive signal. The sync signal generator in the signal generator generates a clock related to the clock given from the liquid crystal projector. Test pattern data is read from the storage unit in synchronization with a clock given from the liquid crystal projector or a clock generated by a synchronizing signal generator. As a result, the read video signal of the test pattern data has a size capable of driving only one dot of the liquid crystal panel and is obtained corresponding to the dot of the liquid crystal panel. Therefore,
An image signal obtained by reading out the test pattern data does not cause an image to be displayed on two dots of the liquid crystal panel at the same time, so that a convergence deviation due to the image signal of the test pattern given to the liquid crystal projector does not occur.

[0008]

The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. 1 and 2 are block diagrams showing the configuration of a convergence deviation correction value calculation device according to the present invention. The liquid crystal projector 1 includes a timing generator 7 and liquid crystal panels 8R, 8G, 8B corresponding to the three primary colors R, G, B. The light projection side 1a of the liquid crystal projector 1 is directed to the screen 3 side, and an image is projected on the screen 3 by the liquid crystal projector 1. The image projected on the screen 3 is a plurality of video cameras 4a, 4b, 4c.
… By 4n, it is possible to shoot different positions on the screen 3 separately. The video data photoelectrically converted and output by the video cameras 4a, 4b, 4c ... 4n are image storage means 5a, 5b, 5c.
... stored separately in 5n. The video data stored in the image storage means 5a, 5b, 5c ... 5n is input to the shift correction data creating means 6. The liquid crystal projector 1 includes a composite sync signal line L ₁ , a composite video signal line L ₂ , a horizontal drive signal line L ₃ , a vertical drive signal line L ₄ , and a sampling clock line L.
₅ , R (red) color signal line L ₆ , G (green) color signal line L ₇
And B (blue) color signal lines L ₈ are connected to the test pattern signal generator 2.

The test pattern signal generator 2 includes a synchronizing signal generator 9, a PLL circuit 10, selector circuits 11a, 11b and 11c, an address counter 12, ROMs 13a, 13b and 13c, D / A (digital / digital).
(Analog) converters 14a, 14b, 14c and an RGB encoder 15 are provided. The composite sync signal output from the sync signal generator 9 is given to the timing generator 7 and the RGB encoder 15 in the liquid crystal projector 1 via the composite sync signal line L ₁ . The horizontal drive signal and the vertical drive signal output from the synchronizing signal generator 9 are applied to one input terminal of the selector circuits 11a and 11b, and a sampling clock having a clock frequency of FHz is applied to the PLL circuit 10. The sampling clock output from the PLL circuit 10 is the selector circuit 11
It is given to one input terminal of c. The subcarrier signal output from the synchronization signal generator 9 is an RGB signal via the subcarrier signal line L _9.
It is given to the encoder 15. Selector circuits 11a and 11b
A horizontal drive signal and a vertical drive signal are applied to the other input terminal from the timing generator 7 in the liquid crystal projector 1 via the horizontal drive signal line L ₃ and the vertical drive signal line L ₄ . To the other input terminal of the selector circuit 11c, for example, a clock frequency 8F output by the timing generator 7 is output.
A sampling clock obtained by converting the Hz sampling clock into a clock frequency FHz of the sampling clock output from the synchronization signal generator 9 is provided by a frequency conversion circuit (not shown) provided in the middle of the sampling clock line L ₅ . The signals selected by the selector circuits 11a, 11b, 11c are given to the address counter 12.

The signals selected by the selector circuit 11c are the address counter 12, the ROMs 13a, 13b, 13c and the D / A converter.
It is given to each clock pin of 14a, 14b, 14c. The address output from the address counter 12 is given to the ROMs 13a, 13b, 13c storing the test pattern data for each color of R, G, B via the 8-bit bus, and the ROMs 13a, 13b, 13
The test pattern data stored in c is given to the D / A converters 14a, 14b, 14c via an 8-bit bus. D / A
The R, G, B color signals output from the converters 14a, 14b, 14c are given to the RGB encoder 15. Also RGB encoder
The R, G, B color signals supplied to 15 are supplied to the liquid crystal panels 8R, 8G, 8B of the liquid crystal projector 1 via the R, G, B color signal lines L ₆ , L ₇ , L ₈ . The composite video signal output from the RGB encoder 15 is given to the liquid crystal projector 1 via the composite video signal line L ₂ .

Next, the operation of the convergence deviation correction value calculating device configured as described above will be described. First, the sync signal generator 9 generates a composite sync signal, a horizontal drive signal, and a vertical drive signal. The PLL circuit 10 creates a sampling clock based on the horizontal drive signal generated by the synchronization signal generator 9. The selector circuit 11a, 11b, 11c is one of the horizontal drive signal, the vertical drive signal and the sampling clock generated by the synchronization signal generator 9 and the horizontal drive signal, the vertical drive signal and the sampling clock supplied from the liquid crystal projector 1. Select. Then, the address counter 12 generates an address based on the selected signal, reads the test pattern data from the ROMs 13a, 13b, 13c in synchronization with the sampling clock, and generates a digitized video signal. This video signal is obtained for each color of R, G, B, and the D / A converters 14a, 14b, 14c convert this to an analog video signal at the timing of the sampling clock. The R, G, B analog-converted video signals converted by the D / A converters 14a, 14b, 14c are input to the liquid crystal panels 8R, 8G, 8B and the RGB encoder 15 in the liquid crystal projector 1. The composite sync signal and the subcarrier generated by the sync signal generator 9 are input to the RGB encoder 15, and when the analog video signal described above is input, the composite video signal is generated and given to the liquid crystal projector 1.

Next, the horizontal synchronizing signal, the vertical synchronizing signal, and the ROM
The relationship with the digital video signal read from will be described.
FIG. 3 is a schematic diagram of the liquid crystal panel in the state where the test pattern is displayed, and FIG. 4 is a waveform diagram showing the data of the ROM for displaying the test pattern. The liquid crystal panel shown in FIG. 3 normally has 470 dots in the vertical direction and 235 dots in the horizontal direction, but here, for convenience, it has 16 dots in the vertical direction and 12 dots in the horizontal direction.

FIG. 5 shows the addresses of the ROM 13a (13b, 13c).
It is a conceptual diagram of ROM. Addresses increase from left to right and from top to bottom. Further, the address changes significantly in units of one horizontal scanning line. Then, 8-bit data is stored for each address. The address counter 12 counts up each time a sampling clock is input, moves to another address each time a horizontal drive signal is input, and is reset by a vertical drive signal. The sampling clock has the same number of clocks as one horizontal line of the liquid crystal panel, that is, the number of dots arranged in one horizontal row, and the sampling clock is the drive start dot of the liquid crystal panel as shown in FIG. It is synchronized with the falling and rising timings of the horizontal driving signal and the vertical driving signal for determining. The video signal of the test pattern data read from the ROM 13a is also synchronized with the sampling clock. The video signals of the read test pattern data are similarly obtained for the ROMs 13b and 13c in synchronization with the sampling clock.

FIG. 6 is a timing chart of the video signal of the video shown in FIG. 3 and other drive signals. The image data of the test pattern is an 8-bit signal, but here, only "00" or "FF" is used. The test pattern data is stored in the ROM address shown in FIG. Therefore, when the horizontal drive signal and the vertical drive signal are first input to the address counter 12, the ROM 13a, 13b, 13
Address "00" is specified as the address of c, and test pattern data from addresses "00" to "10" is read from ROM 13a, 13b, 13c in synchronization with the sampling clock shown in Fig. 6 and D / A converted. Input to the devices 14a, 14b, 14c. When the next horizontal drive signal is input to the address counter 12, it moves to the address "00 + 20 × N" (where N is incremented each time the horizontal drive signal is input).

Until the next horizontal drive signal is input, the liquid crystal 1-line data is read from the address "00 + 20.times.N" and input to the D / A converters 14a, 14b and 14c in the same manner as described above. Whenever the horizontal drive signal is input in this way and the address changes to the address "170" by repeating the above operation, it means that the test pattern data for one screen has been read, and the next vertical drive signal is read. When is input, it moves to the address "00" and reads the test pattern data from the ROMs 13a, 13b, 13c as described above. As described above, the test pattern is synchronized with the horizontal drive signal and the vertical drive signal, and the test pattern is read from the ROM in synchronization with the clock having the same number of clocks as the number of dots of one horizontal line in the liquid crystal panel within the period of the horizontal drive signal. When the data is read, the read video signal of the test pattern data is obtained in a size capable of driving only the dots of the liquid crystal panel, and is obtained corresponding to the dots.

Thus, it is possible to eliminate the convergence deviation which may occur due to the video signal of the test pattern without displaying the video simultaneously on the two dots of the liquid crystal panel. Therefore, it is possible to display the test pattern on the liquid crystal panel and accurately calculate the convergence deviation correction value.

[0017]

As described in detail above, the present invention is synchronized with the horizontal drive signal and the vertical drive signal that determine the drive start dot of the liquid crystal panel, and one horizontal line of the liquid crystal panel is within the period of the horizontal drive signal. Data of the test pattern data read from the storage unit in synchronization with the clock provided from the liquid crystal projector having the same number of clocks as the number of dots or the clock related to the clock provided from the liquid crystal projector generated by the signal generator. Since the image is displayed on the liquid crystal panel by the image signal of, the image can be surely displayed on only one dot of the liquid crystal panel, and a fine test pattern can be generated. Convergence deviation that may occur can be eliminated. As a result, there is an excellent effect that the value for which the convergence should be corrected can be accurately calculated by the generated test pattern.

[Brief description of drawings]

FIG. 1 is a half of a block diagram showing a configuration of a convergence deviation correction value calculation device according to the present invention.

FIG. 2 is a half part of a block diagram showing a configuration of a convergence deviation correction value calculation device according to the present invention.

FIG. 3 is a schematic view of a liquid crystal panel displaying a test pattern.

FIG. 4 is a view for displaying the test pattern shown in FIG.
It is a waveform chart of the data of ROM.

FIG. 5 is a conceptual diagram of a ROM showing addresses of the ROM.

FIG. 6 is a timing chart of the video signal and horizontal and vertical drive signals of the test pattern shown in FIG.

FIG. 7 is a block diagram showing a configuration of a conventional convergence deviation correction value calculation device.

FIG. 8 is a timing chart of signals of respective parts in one line of the liquid crystal of the conventional convergence deviation correction value calculation device.

[Explanation of symbols]

1 LCD projector 2 Test pattern signal generator 3 Screen 6 Deviation correction data creating means 7 Timing generator 8R, 8G, 8B LCD panel 9 Sync signal generator 10 PLL circuit 11a, 11b, 11c Selector circuit 12 Address counter 13a, 13b, 13c ROM 14a, 14b, 14c Digital / analog converter 15 RGB encoder L ₁ Composite sync signal line L ₂ Composite video signal line L ₃ Horizontal drive signal line L ₄ Vertical drive signal line L ₅ Sampling clock line L ₆ , L ₇ , L _8- color signal line L ₉ subcarrier signal line

Claims (2)

[Claims] 1. A liquid crystal projector, which projects an image in accordance with light transmitted through a liquid crystal panel, supplies a signal of a test pattern used for confirming the deviation of convergence from a signal generator to the image projected by the liquid crystal projector. In the convergence deviation correction value calculation device that is configured to calculate the convergence deviation correction value based on the above, the signal generator outputs a horizontal drive signal and a vertical drive signal from the liquid crystal projector that determine the drive start dot position of the liquid crystal panel. The clocks are synchronized and have the same number of clocks as the number of dots of one horizontal line of the liquid crystal panel within the horizontal drive signal period, and generate a clock related to the clock given from the liquid crystal projector. Equipped with a synchronization signal generator and a storage unit that stores test pattern data The test pattern data in the storage unit is read in synchronization with the clock from the liquid crystal projector or the clock generated by the sync signal generator, and the image signal of the read test pattern data is used to form an image of one dot on the liquid crystal panel. A convergence deviation correction value calculation device, which is configured to generate. 2. The convergence deviation correction value calculation according to claim 1, wherein the signal generator can calculate the convergence deviation of the liquid crystal projector up to a unit of one dot or less of the liquid crystal panel. apparatus.