JPH06216393A - Semiconductor nonvolatile memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor nonvolatile memory having smaller size and better characteristics than those of prior art. CONSTITUTION:A plurality of active regions 63 for sequentially forming a plurality of memory cells in a y direction as active regions 63 long in the y direction are aligned to be formed in an x direction on a silicon substrate 61. As a memory cell 65, a memory cell 65 having a floating gate 69, a control gate 71, a source region and a drain region and using the region 63 as an active layer is provided. A control gate 71 of each cell 65 is covered with an upper insulating film, and sidewalls of the gates 69 and 71 are covered with a sidewall insulating film 81b. Source wirings 93 for connecting the source regions of the cells 65 aligned in the x direction are aligned in the y direction and provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory and its manufacturing method.

[0002]

2. Description of the Related Art EEPROM (Electrically Erasable)
A semiconductor non-volatile memory represented by a programmable ROM) or a flash memory has a large number of memory cells arranged on a semiconductor substrate. As an example of a general structure of each memory cell in such a memory, there is a structure shown in a sectional view in FIG. That is, a floating gate 13 and a control gate 15 which are sequentially provided from the substrate side on a Si single crystal substrate 11 as a semiconductor substrate, and a source region 17 and a drain formed in the semiconductor substrate portion on the side of these gates 13 and 15. A memory cell 21 having a structure including a region 19. In FIG. 11, 23 is an insulating film, 25 is a contact hole, and 27 is a contact hole.
Is a wiring (a bit line in this case). The arrangement of the memory cell 21 on the semiconductor substrate 11 as described above has conventionally been performed as follows. FIG. 12 (A)
FIG. 3 is a plan view used for the description, and is a plan view schematically showing a region including a plurality of memory cells. In addition, FIG.
12B is a plan view showing a state in which the wiring 27, the control gate 15, the floating gate 13 and the like are removed from the structure of FIG. 12A in order to clarify the structure of the active region in the portion of FIG. 12A. It is a figure. Figure 11
The portion indicated by is exactly the cross section taken along the line I-I in FIG.

In this conventional semiconductor non-volatile memory, as shown in FIG. 12 (B), the active region 31 for forming a memory cell is arranged on the semiconductor substrate 11 exactly on the cross-cut line portion. Has been formed. In addition,
In FIG. 12B, 33 is a field area. Then, as shown in FIG. 12A, the floating gate 13 (hatched portion) is provided on each memory cell formation region including the active region. In addition, the control gates 15 of the memory cells connected in the x direction in FIG. 12A are connected to each other, and the word line 15 is formed by this. Furthermore, FIG. 12 (A)
In a plurality of memory cells arranged in the y direction, the source region 17 or the drain region 19 is shared by adjacent memory cells. Further, the source region (impurity diffusion layer) 17 is formed so as to extend between the memory cells continuous in the x direction. To fix the potential of the source region 17, an aluminum wiring 35 (see FIG. 12A) provided separately from the bit lines, for example, for every 16 bit lines 27 (refer to FIG. 12A) is hereinafter referred to as "source aluminum wiring 35". )
Is connected to the source region 17 via a contact hole 37.

In this conventional semiconductor non-volatile memory, the maximum source resistance when the source aluminum wiring 35 is provided for every 16 bit lines is the memory cell located at the eighth position in the x direction when viewed from the source aluminum wiring 35. appear. The source resistance at this time is, for example, 2.0 μm for the X pitch (see FIG. 12A) of the memory cell and 0. 0 for the width of the source region (impurity diffusion layer) 17 (dimension in the y direction in FIG. 12A). 5
μm, and assuming that the sheet resistance of the source region 17 is 50Ω, it is 50 × 2.0 × 8 ÷ 0.5 ÷ 2
= 800Ω. Here, the divisor 2 in the equation is that the source aluminum wiring 35 is provided for every 16 bit lines,
This is because it is considered that the route (parallel route) from the two source aluminum wirings 35 extends to the memory cell on the eighth surface in the x direction when viewed from the source aluminum wiring 35.

Further, in this conventional semiconductor nonvolatile memory, the Y pitch of one memory cell is, as shown in FIG. 12A, (half the value y ₁ of the y dimension of the source region 17) + (gate Interval y ₂ between the active regions 31 and 13, 15 + (Gate length y ₃ ) + (Interval y ₄ between the gates 13 and 15 and the contact hole 25) + (Half value y _{5 of the} contact hole 25) ). When this Y pitch is estimated on a rule basis of 0.6 μm, for example, y ₁ = 0.25 μm, y ₂ = 0.25 μm,
y ₃ = 0.7 μm, y ₄ = 0.3 μm and y ₅ = 0.3
Since it is μm, Y = 1.8 μm. Similarly, in the 0.6 μm rule, the X pitch is 2 μm, although details are omitted.

[0006]

However, as shown in FIG.
In the conventional semiconductor nonvolatile memory described with reference to
Since the source regions of the memory cells continuous in the direction are connected by the impurity diffusion layer, the source aluminum wiring 35
For example, even if every 16 bit lines are provided, the memory cell connected in the x direction has a source resistance of 800Ω, and the source resistance of each memory cell in the memory cell connected in the x direction is increased. Has a problem that it changes depending on the distance from the source aluminum wiring 35. Therefore, when writing / erasing data, characteristic deterioration or characteristic variation due to the voltage drop due to the difference in the source resistance occurs. Further, since the source aluminum wiring 35 is provided for every m bit lines (m = 16 in the above example),
The effective X pitch of the memory cell is increased by (m + 1) / m times, which is disadvantageous in reducing the size of the semiconductor nonvolatile memory. Further, regarding the Y pitch of the memory cell, if the mask alignment accuracy at the time of manufacturing the memory is taken into consideration, the gate 1
The distance y ₂ between the active regions 31 and 3 and 15 and the gate 1
The distance y ₄ between the contact holes 3 and 15 and the contact hole 25 (see FIG. 12).
However, it is difficult for the conventional structure to further shorten the length.

Further, due to the mask misalignment at the time of manufacturing the memory, the field area 3 of the floating gate 13 is formed.
3 (see FIG. 12B), the floating gate may be located on the edge portion (on the thin film portion) of the field oxide film or on the portion slightly away from the edge ( There is a problem in that the potential of the floating gate fluctuates because it is located on a portion where the film thickness is relatively thick). This causes variation in the data writing / erasing characteristics of the memory cell, and therefore improvement is desired.

This application has been made in view of the above point, and an object of the first invention of this application is to provide a structure of a semiconductor nonvolatile memory which can solve the above-mentioned problems. The purpose of the second invention of this application is
It is an object of the present invention to provide a method of manufacturing a semiconductor non-volatile memory according to the first aspect of the present invention, which can be manufactured on a fine scale below the resolution limit of current photolithography. Further, the third and fourth inventions of this application are to provide a method useful not only for the semiconductor non-volatile memory of the first invention but also for general semiconductor non-volatile memory, particularly for forming a wiring structure.

[0009]

In order to achieve this object, according to the semiconductor non-volatile memory of the first invention of this application, a plurality of active regions which are elongated in the first direction are formed on a semiconductor substrate. A plurality of active regions for sequentially forming the memory cells in the first direction are arranged side by side in the second direction, and the memory cells include a floating gate, a control gate, a source region and a drain region. A memory cell using the active region as an active layer, the floating gate and the control gate of each memory cell are covered with an insulating film on the upper surface and side walls thereof, and the source of each memory cell is arranged in the second direction. A source wiring for connecting the regions to each other is arranged in the first direction described above.

In the first aspect of the present invention, the active region elongated in the first direction is, of course, a linearly elongated one in the first direction, for example, a rectangular one, which is of course slightly meandering. It may also include one that is elongated in the first direction. Further, the first direction and the second direction mean directions intersecting with each other, and preferably two directions orthogonal to each other.

In the semiconductor non-volatile memory according to the first aspect of the present invention, when the drain pad portion is provided in the drain region of each memory cell, the source wiring and the drain pad portion are close to each other (for example, The source wiring 83 and the drain pad portion 8 in FIG.
See the relationship with 5.). Since each memory cell is miniaturized in order to obtain a highly integrated semiconductor nonvolatile memory, the distance between the source wiring and the drain pad naturally exceeds the resolution limit of the current photolithography technology. Is coming. However, by simply using the current photolithography technique, the source wiring and the drain pad portion cannot be patterned by one photolithography technique and etching technique because of the above-mentioned resolution limit. In order to avoid this, a structure in which the source wiring and the drain pad portion can be formed in separate steps, for example, as shown in FIG.
The structure shown in the sectional view of one memory cell in 3 is considered as an example of the structural example of the first invention. That is, the sidewalls of the floating gate 42 and the control gate 43 of each memory cell 41 are covered with the insulating film 44, the source wiring 46 in the first invention is provided on the source region 45, and the drain region 47 is provided on the drain region 47. The pad portion 48 according to the first aspect of the invention is provided, and the source wiring 46 and the pad portion 48 are insulated by an insulating film 49 like an intermediate insulating film. However, in the example shown in FIG. 13, the drain pad portion 48 and the source wiring 46 are laminated in the upper layer relation, but a structure in which these are reversed may be used. In FIG. 13, 50 is a semiconductor substrate (for example, a silicon substrate), 51 is an interlayer insulating film, 52 is a contact hole provided in the interlayer insulating film 51, and 53 is a wiring (bit line). In the structure shown in FIG. 13, one of the source wiring 46 and the pad portion 48 is patterned and then the insulating film 49 is formed, and then the other of the source wiring 46 and the pad portion 48 can be patterned. The pad portion 48 and the pad portion 48 can be arranged in a plane at a short distance exceeding the resolution limit of the current optical lithography technology. However, when such a manufacturing method is adopted, the conductive thin film for the source wiring, the intermediate insulating film-like insulating film, the conductive thin film for the drain pad, and the insulating film for the interlayer insulating film are formed four times. Since a thin film forming step is required, and a photolithography step and an etching step are required four times each, there is a problem in throughput.

Therefore, in the manufacturing method of the second invention of this application, the semiconductor non-volatile memory of the first invention, which is a semiconductor non-volatile memory having a pad portion in each drain region of each memory cell, is used in the current photolithography. In the case of a finer scale than the resolution limit of the technology, the formation of the pad portion and the source wiring described above, a step of forming a conductive thin film on the entire area including the pad portion and the source wiring formation planned region, One of the above-described pad portion forming mask and the above-mentioned source wiring forming mask is formed on the thin film by the first photolithography step, and one of the above-mentioned masks is formed by the second photolithography step. It is characterized in that it is performed by a step including a step of forming the other.

Further, the third and fourth inventions of this application respectively include various semiconductor nonvolatile memories having island-shaped pad portions and further line-shaped wiring (for example, a drain pad and a source which are examples of the first invention). The present invention relates to a method suitable for use in manufacturing a device having wiring (for example, see the third invention section and the fourth invention section in the examples described later for details).

Therefore, according to the third aspect of the invention, a large number of memory cells having a floating gate, a control gate, a source region and a drain region are provided in a matrix, and the control gates of the memory cells arranged in one direction in the matrix. In manufacturing a semiconductor non-volatile memory including a plurality of word lines configured by connecting a plurality of word lines, after the formation of the word lines, at least a part of each word line that is in contact with the source region and a part that is in contact with the drain region. Forming a side wall film made of an insulating film on each side wall, and at least a space on the field region between the drain regions among the spaces sandwiched by the adjacent word lines except the space corresponding to the drain region. With an insulating film, forming the side wall film and the insulating film Characterized in that it comprises a step of forming a conductive thin film on the buried the sample over the entire surface having undergone by, and the step of patterning the conductive film into a predetermined shape.

According to the fourth invention, a large number of memory cells having a floating gate, a control gate, a source region and a drain region are provided in a matrix form, and the control gates of the memory cells arranged in one direction in the matrix are connected. In manufacturing a semiconductor non-volatile memory having a plurality of configured word lines,
After the formation of the word lines, a sidewall film made of an insulating film is formed on all the sidewalls of the source region side and on the sidewalls of at least the drain region contacting the drain region of each word line. The step of forming and the step of filling only the space on the field region between the drain regions among the spaces sandwiched by the adjacent word lines with the insulating film, the formation of the sidewall film and the filling with the insulating film are completed. A step of forming a conductive thin film on the entire surface of the sample so that the film thickness of the part formed in the space between the word lines of the conductive thin film is thicker than the other part, and a step of forming the conductive thin film. A step of forming a mask on the conductive thin film covering each portion corresponding to the drain region, and after the formation of the mask, the conductive thin film is thicker than the thickness of the portion on the word line, One, characterized in that it comprises a step of removing only the film thickness thinner than the thickness of the portion formed between the word lines.

In implementing the third and fourth inventions, the step of forming a side wall film on the side wall of the word line and the step of filling a predetermined portion of the space between the word lines with an insulating film are performed by different steps. Of course, it can be performed, but it is preferable to form the sidewall film and the insulating film at the same time in order to reduce the number of steps. As a method, for example,
It is preferable to use a method including the following steps (a) to (c).

(A) Each word line is arranged such that the word line interval in a portion to be filled with the insulating film in the space sandwiched by adjacent word lines becomes narrow enough to fill the insulating film in the portion. Pre-forming process.

(B) A step of forming an insulating film on the entire surface of the sample on which the word line is formed.

(C) A step of selectively removing the insulating film by anisotropic etching.

Here, the word line spacing to be filled with the insulating film in the step (a) is, for example,
It depends on the design because it depends on the height of the word line, the accuracy when patterning the word line, the type of the insulating film used, and the method of forming this insulating film.

[0021]

According to the structure of the first invention, each active region has a long shape in the first direction and is divided by the field oxide film in the second direction (FIG. 1 (B)). reference.). For this reason, as shown in FIG.
The active region 63 is opposed only at a portion intersecting with (the portion indicated by P in FIG. 1B). This corresponds to the active area 31 described with reference to FIG.
Since it means that it is not necessary to consider the distance y ₂ between the gate and the gates 13 and 15, the pitch of the memory cells in the Y direction can be shortened. Further, since the floating gate exists on the portion where the film thickness of the field oxide film is substantially thick except for the portion P of FIG. 1B, the floating gate is located at the edge of the field oxide film. It is possible to prevent the problem of the potential variation of the floating gate depending on whether or not this occurs.

The source regions of the memory cells connected in the second direction are connected to each other by the source wiring. That is, the source regions of the memory cells connected in the second direction are connected not by the impurity diffusion layer but by the source wiring. Therefore, the source resistance of each memory cell is reduced by the use of the wiring, and the variation in source resistance due to the difference in the position of the memory cell is also reduced. In addition, the insulation between the source wiring and the control gate and the floating gate is performed by the insulating film covering the upper surface and the side wall of these gates. Such an insulating film that covers the upper surface and side walls of the control gate and the floating gate is formed by, for example, oxidizing the surface of these gates if they are polysilicon, or forming an insulating film separately on the surface of these gates. It can be formed in a self-aligning manner with high precision by a method of forming a sidewall on the gate by processing with an anisotropic etching technique. Therefore, the distance y ₄ between the gates 13 and 15 and the contact hole shown in FIG. 12 can be substantially eliminated, and the Y-direction pitch of the memory cells can be shortened.

According to the structure of the second invention of this application, for example, each source wiring is exposed by the current photolithography technique in the first exposure step, and each drain pad is currently exposed in the second exposure step. When exposed by the photolithography technology, the pitch between the source wiring and the pad portion for the drain can be made equal to or smaller than the resolution limit of the current photolithography technology. Moreover, since the conductive thin film formed in the same step can be used, the number of times of film formation and the number of lithography steps can be reduced as compared with the conventional case.

Further, according to the structure of the third invention of this application, since the predetermined portion between the word lines is filled with the insulating film, the buried insulating film surface and the word line surfaces on both sides thereof form a continuous flat surface. Constitute. Then, a conductive thin film is formed on the sample including such a flat surface. Considering the case where the conductive thin film thus formed is processed to form, for example, a drain pad and a source wiring, in that case, the conductive thin film formed above corresponds to the drain region of this film. A mask is formed to cover the portion and the portion to be the source wiring. Then, after that, a portion of the conductive thin film which is not covered with the mask, that is, a portion of the conductive thin film on the word line and a conductive thin film portion on the insulating film filling the space between the word lines are etched. Since the conductive thin film portion to be etched is a portion formed on the flat surface as described above, the film thickness distribution thereof is sufficiently more uniform than that formed on the uneven portion. It also becomes easier to control. Therefore, it is possible to reduce the risk of damaging the base (for example, the word line) of the conductive thin film. Further, the sidewall film made of an insulating film formed in a predetermined portion electrically insulates the word line from the drain pad and the source wiring. However, in this case, it is necessary to provide a sidewall film made of an insulating film over the entire sidewall of the word line on the source region side.

Further, according to the constitution of the fourth invention of this application, the same action as in the case of the third invention is obtained, and further the following action is obtained. In the fourth invention, the conductive thin film is formed so as to satisfy a predetermined film thickness. Then, after forming a mask for covering the drain region of the conductive thin film, the conductive thin film portion not covered with the mask is removed by a predetermined thickness. After the removal of the predetermined thickness, only the conductive thin film portion under the mask and the conductive thin film portion between the word lines remain in a self-aligned manner.
The former of these remaining conductive thin film portions becomes the drain pad, and the latter becomes the source wiring.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the semiconductor non-volatile memory of the first invention and embodiments of the respective inventions of the second to fourth semiconductor non-volatile memory manufacturing methods will be described below with reference to the drawings. It should be noted that the drawings used for the description only schematically show the dimensions, shapes, and arrangement relationships of the respective constituent components to the extent that these inventions can be understood. Further, in each drawing used for the description, the same components are denoted by the same reference numerals, and duplicate description thereof may be omitted.

1. Description of Structure (First Invention) of Semiconductor Nonvolatile Memory FIG. 1A is a plan view showing a part (a region portion including several memory cells) of the semiconductor nonvolatile memory of the embodiment. In addition, FIG. 1B is provided in order to clarify the structure of the active region in the portion of FIG. 1A and the positional relationship of the floating gate with respect to the active region.
FIG. 7 is a plan view showing a state in which wirings, control gates, and the like are removed from the structure of (A). Further, FIG. 2 is a sectional view of this semiconductor nonvolatile memory, taken exactly along the line II of FIG. 1 (A). In this embodiment, the first direction will be described as the y direction and the second direction will be described as the x direction orthogonal to the y direction.

In the semiconductor non-volatile memory of this embodiment, a silicon substrate 61 as a semiconductor substrate is provided with a plurality of memory cells which are long active regions 63 in the y direction (portions shaded in FIG. 1B). A plurality of active regions 63 for sequentially forming 65 in the y direction are arranged side by side in the x direction. In FIG. 1B, 67 is a field insulating film.

Further, in this semiconductor nonvolatile memory, the floating gate 6 is used as the memory cell 65 described above.
9, a memory cell 65 having a control gate 71, a source region 73 and a drain region 75 (source and drain regions are shown in FIG. 2) and using the above-mentioned active region 63 as an active layer. The control gates 71 of the memory cells 65 connected in the x direction are connected to each other to form a word line. Further, as shown in FIG. 2, a gate insulating film 77 is provided between the semiconductor substrate 61 and the floating gate 69, and the floating gate 69 and the control gate 7 are provided.
An insulating film 79 is provided between the first and second electrodes.

Further, in this semiconductor nonvolatile memory,
The insulating film 81 (see FIG. 2) is formed on the upper surface and sidewalls of the floating gate 69 and the control gate 71 of each memory cell 65.
Reference). In the case of this embodiment, the upper surface of the control gate 71 and the side walls of the floating gate 69 and the control gate 71 are covered with different insulating films for manufacturing reasons. Hereinafter, for convenience of description, the former is referred to as an upper surface insulating film 81a (not shown in FIG. 1A), and the latter is a sidewall insulating film 81b.
Called.

Further, in this semiconductor nonvolatile memory,
Source wirings 83 for connecting the source regions 73 of the memory cells 65 arranged in the x direction are arranged side by side in the y direction, and a pad portion 85 is provided on each drain region 75 of each memory cell 65. . A bit line 87 is connected to the pad 85. In addition, in FIG.
89 is an interlayer insulating film (not shown in FIG. 1), and 91 is a contact hole provided in the interlayer insulating film 89 for connecting the bit line 87 to the pad 85.

Here, the source wiring 83 is made of a refractory material such as tungsten, silicide, or the like. The drain pad portion 85 is preferably made of the same material as the source wiring 83. This is because the source wiring 83 and the drain pad 85 can be easily formed by using the conductive films formed in the same step, which will be described later in the section of the embodiment of the manufacturing method of the second invention.

In the conventional semiconductor nonvolatile memory, the source regions 73 of memory cells connected in the x direction are connected to each other by extending the active region also in the x direction and forming an impurity diffusion layer in this active region portion. (See FIG. 12A). On the other hand, in the semiconductor nonvolatile memory of the present invention, the source wiring 83 is separately provided without extending the active region in the x direction, and the source wirings 83 connect the source regions 73 of the memory cells continuous in the x direction. Therefore, the source resistance of each memory cell can be reduced as compared with the conventional one, and the source resistance variation due to the difference in the position of the memory cell in the memory can also be reduced. In fact, when the source wiring 83 is formed of a tungsten thin film having a film thickness of 100 nm and a width (dimension in the y direction) of 0.5 μm, and the resistivity of tungsten is 1 × 10 5.
If the X pitch of first memory cell is ^-5 Omega · cm was assumed 2 [mu] m, the source resistance value per bit (1 × 10
⁻⁵ / 100 × 10 ⁻⁶ ) × (2 / (0.5 × 2) = 1Ω. Therefore, for example, the memory cell is 1000 in the x direction.
The source resistance in the memory cell at the center of this column is 500Ω even if they are connected in series. In the prior art, the usefulness of the present invention can be understood by comparing with the fact that even if the source / aluminum wiring is provided for every 16 bit lines, the source resistance in the central memory cell is as high as 800Ω. Further, since the source / aluminum wiring which has been conventionally provided for every m bit lines is not required in the present invention, the effective X pitch of the memory cell can be shortened accordingly.

Further, in the semiconductor nonvolatile memory of the present invention, the source wiring 83 and the pad portion 85 are insulated from the floating gate 69 and the control gate 71 by the upper surface insulating film 81a and the side wall insulating film 81b, which is conventionally required. The distance y ₄ between the gates 13 and 15 and the contact hole 25, which is indicated by y ₄ in FIG. 12A, can be substantially zero. Further, since the floating gate 69 because no extended in an active region in the x-direction there is no fear of contact with Akuteibu region shifted in the y-direction, shown in was conventionally required FIG 12 (A) with y ₂ The dimensions can be substantially zero. Therefore, the Y pitch of the memory cell can be shortened as compared with the conventional case. Specifically, in the semiconductor nonvolatile memory shown in FIG. 1A, the Y pitch of one memory cell is (value y _{A which} is half the distance between adjacent gates) +
(Overlap dimension y _{B of the} source wiring on the gate)
+ (Spacing y _C between source wiring and drain pad) +
Since it is determined by (alignment allowance dimension y _D between the contact hole and drain pad) + (half value y _E of contact hole width), assuming that the mask misalignment is 0.3 μm or less according to the rule of 0.6 μm. Assuming dimensions y _{E to} y _A , y _E is 0.3 μm, y _D is 0.3 μm from the mask misalignment, and y _C is 0 because both do not short-circuit even if the mask misalignment occurs. .4
The sum of μm, y _B and y _{A, that} is, the half value of the source wiring 83 varies depending on the width of the sidewall insulating film 81 b and the variation in the manufacturing process, but y _B becomes 0.1 μm and y _A becomes 0.4 μm. The pitch is 1.5 μm. The size can be reduced to 0.3 μm compared to the conventional 1.8 μm.

2. Description of Method for Manufacturing Semiconductor Nonvolatile Memory (Second Invention) Next, an embodiment of a method for manufacturing the semiconductor nonvolatile memory of the first invention on a scale below the resolution limit of the current photolithography technology will be described.

2-1. Manufacturing Method of First Embodiment of Second Invention First, a manufacturing method of the first embodiment will be described with reference to FIGS. 1 and 3 to 5. Note that these drawings show the state of the sample in the main steps of the manufacturing process by the cross-sectional view corresponding to FIG. 2 (the same applies to FIGS. 5 to 10 below).

First, a field oxide film, which is an insulating film for element isolation, is formed on the semiconductor substrate 61 by a known method. At this time, as shown in FIG.
A field oxide film 67 is formed so that each active region 63 remains in the y direction in a long manner.

Next, on the semiconductor substrate 61, an insulating film for forming a gate insulating film, a thin film for forming a floating gate, an insulating film for forming an insulating film between floating gates and control gates, and a conductor for forming a control gate. A film and an insulating film for forming an upper surface insulating film are sequentially formed by a suitable method (not shown), and then these thin films are patterned by a known lithography technique and etching technique to form a gate insulating film 77 and a floating gate. 69, floating gate / control gate insulating film 79, control gate 71, and upper surface insulating film 81a. Next, the source region 7 is formed in the semiconductor substrate portion on the side of the gates 69 and 71 by a known method.
3 and the drain region 75 are formed (FIG. 3A).

Next, an insulating film for forming a sidewall insulating film is formed on the entire surface of this sample by a suitable method (not shown), and then this insulating film is selectively removed by anisotropic etching. The sidewall insulating film 8 is formed on each sidewall of the gates 69 and 71.
1b is formed (FIG. 3 (B)). Through the steps so far, the upper surface of the control gate 71 and the gates 69, 7 are formed.
1 and the side wall thereof are covered with the insulating film 81 (see FIG. 3).
(B)).

Next, the source region 73 and the drain region 7
A conductive thin film (for example, a tungsten film) 83x for forming source wiring and drain pads is formed on the entire surface of the sample with the surface of No. 5 being exposed (FIG. 3).
(C)).

Next, one of a source wiring formation mask and a pad portion formation mask is formed on the conductive thin film 83x by the first photolithography process. In this embodiment, first, a resist is patterned as a mask for forming each source wiring to obtain a first resist pattern 93 (FIG. 4A).

Next, in this embodiment, the resist pattern suitable for the type of resist is strengthened or hardened by irradiating the first resist pattern 93 with ultraviolet rays at a high temperature. Hereinafter, this is referred to as a strengthening process.

Next, a new resist is applied over the entire surface of the sample having the strengthened first resist pattern 93a,
This time, a second resist pattern 95 as a mask for forming the drain pad is formed by the second photolithography process (FIG. 4B). The strengthened first resist pattern 93a is not attacked by the second lithography process for forming the second resist pattern.

Next, the conductive thin film 83x is selectively etched by using the second register pattern 95 and the strengthened first register pattern 93a as a mask. Thus, the source wiring 83 and the drain pad 85 can be formed (FIG. 4C).

Next, an interlayer insulating film 89 is formed on the entire surface of this sample by a known method, and a contact hole 91 is further formed therein (FIG. 5A). Next, the bit line 87 is formed by a known method.

According to this method, it is possible to manufacture a semiconductor nonvolatile memory in which the source wiring 83 and the drain pad are close to each other within the resolution limit of the current photolithography technique.

2-2. Manufacturing Method of Second Embodiment of Second Invention In the manufacturing method of the first embodiment described above, the first resist pattern is strengthened to prevent the first resist pattern from being attacked when the second resist pattern is formed. Was. However, for example, the second invention can be implemented by the following method. FIGS. 6A to 6C are process drawings used to explain the main part of the process.

First, the procedure similar to that described with reference to FIGS. 3A to 3C is performed until the formation of the conductive thin film 83x.
Thereafter, as shown in FIG. 6A, a negative resist 97 is applied on the entire surface of this sample. Then, for example, a region of the negative resist corresponding to the source wiring formation region is selectively exposed. This first exposure area is indicated by Q ₁ in FIG.

Next, the region of the negative resist that has undergone the first exposure, this time corresponding to the drain pad forming region, is selectively exposed (FIG. 6B). This second exposure area is indicated by Q ₂ in FIG. 6 (B).

Thereafter, when this resist is developed, a resist pattern 97x having a portion 97a as a mask for forming a source wiring and a portion 97b as a mask for forming a drain pad is obtained. After that, the procedure of the manufacturing method of the first embodiment may be adopted.

The manufacturing method of the second embodiment has an advantage that the strengthening process of the first resist pattern, which is required in the first embodiment, can be omitted.

2-3. Manufacturing method of the third embodiment of the second invention The manufacturing method of the second invention can also be implemented by the following method. 7 to 10 are process diagrams used for the description.

First, the procedure similar to that described with reference to FIGS. 3A to 3C is performed until formation of the conductive thin film 83x (FIGS. 7A and 7B).

Next, in this third embodiment, the conductive thin film 8
A mask forming thin film 99 made of a material different from the resist is formed on the entire surface of 3x. Such a thin film can be, for example, a silicon oxide film or a silicon nitride film. In this example, a silicon oxide film is used.

Next, a resist is applied on the entire surface of the mask forming thin film 99 (not shown), and then the resist is patterned by patterning so that the resist remains on the source wiring formation planned region. (Fig. 8
(A)).

Next, the mask forming thin film 99 is selectively etched using the resist pattern 101 as a mask. As a result, the source wiring formation mask 99x is obtained (FIG. 8B). This etching is performed by an etching method that etches the mask forming thin film 99 but does not substantially etch the conductive thin film 83x. The mask forming thin film 99 is composed of a silicon oxide film,
If the conductive thin film 83x is made of tungsten,
The etching of the silicon oxide film is performed by using, for example, CHF ₃ gas and C
By performing dry etching using a mixed gas with F ₄ gas, the above selective etching is possible.

Next, a resist is applied again on this sample (not shown), and this resist is patterned so that it remains in the drain pad formation planned region. As a result, the pad portion forming mask 103 is obtained (FIG. 9A).

Next, these source wiring forming masks 99 are formed.
x and the pad portion forming mask 103 are used as masks to selectively etch the conductive thin film 83x. Thus, the source wiring 83 and the drain pad portion 85 can be formed respectively.

Thereafter, as in the first embodiment, the interlayer insulating film 8 is formed.
9 and contact holes 91 are formed respectively (see FIG.
(A)) Further, the bit line 87 is formed.

Although the source wiring forming mask 99x is left in the illustrated example, it may be removed before the interlayer insulating film 89 is formed. Further, in the manufacturing method of the third embodiment described above, the source wiring forming mask 99x is formed of a mask forming material (silicon oxide film in this case) other than the resist, and the drain pad portion forming mask is formed of the resist. However, it is of course possible to reverse this. If necessary, for example, a silicon nitride film is laminated on the silicon oxide film 99 of the sample in the state of FIG. 7C, and these thin films are sequentially patterned by two lithography steps and etching steps to form a source wiring. One of the formation mask and the drain pad portion formation mask may be made of a silicon oxide film, and the other may be made of a silicon nitride film.

In the manufacturing method of the third embodiment, a stronger mask can be obtained as compared with the case where the mask is formed only with the resist, so that the patterning accuracy of the source wiring and the pad can be expected to be improved.

3. Description of Third Invention According to the method of the second invention described above, it is possible to manufacture a fine semiconductor non-volatile memory device having a resolution limit of the current optical lithography technique or less while using the current optical lithography technique. It was However, the method of the second invention,
In the step of etching the conductive thin film when forming the drain pad and the source wiring, there is a possibility that the base (specifically, the word line constituent portion) may be damaged when removing an unnecessary portion of the conductive thin film. It became clear by the research of the inventor of this application. The third invention of this application is a suitable method for preventing the damage of the above-mentioned substrate, and the reason why the substrate is damaged will be described below in the order of the embodiment of the third invention for preventing it.

3-1. The reason why the base is damaged: For example, FIG. 3 (A) of the first embodiment of the method of the second invention.
According to the procedure described with reference to FIGS. 4C and 4A and 4B, a control gate, a source region, a drain region, and the like are formed on a semiconductor substrate, and a conductive thin film for forming a drain pad and a source wiring is formed. When a resist pattern for forming and patterning the thin film on the drain pad and the source wiring is formed, the obtained sample has a structure as shown in FIG. Become a body. Then, when the structure is viewed in plan from above, the structure is as shown in FIG.
However, in FIG. 14, word lines W _n-2 , W _n-1 ,
W _n and W _{n + 1} are shown, and the drain region and the source region for each memory cell 65 are shown as D and S, respectively.
As can be understood from FIG. 14, the second resist pattern 95 for forming the drain pad (indicated by high-density diagonal lines in FIG. 14) is used as the conductive thin film 8 on the drain region D.
3x (see FIG. 4B. Illustration is omitted in FIG. 14). Also, the first resist pattern 9 for forming the source wiring is formed.
3a (in FIG. 14, shaded with a coarse density) is a region including the source region S in each space sandwiched by adjacent word lines (W _n-2 and W _{n- in} the example of FIG. 14). The region between ₁ and the region between W _n and W _{n + 1} ) covers the conductive thin film. Then, in order to form the drain pad and the source wiring, the portion of the conductive thin film 83x which is not covered with the resist patterns 95 and 93a is removed. In the example of FIG. 14, the conductive thin film portion between the word lines and sandwiched by the drain regions D and a part of the conductive thin film on the word lines W _{n-1 to} W _{n + 1} are shown. It will be removed by etching means. However, as the semiconductor non-volatile memory becomes finer, the pitch of the word lines becomes narrower, or the word lines become thinner and the thickness of the word lines becomes thicker to compensate for this,
Since the word line pattern has a high aspect ratio, the conductive thin film is often formed so as to fill the recess in the region between the word lines (that is, in the recess). Therefore, in many cases, the conductive thin film is thicker in the portion between the word lines than in the portion on the word lines. FIG. 15A is a cross-sectional view of a main part showing this state, and is a cross-sectional view of a portion corresponding to the portion P in FIG. 4B. In FIG. 4B, the conductive thin film 83x is drawn in a conformal shape (having the same film thickness at the peaks and valleys), but in reality, as shown in FIG.
The film thickness of the conductive thin film portion between the word lines becomes t ₁ , and the film thickness of the conductive thin film portion on the word line becomes t ₂ (t ₂ <t ₁ ). In this state, naturally, even in the field region between the drain regions of the memory cells, the thickness of the conductive thin film portion between the word lines becomes t ₃ , as shown in FIG. The film thickness of the thin film portion is t ₂ (t ₂
<T ₃ ) and so on. By the way, in order to obtain the drain pad and the source wiring as desired, an unnecessary portion of the conductive thin film must be removed. Therefore, in this case, as shown in FIG. The portions Ia and Ib of the thin film portion and the conductive thin film portion II on the field region between the word lines and between the drain regions must be removed. However, as described above, since the film thickness t ₃ of the conductive thin film portion II on the field region between the drain regions is thicker than the film thickness t ₂ of the conductive thin film portions Ia and Ib on the word lines, the space between the word lines is reduced. During the removal of the conductive thin film portion II, the conductive thin film portions Ia and Ib on the word line are removed to expose the word line. Therefore, in the subsequent etching, the word line (actually, the control gate or floating gate) is removed. It is itself etched. In addition,
If the etching of the conductive thin film is terminated when the conductive thin film portion on the word line can be removed, the conductive thin film portion that should be originally removed cannot be completely removed and remains as a filament, so pattern the drain pad. It's out of the question because you can't do it in the first place. The risk of damaging the word line is one mask (pattern of the second invention) for patterning the drain pad and the source wiring, which has been described with reference to FIGS. 7 and 8 in the third embodiment of the second invention. In the third embodiment, the same occurs when the mask for forming the source region is formed of a silicon oxide film. FIG. 16 shows the state at a position (position on the field area) corresponding to FIG. 15B. However, in the case of the example of FIG. 16, an example is shown in which the conductive thin film 83x is conformally grown on the substrate and the word lines are filled with the insulating film 99 in the subsequent formation of the insulating film 99. That is, an example is shown in which the film thickness t _{3 of} the insulating film 99 between the word lines is thicker than the film thickness t ₂ on the word lines. In this case as well, the drain pad cannot be patterned unless the insulating film portion between the word lines having a film thickness t ₃ and the conductive thin film thereunder are etched. However, if so, the insulating film having a film thickness t ₃ is formed. The word line portion is damaged during the etching of the portion. Therefore, these problems can be avoided by applying the third invention as described below.

3-2. Third Embodiment of the Invention This embodiment will be described with reference to FIGS.

First, a known method, for example, the first method of the second invention.
A word line is obtained by forming a gate insulating film, a floating gate, a control gate, and the like on a semiconductor substrate according to the procedure described with reference to FIG. In this case, at least the control gates connected to each other form a word line. However, in this embodiment, as shown in the plan view of FIG. 17, adjacent word lines W _n-1 and W _{n are}
Each word line is formed in advance so that the word line interval x ₁ in the space sandwiched by the drain regions D among the spaces sandwiched by is narrowed to the extent that an insulating film is embedded in the predetermined portion. That is, the word line interval x ₂ in the portion where the drain region D is formed is a dimension determined by design (however, it is preferable that the insulating film be formed as conformally as possible in the portion between the word lines). On the other hand, each word line is formed by a well-known fine processing technique so that the word line interval x ₁ in the space sandwiched by the drain regions D is narrower than x _{2 and} has the predetermined dimension. Although the source region and the drain region are not originally formed immediately after the word line is formed, the source region S and the drain region D are shown in FIG. 17 in order to clarify the positional relationship.

Next, a drain region and a source region are formed by a known method.

Next, an insulating film such as a silicon oxide film is formed on the entire surface of this sample by a known and suitable film forming method. The film forming conditions are such that the insulating film is embedded in the portion between word lines where the word line interval is x ₂ . Figure 1
8A is a cross-sectional view showing the state of the insulating film in the portion where the word line interval is x ₁ in the sample after the formation of the insulating film 200 is shown in FIG. 18B. The state of the part with x ₂ is also shown.

Next, this insulating film 200 is etched by anisotropic etching until the surface of the semiconductor substrate 61 is exposed in the drain region. When this etching is completed, as shown in the plan view of FIG. 19, a sidewall film made of an insulating film is formed on the sidewalls of the word lines W _n-1 , W _n in contact with the drain region D and the sidewalls on the source region S side. 81b (hatched portion) can be formed, while the portion where the word line interval between the word lines is x ₁ is filled with the insulating film 200 (black dot portion). For better understanding, a cross-sectional view of a portion where the word line spacing between the word lines of the sample after the etching is x ₂ is shown in FIG. 20A, and the word line spacing between the word lines is x _1.
20B is a cross-sectional view of each of the portions described above. As is clear from FIG. 20B, the space including the drain region in the space between the word lines and the space above the field region is filled with the insulating film 200, and
The surface of the word line W _{n−1 and} the surface of the insulating film 200,
The surface of the word line W _n is continuous and flat.

Next, a conductive thin film 83x for forming a drain pad and a source wiring is formed on this sample. The conductive thin film 83x is formed so as to be in contact with the drain region D (similarly on the source region side) because it follows the unevenness of the base on the drain region as shown in FIG. On the field region, as shown in FIG. 21B, the conductive thin film 83x has a uniform film thickness and a flat surface due to the embedded insulating film 200. The state of FIG. 21 (B) and FIG.
Comparing with the state of (B), the superiority of the third invention can be understood. 21A, the conductive thin film 83x
Shows the state in which the film is formed conformally, but it is of course possible that the film is formed so that the film thickness in the recess becomes thick. This is because this portion becomes the drain pad (source wiring on the source region side) and should be left behind.

Next, on this sample, for example, the first of the second invention
The first resist pattern 93a for forming the source wiring and the second resist pattern 95 for forming the drain pad are respectively formed by the procedure described with reference to FIGS. 4A to 4C of the embodiment (FIG. 21 ( (See A) and (B)). Thereby, like the second invention, each resist pattern can be formed finer than the resolution limit of the current lithography technique by using the current lithography technique.

Next, the portion of the conductive thin film 83x not covered with the first and second resist patterns is etched. In this etching, an unnecessary portion of the conductive thin film 83x, that is, a part of the conductive thin film portion on the word line or the conductive thin film portion on the field between the drain regions (see FIG. 21).
Although the thin film 83x portion of (B) is removed, since the film thickness of this portion is uniform in the present invention, removal of this conductive thin film portion until the word line surface is exposed can be performed with good controllability. . Therefore, it is possible to prevent the risk of the word line being damaged.

After that, for example, an intermediate insulating film is formed, a contact hole is formed, and a metal wiring is formed by the method described in the second embodiment.

The third embodiment of the second invention is provided on the conductive thin film 83x of the sample which is in the state as shown in FIGS. 21A and 21B after the formation of the conductive thin film 83x. As described above, in the case where an insulating film for obtaining a source wiring formation mask is further formed, the obtained sample is a sample in the state as shown in FIGS. 22A and 22B. In other words, the mask forming silicon oxide film 99 has an effect of filling the recess because the recess is narrowed at the portion between word lines where the source region is formed because the conductive thin film 83x is already formed. It is considered that the film thickness of the insulating film portion in the recess becomes thicker than other portions. However, since this is the part to be left as the source wiring in the first place, the insulating film does not need to be removed, and considering the subsequent steps, this part should be flattened as much as possible. There is no problem even if such an insulating film is buried.
On the other hand, on the field region between the drain regions, FIG.
As shown in (B), the insulating film 99 is formed on the conductive thin film 83x having a uniform film thickness and a flat surface due to the embedded insulating film 200. After all, the film thickness is uniform and flat. Therefore, even when the unnecessary portions of the insulating film 99 and the conductive thin film 83x are removed, the risk of damage to the word line can be prevented.

In the embodiment of the third invention, an example of manufacturing the semiconductor nonvolatile memory of the first invention by the method of the third invention has been shown. However, the third invention can also be applied to a type of memory (for example, the one shown in FIG. 12) in which the source regions are connected by the impurity diffusion layer without providing the source wiring. In that case, the space to be filled with the insulating film among the spaces sandwiched by the adjacent word lines is the space on the field region between the drain regions and the space between the word lines on the side where the source region is formed (see, for example, FIG. In the example of 14, the space between the word lines W _n-2 and W _n-1 or the space between the word lines W _n and W _{n + 1} ) may be used. By doing so, the word line is not damaged even when only the drain pad is formed.

4. Fourth Invention According to the method of the second invention described above, it is possible to manufacture a fine semiconductor non-volatile memory device having a resolution limit equal to or less than the resolution limit of the current photolithography technology while using the current photolithography technology. It was Further, according to the method of the third invention described above,
It was possible to prevent the word line from being damaged when patterning the conductive thin film. However, the method of the second invention requires two lithographic processes in the first and second embodiments, and the conductive thin film and the insulating film in the third embodiment. Two film formations for forming each, two lithography processes, and two dry etchings were required. Further, as a result, the conductive thin film is exposed in two times, so that a large pattern alignment margin must be expected. Specifically, for example, if the alignment accuracy is ± 0.2 μm, the alignment margin of ± 0.2 μm is set in each of the lithography for obtaining the resist pattern for forming the source wiring and the lithography for obtaining the resist pattern for forming the drain pad. Therefore, in design, the alignment margin between the source wiring and the drain pad must be at least ± 0.4 μm. For this reason, the edge of the source wiring and the edge of the drain pad cannot be brought close to each other by 0.4 μm or less, which becomes an obstacle when the cell size is further reduced. When a resist and an insulating film are used together as an etching mask for a conductive thin film as in the third embodiment of the second invention, the etching rates of the resist and insulating film are different, so that the dimensional conversion difference is also different, which is a point of dimensional control. Is not preferable. Such a problem in the second invention similarly occurs in the third invention. Therefore, for example, by applying the fourth invention as follows, these problems can be solved.

17 to 20 of the above-described third embodiment of the invention.
The insulating film 200 is embedded only in the space between the word lines, which is the space between the drain regions and over the field region, by the same procedure as described with reference to FIG.
In the word line other than the area where the gates are buried, the sidewall 81b of the insulating film is formed over the entire sidewall (see FIG. 20).

Next, a conductive thin film for forming a drain pad and a source wiring is formed on the entire surface of this sample.
In the fourth invention, as shown in FIG. 23A, in the portion where the insulating film 200 between the word lines is not buried, the film thickness t _A of the conductive thin film 83x is the film in the portion on the word line. The conductive thin film 83x is formed so as to be thicker than the thickness t _B. In such film formation, for example, the film formation conditions are optimized, or the side wall film 81b is formed while the insulating film 200 is not filled with the distance between the word lines in which the source regions are formed when the insulating film 200 is formed. After that, it is possible to set the gap so that the filling effect by the conductive thin film is generated. At this time, since the insulating film 200 is buried and flattened on the field region between the drain regions, the conductive thin film is formed in a state where the film thickness is uniform and the surface is flat (FIG. 23). (See (B)). Note that FIG.
Shows an example in which the surface of the conductive thin film 83x is flat even on the recesses between the word lines. This is because it is advantageous for the subsequent steps. However, for example, as shown by the one-dotted broken line Q in FIG.

Next, a resist pattern 201 is formed as a mask for covering each portion of the conductive thin film 83x that corresponds to the drain region (each portion that corresponds to the drain pad formation planned region) (FIG. 24B). In the method of the second invention, the resist pattern for forming the source wiring was formed after this, but this is not done in the fourth invention.

Next, the conductive thin film 83x is removed by a thickness thicker than the thickness t _{B of the} portion on the word line and thinner than the thickness t _{A of the} portion formed between the word lines ( FIG. 24 (B)). Preferably, the etching is stopped when the conductive thin film portion on the word line is removed. Under such etching conditions, the conductive thin film 8
3x remains only in the portion masked by the resist pattern 201 and the portion embedded between the word lines. The former becomes the drain pad 85 and the latter becomes the source wiring 83 (FIG. 24B).

After that, for example, the formation of the intermediate insulating film, the formation of the contact hole, the formation of the metal wiring, etc. are performed by the method described in the embodiment of the second invention.

According to the method of the fourth embodiment of the present invention, when the drain pad and the source wiring are obtained, the conductive thin film is formed once, the photolithography step is formed once, and the etching step 1 is formed.
Since the number of times is sufficient, the process can be simplified as compared with the respective embodiments of the second invention. Further, the source wiring can be formed in a self-aligned manner. From these things, it is possible to reduce the alignment margin in the lithography process.
The drain pad and the source wiring can be placed closer to each other than in the case of the second invention. Therefore, it is more advantageous than the second invention in terms of shortening the process and reducing the cell size. Further, by setting the conditions for forming the conductive thin film and the etching conditions for this thin film so that the surface of the source wiring becomes flat, the metallization process can be made advantageous in the step after the formation of the source wiring. In addition, since the photolithography step for obtaining the source wiring formation mask can be omitted,
This is also advantageous in that respect because the risk of a reduction in process yield due to reticle defects is reduced.

Although the respective embodiments of the first to fourth inventions of this application have been described above, these inventions are not limited to the above-mentioned examples. For example, the materials used are not limited to those in the embodiment, and other suitable materials may be used. Further, in the third and fourth inventions, the description has been given of the example in which the insulating film is embedded in the predetermined portion between the word lines and the side wall film is formed on the predetermined side wall of the word line at the same time. You can go.

Further, in the above-mentioned third and fourth inventions, among the spaces between the adjacent word lines, the space corresponding to the field region between the drain regions is filled with the insulating film. This was to prevent the inconvenience described with reference to FIGS. 14 to 16 from occurring during the patterning of the conductive thin film at the time of forming the drain pad. However, the space filled with the insulating film corresponds to the case where a similar problem may occur, specifically, in the space between the adjacent word lines, the final space of the conductive thin film to be formed later. Of course, it may be a portion where the portion to be removed is formed.

[0084]

As is apparent from the above description, according to the semiconductor nonvolatile memory of the first invention of this application, each active region has an elongated shape in the first direction and the second region. The structure is divided by the field oxide film in the direction. Therefore, it is possible to eliminate the problem caused by the active region extending in the second direction. Specifically, since the mask alignment misalignment margin size can be reduced, the size of the memory cell in the first direction (the y direction in the embodiment) can be shortened, and due to the misalignment between the floating gate and the field oxide film. The potential fluctuation of the floating gate can be reduced.

Further, since the source regions of the memory cells are connected by the source wiring, not by the impurity diffusion layer,
It is possible to reduce the source resistance and the variation in the source resistance among the memory cells as compared with the case where the impurity diffusion layers are connected. Further, since the source / aluminum wiring, which has been conventionally required, can be eliminated, the dimension of the memory cell in the second direction (x direction in the embodiment) can be shortened accordingly. In addition, the insulation between the source wiring and the control gate and the floating gate is performed by the insulating film covering the upper surface and the side wall of these gates. These insulating films can be formed with high accuracy in a self-aligned manner. Therefore, the distance y between the gates 13 and 15 and the contact hole shown in FIG.
_{Since 4} can be substantially unnecessary, the dimension of the memory cell in the second direction can be shortened also from this.

According to the configuration of the second invention of this application, for example, each source wiring is exposed by the current photolithography technique in the first exposure step, and each drain pad is currently exposed in the second exposure step. When exposed by the photolithography technology, the pitch between the source wiring and the pad portion for the drain can be made equal to or smaller than the resolution limit of the current photolithography technology. In addition, the number of times of film formation and the number of lithography steps can be reduced as compared with the conventional case, since the conductive film formed in the same step can be used.

Further, according to the structure of the third invention of this application, a predetermined portion (a portion to be finally removed of the conductive thin film to be formed later) in each space between adjacent word lines is formed. Part) is flattened in advance, and then a conductive thin film is formed on the entire surface of this sample. Therefore, the portion etched after the conductive thin film is not formed in the concave portion between the word lines but is formed on the flat base, so that the film thickness becomes uniform. Therefore, when the portion of the conductive thin film to be etched is etched, the etching can be finished with good control, and the risk of damaging the base can be prevented. Therefore, for example, the word line is not scraped when the drain pad is formed.

According to the structure of the fourth invention of this application, in addition to the effect of the third invention, the drain pad and the source wiring are formed in a self-aligning manner only by using the mask for forming the drain pad as the etching mask. it can. Therefore, the lithography process for obtaining the source wiring formation mask can be omitted as compared with the third aspect of the invention, so that the process can be simplified and the risk of lowering the process yield can be reduced. In addition, the number of times of lithography can be omitted, so that the photomask combined margin can be reduced, which is advantageous in reducing the cell size.

[Brief description of drawings]

FIG. 1A is a plan view of a main part of a semiconductor nonvolatile memory of an embodiment, and FIG. 1B is a plan view in which some active components are removed from the structure of FIG. is there.

FIG. 2 is a cross-sectional view of essential parts of a semiconductor nonvolatile memory of an example.

3A to 3C are process drawings for explaining the manufacturing method of the first embodiment.

4A to 4C are process diagrams subsequent to FIG. 3 for explaining the manufacturing method of the first embodiment.

5A and 5B are process diagrams following FIG. 4 for explaining the manufacturing method of the first embodiment.

6 (A) to 6 (C) are process drawings for explaining the main part of the manufacturing method of the second embodiment.

7 (A) to 7 (C) are process drawings for explaining the manufacturing method of the third embodiment.

8A and 8B are process drawings following FIG. 7 for explaining the manufacturing method of the third embodiment.

9A and 9B are process diagrams following FIG. 8 for explaining the manufacturing method of the third embodiment.

10 (A) and 10 (B) are process drawings following FIG. 9 for explaining the manufacturing method of the third embodiment.

FIG. 11 is a cross-sectional view showing a memory cell portion of a conventional semiconductor nonvolatile memory.

12A and 12B are plan views for explaining the configuration of a conventional semiconductor nonvolatile memory.

FIG. 13 is a diagram provided for explaining another structural example of the semiconductor nonvolatile memory of the first invention and a background explanation of the second invention.

FIG. 14 is a diagram for explaining the necessity of the third invention.

15 (A) and 15 (B) are views following FIG. 14 for explaining the necessity of the third invention.

FIG. 16 is a view following FIG. 15 for explaining the necessity of the third invention.

FIG. 17 is an explanatory diagram of an example of the third invention, and is a plan view showing a relationship between a word line and a source region and a drain region.

18A and 18B are views following FIG. 17 for explaining the embodiment of the third invention, and are explanatory views of a state immediately after formation of the insulating film 200 in each part of the sample.

FIG. 19 is a view following FIG. 18 for explaining the embodiment of the third invention, and is a plan view showing a state after the insulating film 200 in each portion of the sample is selectively etched.

20 (A) and 20 (B) are views following FIG. 19 for explaining the embodiment of the third invention, showing a cross section showing a state after selectively etching the insulating film 200 in each part of the sample. It is a figure.

21A and 21B are views following FIG. 20 for explaining the embodiment of the third invention, showing the state after forming the conductive thin film 83x and the state after forming the resist pattern in each part of the sample. It is the sectional view shown.

22A and 22B are views following FIG. 21 for explaining the embodiment of the third invention and are explanatory views of an example in which an insulating film is further used as a mask.

23 (A) and (B) are diagrams for explaining an embodiment of the fourth invention.

24 (A) and (B) are views following FIG. 23 for explaining the embodiment of the fourth invention.

[Explanation of symbols]

41: memory cell 42: floating gate 43: control gate 44: insulating film covering each gate 45: source region 46: source wiring 47: drain region 48: pad portion 49: insulating film like intermediate insulating film 50: semiconductor substrate 51 : Interlayer insulating film 52: Contact hole 53: Bit line 61: Semiconductor substrate 63: Active area 65: Memory cell 67: Field insulating film 69: Floating gate 71: Control gate 73: Source area 75: Drain area 81: Cover the gate Insulating film 81a: upper surface insulating film 81b: side wall insulating film 83: source wiring 85: drain pad portion 87: bit line 89: interlayer insulating film 91: contact holes Wn _{-2 to} Wn _{+ 1} : word line D: Drain region S: Source region 200: Insulating film 201: Mask

Claims (8)

[Claims] 1. A semiconductor substrate is provided with a plurality of active regions, which are long in the first direction and for sequentially forming a plurality of memory cells in the first direction, arranged in the second direction. The memory cell includes a memory cell having a floating gate, a control gate, a source region and a drain region, and using the active region as an active layer. Is covered with an insulating film, and source wirings for connecting the source regions of the memory cells arranged in the second direction are arranged side by side in the first direction. . 2. The semiconductor non-volatile memory according to claim 1, wherein a pad portion is provided on each drain region of each memory cell. 3. The method for manufacturing a semiconductor nonvolatile memory according to claim 2, wherein the pad portion and the source wiring are formed by forming a conductive thin film over the entire area including the pad portion and the source wiring formation planned region. One of the mask for forming the pad portion and the mask for forming the source wiring is formed on the thin film by the first photolithography step, and the step of forming each of the masks is performed by the second photolithography step. A method of manufacturing a semiconductor nonvolatile memory, which is performed by a step including a step of forming the other one. 4. A plurality of memory cells having a floating gate, a control gate, a source region and a drain region are arranged in a matrix, and a plurality of memory cells arranged in one direction in the matrix are connected together to form a plurality of memory cells. In manufacturing a semiconductor nonvolatile memory including word lines, after the formation of the word lines is completed, sidewalls made of an insulating film are formed on at least the sidewalls of the portions contacting the source region and the sidewalls of the drain region. A step of forming each film, and a step of filling at least a space on the field region between the drain regions with an insulating film in a space excluding a space corresponding to the drain region in each space sandwiched by adjacent word lines, , The entire surface of the sample on which the side wall film has been formed and which has been filled with the insulating film. A method of manufacturing a semiconductor nonvolatile memory, comprising: a step of forming a conductive thin film on a surface; and a step of patterning the conductive thin film into a predetermined shape. 5. A plurality of memory cells each having a floating gate, a control gate, a source region and a drain region are arranged in a matrix form, and a plurality of memory cells arranged in one direction in the matrix are connected to each other. In manufacturing a semiconductor non-volatile memory including word lines, after the formation of the word lines is completed, each word line is formed on all sidewalls of the source region side and at least the drain region of the drain region side. A step of forming a side wall film made of an insulating film on the side wall of a portion in contact with each other, and a step of filling only the space on the field region between the drain regions among the spaces sandwiched by adjacent word lines with the insulating film A conductive thin film is formed on the entire surface of the sample on which the sidewall film has been formed and the insulating film has been embedded. A step of forming a portion of the conductive thin film formed in the space between the word lines to be thicker than the other portions, and a mask covering each portion of the conductive thin film which is on the drain region. A step of forming on the conductive thin film, and after forming the mask, the conductive thin film is thicker than the film thickness of a portion on the word line, and a portion formed between the word lines. And a step of removing only a thickness smaller than the thickness of the semiconductor non-volatile memory. 6. The method for manufacturing a semiconductor nonvolatile memory according to claim 4, wherein the formation of the sidewall film and the filling with the insulating film include the following steps (a) to (c). A method for manufacturing a semiconductor non-volatile memory, which is performed simultaneously. (A) Each word line is formed in advance so that a word line interval in a portion to be filled with the insulating film in a space sandwiched between adjacent word lines becomes narrow enough to fill the insulating film in the intended portion. Process. (B) A step of forming an insulating film on the entire surface of the sample on which the word line is formed. (C) A step of selectively removing the insulating film by anisotropic etching. 7. The method of manufacturing a semiconductor nonvolatile memory according to claim 4, wherein the conductive thin film is a pad forming film formed on a drain region of each memory cell, and a source of each memory cell. A method of manufacturing a semiconductor non-volatile memory, wherein the film also serves as a film for forming a source wiring that connects regions to each other. 8. The method of manufacturing a semiconductor non-volatile memory according to claim 4, wherein a region of the conductive thin film, which is formed later, in each of the spaces sandwiched by adjacent word lines, is filled with the insulating film. A method for manufacturing a semiconductor nonvolatile memory, wherein a portion to be finally removed is formed.