JP2003068894A - Semiconductor storage device and method for forming the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate a writing operation and an erasing operation and to reduce power consumption by reducing the resistance of a well region in a semiconductor storage device having well regions partitioned by an element isolation region used as bit lines. SOLUTION: The semiconductor storage device comprises an N-type deep well region 331 formed on a semiconductor substrate 351 and further a P-type shallow well region 332 formed on the well region 331. The well region 332 is isolated in a band-like state by an element isolation region 316 and the N-type deep well region 331, and functioned as bit lines. The storage device further comprises a P-type dense impurity concentration region 332a formed in the P-type well region 332 becoming a third bit line in such a manner that the impurity concentration region 332a is interposed between P-type thin impurity concentration regions 332b and 332c. Thus, the resistance and a junction capacity can be suppressed to small values.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for forming the same. More specifically, the present invention relates to a memory cell array in which well regions divided by element isolation regions are used as bit lines and a method of forming the same.

[0002]

2. Description of the Related Art Conventionally, in a nonvolatile memory having a floating gate, a technique in which a well region divided by an element isolation region is used as a bit line is disclosed in Japanese Unexamined Patent Publication No. Hei 11 (1999).
No. 177068. The above conventional technique will be described with reference to FIGS.

FIG. 22 is a circuit diagram of the above-mentioned conventional memory cell array. B0, B1, and B2 are drain lines (first bit lines), and S0, S1, and S2 are source lines (second bit lines). The above-mentioned conventional technique is characterized in that the well region is elongated in the same direction as the bit line by the element isolation region, and each of the elongated well regions functions as the third bit lines PW0, PW1, and PW2. A memory transistor 931 is provided between the pair of first and second bit lines (for example, S0 and B0).
And the selection transistor 932 are connected in series.
The memory transistor word lines MW0, MW1 and MW2 are connected to the control gate of the memory transistor 931 and selected transistor word lines SW0, SW1 and SW.
2 is connected to the selection gate electrode of the selection transistor 932.

FIG. 23 is a cross-sectional view of the above-described conventional memory cell array taken along the memory transistor word line. Further, FIG. 24 is a cross-sectional view when cut in the bit line direction. An N-type well 912 is formed in the semiconductor substrate 911. Although a P-type well is formed on the N-type well 912, the element isolation insulating film 914 extending in the bit line direction allows the elements 913a and 913 to be formed.
It is divided into b and 913c to form a third bit line.

Third bit lines 913a, 913b, 913
A control gate 916 is formed on c via a gate insulating film 917, a floating gate 915, and an inter-electrode insulating film 918 to form a memory transistor 931. The control gate 916 extends in a direction perpendicular to each bit line and has a plurality of memory transistors 931.
Memory transistor word lines MW0, MW
1 and MW2.

Third bit lines 913a, 913b, 913
The dummy electrode 92 is formed on the substrate c via the gate insulating film 917, the select gate electrode 919, and the interelectrode insulating film 918.
0 is formed to configure the selection transistor 932. Although not shown, the select gate electrode 919 and the dummy electrode 920 are electrically connected and integrated, and extend in a direction perpendicular to each bit line to connect a plurality of select transistors 932 to each other. SW0, S
It constitutes W1 and SW2.

Although not shown, the source diffusion layer 921 (source region) of the memory transistor 931 has source lines (second bit lines) S0 and S extending in the direction perpendicular to each word line.
1, S2 are connected. Although not shown, the drain diffusion layer 922 of the selection transistor 932 is connected to the drain lines (first bit lines) B0, B1, and B2 extending in the vertical direction to the word lines. The intermediate diffusion layer 923 serves as the drain region of the memory transistor 931 and the source region of the selection transistor 932.

In the above-mentioned conventional memory cell array, since the potential of the well region can be controlled for each bit line, the potential of the source diffusion layer and the potential of the well region (third bit line) can be made the same. . For example, at the time of writing (here, electron injection into the floating gate is writing), + is applied to the selected memory transistor word line.
9V, 0V for unselected memory transistor word lines and all selected transistor word lines, -3.5V for selected source line (second bit line) and selected third bit line (well region), unselected source 0 V is applied to each of the line (second bit line) and the non-selected third bit line (well region) to open all drain lines (first bit lines). At this time, the potential of the source diffusion layer and the potential of the well region (third bit line) are the same in all memory cells. Therefore, unlike the case where the well region is shared, it is not necessary to secure the breakdown voltage due to the potential difference between the source diffusion layer and the well region. The necessity of ensuring this breakdown voltage becomes important as the element becomes finer. Therefore, the above conventional technique facilitates miniaturization of the device.

[0009]

However, in the above-mentioned conventional memory cell array, since the resistance of the well region forming the third bit line is high, the delay time is large and the write and erase operations can be speeded up. There was a problem that it was difficult.

For example, consider a memory cell array in which 10 ³ memory cells are connected to one set of bit lines.
When the minimum processing size is F, the width of the third bit line (see FIG.
W of 3 is approximately F. On the other hand, if the size of the memory cell in the bit line direction is, for example, 6F, the length of the third bit line is about 6 × 10 ³ F. If the sheet resistance of the third bit line (well region) is 5 × 10 ³ Ω / □,
The resistance of the third bit line is about 3 × 10 ⁷ Ω. further,
The capacity associated with the third bit line per memory cell is 1 × 10.
^-14 F, each 3rd bit line has about 1 x 10
- so that the capacity of ¹¹ F is present. At this time, the delay time of the third bit line is represented by the product of resistance and capacitance, and is approximately 3 × 1.
It becomes 0 ⁻⁴ seconds (0.3 milliseconds), which is much higher than the writing speed of the flash memory (for example, 10 microseconds). Therefore, there has been a problem that the writing operation (erasing operation) is extremely delayed.

The present invention has been made to solve the above problems, and its object is to significantly improve the resistance of the well region in a non-volatile memory cell array in which the well region divided by the element isolation region is used as a bit line. To enable high speed operation and to provide a method for manufacturing such a memory cell array.

[0012]

[Means for Solving the Problems]
Therefore, the semiconductor memory device of the first invention is provided on the semiconductor substrate.
A deep well region of one conductivity type is formed,
Of multiple second conductivity type shallow well regions on the deep well region of
Regions are formed to form the deep well region of the first conductivity type and
A plurality of memory cells are formed on the plurality of second conductivity type shallow well regions.
A memory cell array in which the memory cells are arranged in a matrix
A conductor storage device comprising a plurality of second conductivity type shallow wires
The well region is an element isolation region and the deep well of the first conductivity type.
Are electrically isolated from each other by a shell region,
Impurities that give the second conductivity type in the shallow well region of the conductivity type
Is 1 × 10 ²⁰cm^-3High-concentration impurity layer existing at the above concentration
Is formed.

In the present specification, the first conductivity type means P type or N type. The second conductivity type means N type when the first conductivity type is P type and P type when the first conductivity type is N type.

According to the above structure, the second conductivity type is provided in the shallow well region of the second conductivity type electrically isolated from each other by the element isolation region and the deep well region of the first conductivity type. A region containing a high concentration of impurities is formed. Therefore, the resistance of the second conductivity type shallow well region can be significantly reduced. Therefore, in the memory cell array in which the second-conductivity-type shallow well region is used as a bit line, the delay of the bit line formed of the second-conductivity-type shallow well region can be significantly reduced, and the write operation and the erase operation can be performed. It is possible to prevent the speeding up of the operation from being hindered. Therefore,
A semiconductor memory device capable of high-speed operation is provided.

In one embodiment, the shallow well region of the second conductivity type is a region of a low impurity concentration of the second conductivity type above or below a region of a high impurity concentration of the second conductivity type. Is characterized by having a structure that exists.

According to the above embodiment, the resistance of the second conductivity type shallow well region can be sufficiently reduced, and
A desired threshold value can be easily obtained by appropriately maintaining the impurity concentration of the channel region, and further, the junction capacitance between the shallow well region of the second conductivity type and the source / drain region of the memory element can be suppressed to be small. In addition, the junction capacitance between the second-conductivity-type shallow well region and the first-conductivity-type deep well region can be suppressed to a small value. Therefore, it is possible to further reduce the delay of the bit line formed of the shallow well region of the second conductivity type and suppress the power consumption.

In the semiconductor memory device according to the second aspect of the invention, a first conductivity type deep well region is formed on a semiconductor substrate, and a plurality of second conductivity type deep well regions are formed on the first conductivity type deep well region.
A semiconductor memory having a memory cell array in which a conductivity type shallow well region is formed, and a plurality of memory cells are arranged in a matrix on the first conductivity type deep well region and the plurality of second conductivity type shallow well regions. In the device, the plurality of second conductivity type shallow well regions are electrically isolated from each other by the element isolation region and the first conductivity type deep well region, and function as bit lines. It is characterized in that a metal layer or a silicide layer is formed in the shallow well region.

According to the above structure, a metal layer or a silicide layer is provided in the shallow well region of the second conductivity type electrically isolated from each other by the element isolation region and the deep well region of the first conductivity type. Has been formed.
Therefore, the resistance of the second conductivity type shallow well region can be significantly reduced. Therefore, in the memory cell array in which the second-conductivity-type shallow well region is used as a bit line, the delay of the bit line formed of the second-conductivity-type shallow well region can be significantly reduced, and the write operation and the erase operation can be performed. It is possible to prevent the speeding up of the operation from being hindered. Therefore, a semiconductor memory device that can operate at high speed is provided.

Further, one embodiment is characterized in that a part of the shallow well region of the second conductivity type exists above the upper surface of the element isolation region.

According to the above embodiment, without changing the thickness of the entire second conductivity type shallow well region,
The depth of the lower surface of the shallow well region of the second conductivity type can be made shallow. As a result, the element isolation region can be made shallow. If the element isolation region can be made shallow, the step of filling the insulating film when forming the element isolation region becomes easy. Therefore, it becomes possible to more easily form a semiconductor memory device in which the bit line formed of the second conductivity type shallow well region has a small delay.

According to a third aspect of the present invention, there is provided a method of forming a semiconductor memory device, wherein a first conductivity type deep well region is formed on a semiconductor substrate, and a plurality of second conductivity type deep well regions are formed. A shallow well region of conductivity type is formed,
There is provided a memory cell array in which a plurality of memory cells are arranged in a matrix on a deep well region of conductivity type and a plurality of shallow well regions of second conductivity type, and the shallow well regions of second conductivity type are elements. The isolation region and the first-conductivity-type deep well region are electrically separated from each other to function as a bit line, and the second-conductivity-type shallow well region has a high concentration of impurities imparting the second-conductivity type. A method of forming a semiconductor memory device, wherein a high-concentration impurity layer is formed, comprising: forming a single crystal semiconductor film after forming the element isolation region and the high-concentration impurity layer on a semiconductor substrate. It is characterized in that a step of selectively epitaxially growing the high-concentration impurity layer is performed.

According to the above method, since the single crystal semiconductor film is selectively epitaxially grown after the element isolation region and the high-concentration impurity layer are formed, the shallow well of the second conductivity type that functions as a bit line is formed. While forming a low resistance layer inside the region, a region having a sufficiently low concentration of impurities (impurities or metal atoms that give conductivity) and few crystal defects is formed in the upper layer portion of the second conductivity type shallow well region. can do. Therefore, the junction capacitance between the shallow well region of the second conductivity type and the source / drain region of the memory element is reduced, and the threshold adjustment of the memory element is facilitated,
Alternatively, it is possible to create a memory element with a small leak current and good characteristics.

In one embodiment, the element isolation regions that meander in the first direction are formed side by side in the second direction intersecting the first direction, and the adjacent element isolation regions are formed. The well regions are defined so as to extend meandering in the first direction, and impurity diffusion regions functioning as a source region or a drain region are formed at the respective turning points of the meandering in the well regions. , A channel region is defined between the impurity diffusion regions adjacent to each other in the same well region, and a plurality of word lines extending in the second direction are formed in each well region via a film having a memory function. A first bit line provided so as to pass over the channel region and extending in the first direction,
The second bit line, which is provided so as to pass over the impurity diffusion region provided at the turn-back portion on one side of the meandering in the same well region and extends in the first direction, has the meandering in the same well region. Is provided so as to pass over the impurity diffusion region provided at the turning point on the other side of
It is characterized in that the first bit line and the second bit line are respectively connected to the impurity diffusion regions existing therebelow via contact holes.

According to the above embodiment, the area of one memory cell is as small as 4F ² (F is the minimum processing pitch), so that high integration is possible. Furthermore, according to the above embodiment, writing and erasing can be performed bit by bit. Therefore, a semiconductor memory device capable of high-speed operation, high integration, and writing and erasing bit by bit is provided.

In one embodiment, the element isolation regions extending in the first direction are formed side by side in the second direction intersecting the first direction, and the adjacent element isolation regions are formed. The well regions extending in the first direction are defined between the regions, the word lines extending in the second direction are formed side by side in the first direction, and each word line is formed. Impurity diffusion regions functioning as a source region or a drain region are formed in the well regions located between, and channel regions are defined between adjacent impurity diffusion regions in the same well region,
The word line is arranged on each channel region through a memory film having a memory function.
A plurality of bit lines extending in the direction of the above are formed above the well regions, and are connected to the impurity diffusion regions in the well regions located below every other via contact holes. A plate electrode is formed below the bit line and is connected to an impurity diffusion region to which the bit line is not connected, and the contact hole passes through a hole or slit provided in the plate electrode. It is characterized by being provided as follows.

According to the above embodiment, the first and second
Since one of the bit lines is used as the common plate electrode, the structure of the memory cell array can be simplified. Therefore, an improvement in yield is achieved.

Further, one embodiment is characterized in that the memory functional film is a laminated film of a silicon nitride film and a silicon oxide film.

According to the above embodiment, the memory function film is a laminated film of a silicon nitride film and a silicon oxide film and has a function of trapping charges. Therefore, the problem of leakage of stored charges is reduced as compared with the case where the conductive film is a floating gate. Therefore, the reliability of the device can be improved.

Further, one embodiment is characterized in that the memory functional film is an insulating film containing fine particles of a semiconductor or a conductor in a scattered manner. In addition, the above-mentioned "fine particles" mean particles having a size of nanometer (nm) order.

According to the above embodiment, the memory functional film is an insulating film containing fine particles of a semiconductor or a conductor in a scattered manner, so that the memory charge of the memory film is larger than that in the case where the conductor film is a floating gate. Leakage problems are mitigated. Therefore, the reliability of the device is improved.

Further, in one embodiment, the memory function film is an insulating film containing a film made of a semiconductor or a conductor and fine particles made of a semiconductor or a conductor.

According to the above-mentioned embodiment, since the composite film of the semiconductor or conductor and the fine particles of the semiconductor or conductor is used as the memory functional film,
Writing is performed with a voltage of ± 3 V applied to the word line to the second conductivity type shallow well region. Therefore, writing and erasing can be performed with a low voltage.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the embodiments shown in the drawings.

The semiconductor substrate that can be used in the present invention is not particularly limited, but a silicon substrate is preferable. Further, the semiconductor substrate may have a P-type or N-type conductivity. In each of the embodiments, an N-channel type element is mainly described, but a P-channel type element can be formed by reversing the conductivity types of impurities. (First Embodiment) A semiconductor memory device according to the first embodiment is
In the above-mentioned conventional memory cell array, the resistance of the well region is reduced by increasing the impurity concentration of the well region which becomes the third bit line.

The semiconductor memory device of the first embodiment is shown in FIG.
~ It demonstrates using FIG. 1 is a sectional view of the semiconductor memory device of the first embodiment taken along the memory transistor word line, and FIG. 2 is a sectional view taken along the bit line direction. FIG. 3 is a circuit diagram of the semiconductor memory device according to the first embodiment. Further, FIG. 4 shows the first embodiment.
The procedure for forming the semiconductor memory device is described.

First, the configuration of the semiconductor memory device according to the first embodiment will be described with reference to FIGS. 1, 2 and 3.

An N type deep well region 331 is formed on the semiconductor substrate 351. N-type deep well region 3
A P-type shallow well region 332 is formed on 31. The P-type shallow well region 332 is the element isolation region 31.
6 and N-type deep well regions 331 are separated into strips to form third bit lines PW0, PW1 and PW2.

A floating gate 321 is formed on the P-type well region 332 via a gate insulating film 322. A control gate 311 is formed on the floating gate 321 via an insulating film 323. The control gate 311 extends crossing (preferably perpendicularly crossing) the third bit line to form memory transistor word lines MW0, MW1, MW2. A memory transistor 391 is formed in a region where the third bit line intersects with the control gate.

On the P-type well region 332,
A select gate electrode 361 is formed with a gate insulating film 322 interposed therebetween. A dummy electrode 362 is formed on the select gate electrode 361 via an insulating film 323.
Although not shown, the select gate electrode 361 and the dummy electrode 362 are electrically connected and integrated, and extend in parallel with the memory transistor word line to form select transistor word lines SW0, SW1, SW2. is doing. A selection transistor 392 is formed in a region where the third bit line intersects with the dummy electrode.

Although not shown, the source diffusion layer 364 of the memory transistor 391 is composed of an upper metal wiring and has a third structure.
It is connected to a source line (second bit line) extending in parallel with the bit line. Although not shown, the drain diffusion layer 363 of the selection transistor 392 is connected to a drain line (first bit line) formed of an upper metal wiring and extending in parallel with the third bit line. The intermediate diffusion layer 365 also serves as the drain region of the memory transistor 391 and the source region of the selection transistor 392. As a result, the memory transistor 391 and the selection transistor 392 are connected in series between the first bit line and the second bit line. In the above description, the second bit line is the source line and the first bit line is the drain line for convenience of description, but they may be reversed.

A P-type well region 33 to be the third bit line.
A region 332a having a high P-type impurity concentration is formed in 2 to reduce the resistance of the third bit line. The impurity concentration of the region 332a having a high P-type impurity concentration is 1 ×
It is preferably 10 ²⁰ cm ^-3 or more. At this time, the specific resistance of the region 332a having a high P-type impurity concentration is about 10 ⁻³ Ω.
cm, the sheet resistance is 1 × 10 ² Ω / □ when the film thickness is 100 nm. In this case, the invention example was mentioned problems to be solved (capacity of the first present per 3 bit lines is that 1 × 10- ¹¹ F, the length of the third bit line 6 × 1
0 ³ F), the delay time of the third bit line is about 6 ×
It can be set to 10 ⁻⁶ seconds (6 microseconds), which is shorter than the typical write time (10 microseconds) of a flash memory. Therefore, the write operation speed of the memory can be made sufficiently high. Therefore, it is possible to prevent the memory write operation (and erase operation) from being delayed due to the delay of the third bit line formed of the well region.

By the way, as shown in FIG. 1 and FIG.
In the P-type shallow well region 332, a region 332a having a high P-type impurity concentration and a region 332 having a low P-type impurity concentration are included.
It is preferable to have a structure sandwiched between b and 332c. According to such a structure, the P-type shallow well region 3
The resistance of 32 can be made sufficiently small, a desired threshold value can be easily obtained by appropriately maintaining the impurity concentration of the channel region, and further, the P-type shallow well region 332, the source diffusion layer 364, the drain diffusion layer 363, and the intermediate diffusion can be obtained. The junction capacitance with the layer 365 can be suppressed low. Furthermore, the junction capacitance between the P-type shallow well region 332 and the N-type deep well region can be reduced. Therefore, it is possible to further reduce the delay of the third bit line formed of the well region and suppress the power consumption. The region 332a having a high impurity concentration is a region 332b having a low P-type impurity concentration.
Alternatively, it is possible to obtain some of the above effects by providing only one of 332c.

A part of the P type shallow well region 332 preferably exists above the upper surface of the element isolation region 316. By doing so, the P-type shallow well region 332 is formed.
The depth of the lower surface of the P-type shallow well region 332 can be reduced without changing the overall thickness. Thereby, the element isolation region 316 can be made shallow.
If the element isolation region 316 can be made shallow, the step of filling the insulating film when forming the element isolation region becomes easy. Therefore, it is possible to more easily form a semiconductor memory device in which the delay of the third bit line formed of the well region is small. In the shallow P-type well region 332, if a region above the upper surface of the element isolation region 316 is a well upper region and the other regions are well lower regions, the P-type impurity concentration in the well upper region is It is preferable that the concentration is lower than the P-type impurity concentration in the lower well region. As a result, the impurity concentration of the channel region is appropriately maintained and a desired threshold value can be easily obtained.
63, the junction capacitance with the intermediate diffusion layer 365 can be suppressed small.

Next, a procedure for manufacturing the semiconductor memory device according to the first embodiment will be described with reference to FIG.

First, as shown in FIG. 4A, an N type deep well region 331 and an element isolation region 316 are formed on a semiconductor substrate 351. In FIG. 4A, the N-type deep well region 331 is formed up to the surface of the semiconductor substrate, but it does not necessarily have to be formed near the surface and is formed at a depth near the bottom surface of the element isolation region 316. If you have.

Next, as shown in FIG. 4B, a P-type shallow well region is formed. The P-type shallow well region can be formed by implanting boron ions, for example. At this time, a region 332a having a high P-type impurity concentration
It is preferable that a region 332c having a low P-type impurity concentration is formed underneath. The P-type shallow well region and N
The junction depth with the deep type well region is determined by the ion implantation conditions and the subsequent thermal history. The P type shallow well region is electrically isolated by the element isolation region and the N type deep well region. To do. Further, since a large number of crystal defects have occurred after forming the region 332a having a high P-type impurity concentration, it is preferable to perform annealing for recovering the crystal defects.

The region 3 having a high P-type impurity concentration
Instead of forming 32a, a P-type shallow well region containing P-type impurities at a normal concentration (for example, 10 ¹⁶ to 10 ¹⁸ cm ⁻³ ) is formed, and then a metal is formed in the P-type shallow well region. Ions may be implanted to form a metal layer. Alternatively, metal ions that are reactive with semiconductor atoms may be implanted into the P-type shallow well region to form a metal-semiconductor compound layer (a silicide layer when a silicon substrate is used as the semiconductor substrate). Also by the above method, the low resistance layer can be formed in the P-type shallow well region.

Next, as shown in FIG. 4C, a single crystal semiconductor film inheriting the plane orientation of the silicon substrate is selectively epitaxially grown only on the shallow well region. When forming the single crystal semiconductor film, it is preferable not to introduce a gas that gives impurities of a conductive type so that the impurity concentration can be easily controlled later. The procedure for forming a silicon single crystal film using a silicon substrate is shown below. HF
After cleaning the surface of the silicon substrate by (hydrofluoric acid) treatment, for example, a UHV-CVD apparatus (Anerva SRE-
612) at 660 ° C. and at least 1 sccm of Si ₂
When H ₆ gas is flowed, the silicon single crystal film is epitaxially grown only in the region where the surface of the silicon substrate is exposed. The film thickness of the silicon single crystal film is, for example, 30 nm to 200 nm
It can be, but is not limited to this.

As a method of growing the single crystal semiconductor film on the shallow well region, the condition that the single crystal semiconductor film is epitaxially grown only on the shallow well region and the polycrystalline semiconductor film is deposited on the element isolation region is used. Good. The procedure for forming a silicon single crystal film using a silicon substrate is shown below. After cleaning the surface of the silicon substrate by HF treatment, by LPCVD (Low Pressure Chemical Vapor Deposition) method,
For example, 580 to 650 ° C., Si ₂ H ₆ or SiH ₄
If the silicon film is deposited under the condition of gas of 20 to 100 Pa, the single crystal silicon film can be formed in the region where the surface of the silicon substrate is exposed, and the polysilicon film can be formed in the other regions. After that, the polysilicon film may be selectively etched with a mixed solution of hydrofluoric acid, nitric acid, and acetic acid.

The single crystal semiconductor film becomes a region 332b having a low P-type impurity concentration by diffusion of impurities from the region 332a having a high P-type impurity concentration and impurity ion implantation for adjusting a threshold value which will be performed later. P-type shallow well region 332 is formed by 332b and 332c.
However, the region 332b in which the P-type impurity concentration is low
Is formed after forming the P-type impurity-rich region 332a, it is possible to minimize the impurity diffusion from the impurity-rich region 332a. Therefore, it becomes easy to reduce the junction capacitance between the P-type shallow well region and the source / drain region and to adjust the threshold value of the memory element. Further, the crystal in the region 332b having a low P-type impurity concentration is not damaged by the ion implantation when forming the region 332a having a high P-type impurity concentration. Therefore, it is possible to form a memory element having good characteristics.

Next, a semiconductor memory device is completed by forming a gate insulating film, a floating gate, a control gate, an upper wiring, etc. by a known method.

The above procedure gives an example of a specific method for forming the semiconductor memory device of the first embodiment. According to the above procedure, a region having a high impurity concentration is formed inside the shallow well region serving as the third bit line, while a region having a sufficiently low impurity concentration and a small number of crystal defects is formed in the upper layer portion of the shallow well region. Can be formed. Therefore, the junction capacitance between the shallow well region and the source / drain region can be easily reduced, and the threshold value of the memory element can be easily adjusted, so that a memory element having excellent characteristics can be manufactured.

Even when a metal layer or a metal-semiconductor compound layer is formed in the P-type shallow well region, the upper layer portion of the P-type shallow well region is a region with few metal impurities and crystal defects. can do. Therefore, it is possible to form a memory element with a small leak current.

As is clear from the above description, in the semiconductor memory device of the first embodiment, the well region divided by the element isolation region has the region containing the impurity at a high concentration. The resistance of the well region can be significantly reduced. Therefore, when the well region is used as the bit line of the memory cell array, the delay of the bit line can be remarkably reduced, so that the speeding up of the write operation and the erase operation can be prevented from being hindered. Therefore, a semiconductor memory device that can operate at high speed is provided. (Second Embodiment) A semiconductor memory device according to the second embodiment is
A memory cell array using a well region divided by an element isolation region as a bit line, the resistance of the well region is reduced by increasing the impurity concentration of the well region, and the area of the memory cell is small and highly integrated. It is possible to make it.

The second embodiment of the present invention will be described below with reference to FIGS.

5 to 9 are schematic views of a memory cell array which is a semiconductor memory device according to an embodiment of the present invention. FIG. 5 is a schematic plan view. 6 is a sectional view taken along the section line AA ′ of FIG. 5, FIG. 7 is a sectional view taken along the section line BB ′ of FIG. 5, and FIG. 8 is a section surface of FIG. It is sectional drawing seen from the line CC '. FIG. 9 is a circuit diagram of a memory cell array which is a semiconductor memory device according to the second embodiment of the present invention.

First, the structure of the semiconductor memory device of the present embodiment will be described with reference to FIGS. As can be seen from FIGS. 5 to 8, the N-type deep well region 131 is formed on the semiconductor substrate 151. A P-type shallow well region 132 is formed on the N-type deep well region 131. Further, a plurality of element isolation regions 116 are formed so as to extend meandering in the lateral direction in FIG. 5 (in FIG. 5, each meandering band-like region is shaded). The vertical pitch of the element isolation regions 116 is 2F (F
Is set to the minimum processing pitch). The P-type well region 132 is separated by the element isolation region 116 and the N-type deep well region 131 into a strip shape that meanders in the lateral direction in FIG. 5 to form a third bit line.
In the P-type shallow well region 132, the region 132a having a high P-type impurity concentration is the region 1 having a low P-type impurity concentration.
It is preferable to have a structure sandwiched between 32b and 132c. Further, it is preferable that a part of the P-type shallow well region 132 exists above the upper surface of the element isolation region 116.

As can be seen from the combination of FIG. 5 to FIG. 8, N ⁺ as impurity diffusion regions are formed at the respective folding points (portions corresponding to the contacts 114 and 115) of the meandering of the P-type shallow well region 132. A diffusion layer 134 is formed. Each N ⁺ diffusion layer 134 acts as a source region or a drain region depending on the selection by the bit line when using this memory. At that time, adjacent N ⁺ diffusion layers 134
The regions between the two become the channel regions.

A plurality of word lines 11 made of polysilicon
1 is formed so as to extend straight (crosswise to the direction in which the element isolation region 116 extends (vertical direction in FIG. 5, preferably vertical direction)). The horizontal pitch of the word lines 111 is set to 2F. Word line 11
The upper portion of the P-type shallow well region 132 covered with 1 serves as a channel region. The channel region and the word line 111 are separated by a laminated film including a tunnel oxide film 122, a floating gate 121, and a silicon oxide film 123. The word line 111 plays the role of a control gate on this channel region.

A plurality of first bit lines 112 made of the first layer metal are formed so as to intersect the word lines 111 (horizontal direction in FIG. 5) and extend straight. The vertical pitch of the first bit lines 112 is set to 2F, and the first bit lines 112 are set on the N ⁺ diffusion layer 134 provided at the folding point on one side (the mountain side in FIG. 5) of the meander in the same P-type shallow well region 132. It is provided to pass through. The first bit line 112 and the N ⁺ diffusion layer 134 immediately below the first bit line 112 are connected by a first bit line contact 114 at a pitch of 4F in the horizontal direction. Further, the plurality of second bit lines 113 made of the second layer metal are connected to the first bit line 1
It is formed so as to extend straight in parallel with the first bit line at a position which becomes the gap of the first bit line in the same direction as 12. The vertical pitch of the second bit lines 113 is set to 2F, and the N ⁺ diffusion layer 134 provided at the folded portion on the other side (valley side in FIG. 5) of the meander in the same P-type shallow well region 132. It is provided to pass above. The second bit line 133 and the N ⁺ diffusion layer 13 immediately below it
4 are connected by a second bit line contact 115 at a pitch of 4F in the horizontal direction. First and second
The bit lines 112 and 113 of the
And are connected to the N ⁺ diffusion layer 134 via the contacts 114 and 115, respectively, as required, as described above.

According to the above structure, one memory cell is represented by a parallelogram 191 indicated by a chain double-dashed line in FIG. 7, and its area is 4F ² .

Next, the circuit configuration of the semiconductor memory device of this embodiment will be described with reference to FIG. This memory cell array is arranged in a so-called AND type. That is,
One first bit line and one second bit line form a pair, and n memory elements are connected in parallel between these bit lines. In FIG. 9, for example, the first bit line of the first bit line pair is shown as Ba1, and the second bit line of the first bit line pair is shown as Bb1. Further, the P-type shallow well region shared by the memory elements connected to the bit line pair is the third bit line. In FIG. 9, for example, the third bit line associated with the first bit line pair is Bw.
It is written as 1. Further, for example, the nth memory cell connected to the first bit line pair is represented as M1n. A selection transistor is provided in each bit line. In FIG. 9, for example, the first bit line selection transistor of the first bit line pair is represented as STBa1. In addition, n word lines run in the direction perpendicular to each bit line,
The gates of the memory cells are connected together. In FIG. 9, each word line is represented by W1 to Wn.

Next, an operation example of the semiconductor memory device of this embodiment will be described with reference to FIG. As an example, let us say that the low threshold state of the memory element is the write state, and the high threshold state of the memory cell is the erase state. Also, as an example, the first
It is assumed that the drain region is connected to the bit line and the source region is connected to the second bit line. In FIG. 9, when writing to the memory cell M12, a negative voltage (for example, −8 V) is applied to the word line W2, and the first bit line Ba1 and the third bit line Ba1 are applied.
A positive voltage (for example, 6V) is applied to the bit line Bw1, and the selection transistors STBa1 and STBw1 are turned on. At this time, the selection transistor STBb1 is turned off (the source region is open). By doing so, a high voltage is applied between the control gate of the memory cell M12 and the drain region and channel region, and electrons are extracted from the floating gate by FN (Fowler Nordheim) tunneling, and writing is performed.

On the other hand, erasing is performed by the memory cell M1 in FIG.
2 is erased, a positive voltage (for example, 10
V) is applied, and a negative voltage (for example, −) is applied to the second bit line Bb1.
8V) is applied to turn on the select transistor STBb1. At this time, the selection transistor STBa1 is turned off (the drain region is open). At this time, -8V is further applied to the third bit line Bw1 to turn on the selection transistor STBw1. Here, for example, the ground potential is applied to the other third bit line and the other second bit line to turn on the respective selection transistors. By doing so, a high voltage is applied only between the control gate and the source region and channel region of the memory cell M12, electrons are injected into the floating gate by FN tunneling, and the memory cell M12 is erased alone.

As is clear from the above description, the semiconductor memory device of the present embodiment is capable of writing and erasing bit by bit. The reason why writing and erasing can be performed for each bit is that it is possible to apply an independent potential to each bit line using the well region as a third bit line.

Further, in FIG. 9, when reading data from the memory cell M12, a positive voltage (for example, 3 V) is applied to the word line W2.
To apply a positive voltage (eg, 1 V) to the first bit line Ba1.
Is applied to turn on the selection transistor STBa1. At this time, the second bit line Bb1 is set to the ground potential, the selection transistor STBb1 is turned on, and the source of the memory cell M12 is set to the ground potential. By doing so, the data in the memory cell M12 can be read.

The voltage setting of each node in writing, erasing and reading is not limited to the above voltage.

The procedure for forming the semiconductor memory device of the second embodiment is similar to the procedure described in the first embodiment.

In the memory cell array which is the semiconductor memory device of the second embodiment, the well region isolated by the element isolation region functions as a bit line as in the memory cell array of the first embodiment. In this region, a region having a high concentration of impurities giving conductivity is formed. Therefore, since the delay of the bit line can be remarkably reduced, it is possible to prevent the speeding up of the write operation and the erase operation from being hindered. Further, the memory cell array, which is the semiconductor memory device of the second embodiment, can be highly integrated because the area of one memory cell is as small as 4F ² . Furthermore, the memory cell array, which is the semiconductor memory device of the second embodiment, is capable of writing and erasing bit by bit. Therefore, a semiconductor memory device capable of high-speed operation, high integration, and writing and erasing bit by bit is provided. (Third Embodiment) A semiconductor memory device according to the third embodiment is
In the semiconductor memory device according to the second embodiment, the first, second
The structure is simplified by using one of the bit lines as a common plate electrode.

FIG. 10 shows the third embodiment of the present invention.
It will be described below with reference to FIG.

10 to 12 are schematic views of a memory cell array which is the semiconductor memory device of the present embodiment. Figure 1
0 is a schematic view of a plane. 11 is a sectional view taken along the section line AA 'in FIG. 10, and FIG. 12 is a sectional view taken along the section line BB' in FIG.

First, the structure of the semiconductor memory device of the present embodiment will be described with reference to FIGS. 10 to 1
As can be seen from 2, the N-type deep well region 231 is formed on the semiconductor substrate 251. A P-type shallow well region 232 is formed on the N-type deep well region 231. Further, a plurality of element isolation regions 216 are formed so as to extend straight in the horizontal direction in FIG. 10 (in FIG. 10, each band-shaped region is shaded). The vertical pitch of the element isolation regions 216 is set to 2F (F is the minimum processing pitch). The P-type shallow well region 232 is separated by the element isolation region 216 and the insulating film 252 into a strip shape that extends straight in the horizontal direction in FIG. 10 to form a third bit line. The P-type shallow well region 232 preferably has a structure in which a P-type high impurity concentration region 232a is sandwiched between P-type low impurity concentration regions 232b and 232c. Further, it is preferable that a part of the P-type shallow well region 232 exists above the upper surface of the element isolation region 216.

A plurality of word lines 21 made of polysilicon
1 is formed so as to extend straight (crosswise to the direction in which the element isolation region 116 extends (vertical direction in FIG. 10, preferably vertical direction)). The horizontal pitch of the word lines 211 is set to 2F. Word line 21
The upper portion of the P-type shallow well region 232 covered with 1 serves as a channel region. The channel region and the word line 211 are separated by the insulating film 224 including the floating gate 221. The word line 211 plays the role of a control gate on this channel region.

As can be seen from the combination of FIGS. 10 to 12, an N ⁺ diffusion layer 234 is formed in the region above the P-type shallow well region 232 and other than the channel region. Each N ⁺ diffusion layer 234 functions as a source region or a drain region depending on the selection by the bit line when using this memory. At that time, the regions between the adjacent N ⁺ diffusion layers 234 become the channel regions, respectively.

A plurality of first bit lines 212 made of the first-layer metal are formed so as to intersect the word lines 211 (horizontal direction in FIG. 10) and extend straight. The vertical pitch of the first bit lines 212 is set to 2F and is provided so as to pass over the P-type shallow well region 232. The first bit line 212 and the N ⁺ diffusion layer 234 existing below the first bit line 212 have a pitch of 4F in the horizontal direction.
Therefore, they are connected by the first bit line contact 214. N ⁺ diffusion layer 234 connected to the first bit line 212
Is one of the source / drain regions. The plate electrode 217 made of a polysilicon film is connected to the N ⁺ diffusion layer 234 to which the first bit line contact 214 is not connected. The N ⁺ diffusion layer 234 connected to the plate electrode 217 becomes the other of the source / drain regions. A hole 218 is formed in the plate electrode 217 in the region where the first bit line contact 214 is present.

As described above, the semiconductor memory device according to the third embodiment is the same as the semiconductor memory device according to the second embodiment.
Since one of the second bit lines (the second bit line in the above example) is a common plate electrode, the element isolation region and the third bit line can be made linear. Therefore, the structure of the memory cell array can be simplified. According to the above configuration, one memory cell is represented by a rectangle 291 indicated by a chain double-dashed line in FIG. 12, and its area is 4F.
^{Is 2} .

The memory cell array may have the shape shown in FIGS. 13 to 15 (using the same part number as in FIGS. 10 to 12). In the case of the memory cell array shown in FIGS. 13 to 15, the plate electrodes 217 have a strip shape, and the strip plate electrodes 217 are arranged in parallel in the same direction as the word lines 211 at a pitch of 4F. The first bit line contacts 214 are connected to one of the source / drain regions in a region where the plate electrode 217 is not present (between the plate electrodes 217), and are linearly arranged at a pitch 2F in the extending direction of the word lines 211. I'm out.

Next, the circuit configuration of the semiconductor memory device of this embodiment will be described with reference to FIG. The circuit configuration of the memory cell array of the third embodiment differs from the circuit configuration of the memory cell array of the second embodiment in that the second bit line is a common plate electrode (denoted as Plt). . The selection transistor is omitted in FIG.

The procedure for forming the semiconductor memory device of the third embodiment is the same as that of the first embodiment except that the plate electrode is formed.
The procedure is the same as that described in.

Since the memory cell array of the third embodiment uses either one of the first and second bit lines in the memory cell array of the second embodiment as a common plate electrode, the structure of the memory cell array should be simplified. You can Therefore, in addition to the effect obtained by the memory cell array of the second embodiment, improvement in yield is achieved. (Embodiment 4) This embodiment is the same as the second or third embodiment.
The present invention relates to a semiconductor memory device using a film for trapping charges as a memory functional film in the semiconductor memory device of the above embodiment. The basic structure of the memory cell array in the semiconductor memory device of this embodiment is shown in FIGS.
1 and any of FIGS. 13 to 15. The circuit diagram thereof is the same as that of FIG. 9 or FIG. Therefore, description of the basic structure and circuit operation of the memory cell array is omitted.

FIG. 17 is a schematic sectional view of a memory element forming the memory cell M12 of FIG. 9 or 16.
51 is a semiconductor substrate, 31 is an N-type deep well region, 32
Is a deep P-type well region, 32a is a region having a high concentration of P-type impurities, 32b and 32c are regions having a low concentration of P-type impurities,
16 is an element isolation region, 34 is an N ⁺ diffusion layer, 11 is a control gate, W2 is a word line, Ba1 is a first bit line, and Bb1 is a second bit line (in FIG. 18, the plate electrode P).
lt) and Bw1 represent the third bit lines, respectively.

Channel of the P-type shallow well region 32
A memory function film is provided between the region and the control gate 11.
A charge trap film 58 that functions as is formed.
Here, the charge trap film is, for example, Si.₂N_Four/
SiO₂Film or SiO₂2 / Si ₂N_Four/ SiO₂Membrane (ONO
Membrane). As an element using this, for example,
For example, MNOS, SNOS, SONOS, etc. may be mentioned.
Here, the silicon nitride film is₂N_FourAnd silicon acid
SiO 2₂However, due to this, the composition of each element
The ratio is not limited. In addition, the charge trap film
Ferroelectric memory film having hysteresis characteristics instead of 58
May be used.

When a film that traps charges for holding charges is used, there is less leakage of stored charges than in the semiconductor memory devices of the second and third embodiments in which a conductor film is used as the floating gate. The problem is alleviated. Therefore, the reliability of the device can be improved. (Embodiment 5) This embodiment is the same as the second or third embodiment.
As the floating gates 121 and 221 in the semiconductor memory device according to the embodiment of the present invention, fine particles composed of a semiconductor or a conductor having a dimension of nanometer order
A semiconductor memory device using discrete dots).
The basic structure of the memory cell array in the semiconductor memory device according to the present embodiment is shown in FIGS.
Is the same as any one of FIG. The circuit diagram thereof is the same as that of FIG. 9 or FIG. Therefore, description of the basic structure and circuit operation of the memory cell array is omitted.

FIG. 18 is a schematic sectional view of a memory element forming the memory cell M12 of FIG. 9 or 16.
In the insulating film 57 that dissociates the channel region of the P-type well region 32 and the control gate 11, discrete dots 56 that function as floating gates are formed in a scattered manner. Here, as an example of the discrete dots 56, dots made of a conductor or a semiconductor discretely formed in the insulating film 57 can be cited. For example, it is a silicon dot or a metal dot formed in the silicon oxide film.

A procedure for manufacturing the semiconductor memory device according to this embodiment will be described. The manufacturing procedure of the semiconductor memory device in the present embodiment differs from the manufacturing procedure in the second embodiment only in the procedure of forming the floating gate. The discrete-dot-shaped floating gate is formed, for example, on the oxide film formed on the channel region by LPCV.
Silicon microcrystals may be formed by the D method, and then an oxide film may be formed by the CVD method.

The discrete dots 56 may be regularly arranged or may be randomly arranged. Further, they may be arranged three-dimensionally as shown in FIG. Further, as shown in FIG. 20, the floating gate may be composed of a conductor film 59 and discrete dots 56. FIG. 21 shows the CV measurement of the memory function film of the memory device shown in FIG. In the figure, Vg represents the voltage applied to the control gate 11 with respect to the P-type well region 32, and C represents the capacitance per unit gate area. For example, when the applied voltage Vg was scanned from + 3V to -3V and then from -3V to + 3V, a clear hysteresis characteristic was obtained. This indicates that the memory element shown in FIG. 21 is capable of memory operation.

As described above, according to the semiconductor memory device of the present embodiment, since the discrete dots 56 are used as the floating gate, the semiconductors of the second and third embodiments using the conductor film as the floating gate. The problem of leakage of stored charges is reduced as compared to the storage device. Therefore, the reliability of the device can be improved. Further, when the quantum dot memory function film, which is one form of the memory function film using the discrete dots 56, is used, since the tunneling can be directly used for the writing and erasing, deterioration of the element is suppressed by the low voltage operation. , Reliability can be improved. Furthermore, when the direct tunneling is used for the writing and erasing, the time required for the writing and erasing can be significantly reduced in the memory device alone, but at this time, the delay time of the bit line formed of the well region is shortened. The effect of doing is even more important. Therefore, according to the semiconductor memory device of the present embodiment, it is possible to take full advantage of the short delay time of the bit line formed of the well region.

[0088]

As is apparent from the above, according to the semiconductor memory device of the first invention, the second conductivity type electrically isolated from each other by the element isolation region and the deep well region of the first conductivity type. In the shallow well region of the mold, a second
A region containing a high concentration of impurities imparting a conductivity type is formed. Therefore, the resistance of the second conductivity type shallow well region can be significantly reduced. Therefore, in the memory cell array in which the second-conductivity-type shallow well region is used as a bit line, the delay of the bit line formed of the second-conductivity-type shallow well region can be significantly reduced, and the write operation and the erase operation can be performed. It is possible to prevent the speeding up of the operation from being hindered. Therefore, a semiconductor memory device that can operate at high speed is provided.

According to one embodiment, the resistance of the shallow well region of the second conductivity type can be made sufficiently small, and the desired threshold value can be easily obtained by appropriately maintaining the impurity concentration of the channel region. The junction capacitance between the shallow well region of the second conductivity type and the source / drain region of the memory element can be suppressed small. In addition, the junction capacitance between the second-conductivity-type shallow well region and the first-conductivity-type deep well region can be suppressed to a small value. Therefore, the second
It is possible to further reduce the delay of the bit line formed of the conductive type shallow well region and suppress the power consumption.

Further, according to the semiconductor memory device of the second invention, the second element electrically isolated from each other by the element isolation region and the deep well region of the first conductivity type.
A metal layer or a silicide layer is formed in the conductivity-type shallow well region. Therefore, the resistance of the second conductivity type shallow well region can be significantly reduced. Therefore, in the memory cell array in which the second-conductivity-type shallow well region is used as a bit line, the delay of the bit line formed of the second-conductivity-type shallow well region can be significantly reduced, and the write operation and the erase operation can be performed. It is possible to prevent the speeding up of the operation from being hindered. Therefore, a semiconductor memory device that can operate at high speed is provided.

According to one embodiment, the depth of the lower surface of the shallow well region of the second conductivity type is made shallow without changing the overall thickness of the shallow well region of the second conductivity type. You can As a result, the element isolation region can be made shallow. If the element isolation region can be made shallow, the step of filling the insulating film when forming the element isolation region becomes easy. Therefore, it becomes possible to more easily form a semiconductor memory device in which the bit line formed of the second conductivity type shallow well region has a small delay.

According to the method for forming a semiconductor memory device of the third invention, the single crystal semiconductor film is selectively epitaxially grown after the element isolation region and the high concentration impurity layer are formed. A low resistance layer is formed inside the second-conductivity-type shallow well region that functions as a line, while a sufficient amount of impurities (impurity or metal atom that imparts conductivity) is formed in the upper layer portion of the second-conductivity-type shallow well region. ) A region having a low concentration and few crystal defects can be formed. Therefore, the junction capacitance between the shallow well region of the second conductivity type and the source / drain region of the memory element is reduced, the threshold value of the memory element can be easily adjusted, or a memory element having a small leak current and good characteristics is manufactured. It becomes possible.

Further, according to one embodiment, since the area of one memory cell is as small as 4F ² (F is the minimum processing pitch), high integration is possible. Furthermore, according to the above embodiment, writing and erasing can be performed bit by bit. Therefore, high-speed operation, high integration, and 1
Provided is a semiconductor memory device capable of writing and erasing bit by bit.

Further, according to one embodiment,
Since one of the second bit lines is the common plate electrode, the structure of the memory cell array can be simplified. Therefore, an improvement in yield is achieved.

Further, according to one embodiment, the memory functional film is a laminated film of a silicon nitride film and a silicon oxide film, and has a function of trapping charges. for that reason,
The problem of leakage of stored charges is reduced as compared with the case where the conductor film is a floating gate. Therefore, the reliability of the device can be improved.

Further, according to one embodiment, since the memory functional film is an insulating film containing fine particles of a semiconductor or a conductor in a scattered state, the memory functional film is stored as compared with the case where the conductor film is a floating gate. The problem of charge leakage is reduced. Therefore, the reliability of the device is improved.

Further, according to one embodiment, since a composite of a film made of a semiconductor or a conductor and fine particles made of a semiconductor or a conductor is used as the memory function film, the shallow well of the second conductivity type is used. Writing is performed when the voltage applied to the word line for the region is, for example, ± 3V.
Therefore, writing and erasing can be performed with a low voltage.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor memory device according to a first embodiment of the present invention taken along a memory transistor word line.

FIG. 2 is a sectional view of the semiconductor memory device according to the first embodiment of the present invention when cut in the bit line direction.

FIG. 3 is a circuit diagram of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a procedure of forming the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a schematic plan view of a semiconductor memory device according to a second embodiment of the present invention.

6 is a cross-sectional view taken along the section line AA ′ of FIG.

FIG. 7 is a cross-sectional view taken along the section line BB ′ of FIG.

FIG. 8 is a cross-sectional view taken along the section line CC ′ of FIG.

FIG. 9 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a schematic plan view of a semiconductor memory device according to a third embodiment of the present invention.

11 is a cross-sectional view taken along the section line AA ′ of FIG.

12 is a cross-sectional view taken along the section line BB ′ of FIG.

FIG. 13 is a schematic plan view of a modification of the semiconductor memory device according to the third embodiment of the present invention.

FIG. 14 is a cross-sectional view taken along section line AA ′ of FIG.

FIG. 15 is a cross-sectional view taken along the section line BB ′ of FIG.

FIG. 16 is a circuit diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 17 is a schematic cross-sectional view of a memory element forming a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 18 is a schematic cross-sectional view of a memory element forming a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 19 is a schematic cross-sectional view of a first modification of the memory element forming the semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 20 is a schematic cross-sectional view of a second modification of the memory element forming the semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 21 is a CV characteristic of a second modified memory film of the memory element forming the semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 22 is a circuit diagram of a conventional semiconductor memory device.

FIG. 23 is a cross-sectional view of a conventional semiconductor memory device taken along a memory transistor word line.

FIG. 24 is a cross-sectional view of a conventional semiconductor memory device taken along the bit line direction.

[Explanation of symbols]

111 ... Word line 112 ... First bit line 113 ... Second bit line 116, 316 ... Element isolation region 131, 331 ... N type deep well region 132, 332 ... P type shallow well region 132a, 332a ... P type Regions 132b, 132c, 332a, 332c having a high impurity concentration ... Regions 134 having a low P-type impurity concentration ... N ⁺ diffusion layers 151, 351 ... Semiconductor substrate

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F083 EP03 EP18 EP32 EP79 ER06                       ER09 ER15 ER19 ER21 ER29                       GA02 GA03 GA05 JA35 KA07                       KA08 NA01 PR25 PR36 ZA28                 5F101 BA05 BA07 BA12 BA45 BA46                       BA52 BA54 BB05 BC02 BD02                       BD22 BD31 BD34 BD35 BD36                       BE02 BE05 BE07 BF08 BH09                       BH11

Claims (10)

[Claims] 1. A deep well of the first conductivity type on a semiconductor substrate.
A region and a plurality of first regions on the deep well region of the first conductivity type.
The second conductivity type shallow well region is formed, and the first conductivity type is formed.
Deep well region and multiple second conductivity type shallow wells
A memo with multiple memory cells arranged in a matrix on the area
A semiconductor memory device having a re-cell array, The plurality of second conductivity type shallow well regions are element isolation regions.
And the deep well region of the first conductivity type
Electrically separated, The second conductivity type is provided in the shallow well region of the second conductivity type.
1 x 10 impurities ²⁰cm^-3Impurity that exists at the above concentration
Semiconductor memory device characterized in that a physical layer is formed
Place 2. The semiconductor memory device according to claim 1, wherein the second-conductivity-type shallow well region is located above or below a region having a high impurity concentration that imparts the second-conductivity type. A semiconductor memory device having a structure in which there is a region having a low impurity concentration that gives 3. A first-conductivity-type deep well region is formed on a semiconductor substrate, and a plurality of second-conductivity-type shallow well regions are formed on the first-conductivity-type deep well region. Storage device having a memory cell array in which a plurality of memory cells are arranged in a matrix on a deep well region of a second type and a plurality of shallow well regions of a second conductivity type. The well region is electrically isolated from each other by the element isolation region and the deep well region of the first conductivity type, and a metal layer or a silicide layer is formed in the shallow well region of the second conductivity type. And semiconductor memory device. 4. The semiconductor memory device according to claim 1, wherein a part of the second-conductivity-type shallow well region is located above an upper surface of the element isolation region. A characteristic semiconductor memory device. 5. A first-conductivity-type deep well region is formed on a semiconductor substrate, and a plurality of second-conductivity-type shallow well regions are formed on the first-conductivity-type deep well region. Type deep well regions and a plurality of second-conductivity-type shallow well regions having a memory cell array in which a plurality of memory cells are arranged in rows and columns, and the plurality of second-conductivity-type shallow well regions are isolated from each other. And a deep well region of the first conductivity type are electrically separated from each other, and a high-concentration impurity layer containing a high concentration of impurities imparting the second conductivity type is formed in the shallow well region of the second conductivity type. A method for forming a semiconductor memory device, comprising: forming a device isolation region and a high-concentration impurity layer on a semiconductor substrate; Method of forming a semiconductor memory device and performing the step of Le grown. 6. The semiconductor memory device according to claim 1, wherein the element isolation regions that meander and extend in the first direction are arranged in a second direction intersecting the first direction. Formed by
The well regions that meander and extend in the first direction are defined between the adjacent element isolation regions, and the impurity diffusions functioning as the source region and the drain region are formed at the respective turning points of the meander in each of the well regions. A region is formed, a channel region is defined between the impurity diffusion regions adjacent to each other in the same well region, and a plurality of word lines extending in the second direction are respectively interposed via a film having a memory function. A first bit line provided so as to pass over a channel region in each well region and extending in the first direction is provided on the impurity diffusion region provided at a folding point on one side of the meandering in the same well region. And a second bit line extending in the first direction is provided at a folding point on the other side of the meander in the same well region. The first bit line and the second bit line are provided so as to pass over the impurity diffused region thus formed, and are respectively connected to the impurity diffused region located below through the contact hole. Semiconductor memory device. 7. The semiconductor memory device according to claim 1, wherein the element isolation regions extending in the first direction are formed side by side in a second direction intersecting the first direction. The well regions extending in the first direction are defined between the adjacent element isolation regions, and the word lines extending in the second direction are formed side by side in the first direction. In addition, impurity diffusion regions functioning as a source region or a drain region are formed in the well regions located between the word lines, and channels are formed between the impurity diffusion regions adjacent in the same well region. A region is defined, the word line is arranged on each channel region through a memory film having a memory function, and a plurality of bit lines extending in the first direction are formed on the respective channel regions. Is formed above the well region and is connected to every other impurity diffusion region in each well region located therebelow via a contact hole, and a plate electrode is formed below the bit line. In addition, the bit line is connected to an impurity diffusion region which is not connected, and the contact hole is provided so as to pass through a hole or a slit provided in the plate electrode. Storage device. 8. The semiconductor memory device according to claim 6 or 7, wherein the memory functional film is a laminated film of a silicon nitride film and a silicon oxide film. 9. The semiconductor memory device according to claim 6 or 7, wherein the memory function film is an insulating film containing fine particles of a semiconductor or a conductor in a scattered manner. 10. The semiconductor memory device according to claim 6 or 7, wherein the memory functional film is an insulating film containing a film made of a semiconductor or a conductor and fine particles made of a semiconductor or a conductor. Storage device.