JPH06216291A - Solder plating method for armour of semiconductor leadframe - Google Patents

Abstract

PURPOSE:To simultaneously subject a number of leadframes to a plating treatment by arranging strip-shaped leadframes, which serve as a negative electrode and are to be positioned between positive electrodes which are opposite to each other, in such a way that the surfaces of the strip-shaped leadframes are orthogonal to the surfaces of the positive electrodes. CONSTITUTION:A pair of positive electrodes 2 are disposed opposite to each other within a plating bath 1, and a leadframe support 3 serving as a negative electrode is disposed between a pair of brackets 4 which stand upright along the upper edges of the plating bath 1 in such a way that the leadframe support 3 is located along the center plane between these positive electrodes 2. A number of leadframes 5 are suspended below the support 3 at given intervals D in such a way that the leadframes are arranged orthogonal to the positive electrodes 2. Thereby, a number of leadframes 5 can be simultaneously subjected to a plating treatment in the small plating bath 1, and hence installation space of the plating bath 1 can be saved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external solder plating method for semiconductor lead frames.

[0002]

2. Description of the Related Art In a conventional method for external solder plating of a semiconductor lead frame, as shown in FIG. 2, both sides of a lead frame 5 are plated in a plating tank (not shown) in order to have a uniform film thickness. On the center surface of the facing positive electrode 2,
The lead frames 5 were arranged at a predetermined pitch P parallel to the surface of the positive electrode 2.

[0003]

However, in the conventional arrangement of lead frames, the length of the plating tank becomes long in order to plate many lead frames 5 at the same time. Further, when the lead frames 5 are arranged on the same plane in the vertical direction at the central portions of the positive electrodes 2 and 2, the width of the plating tank becomes large.

As another conventional technique, for example, Japanese Patent Application Laid-Open No. 3-27796 discloses a method and apparatus for plating the entire surface of a short plate-shaped object to be plated. No description is made regarding the relative positional relationship between the positive electrode and the surface of the positive electrode. Therefore, it was not possible to solve the above-mentioned problems of the conventional technology.

The present invention has been proposed in view of the above problems, and provides an external solder plating method for a semiconductor lead frame capable of simultaneously plating a larger number of lead frames in a conventional plating tank. It is an object.

[0006]

According to the method of the present invention, the surface of a strip-shaped lead frame, which is a negative electrode and is placed between opposing positive electrodes, is orthogonal to the surface of the positive electrode.

[0007]

In the present invention, the surface of the lead frame is orthogonal to the surface of the positive electrode and the lead frames are arranged in parallel at a predetermined interval, so that a large number of lead frames can be plated at the same time in a small plating tank.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a plating tank 1 for carrying out the present invention. Inside the plating tank 1, a pair of positive electrodes 2 are provided so as to face each other, and on the center faces of the positive electrodes 2 and 2,
A lead frame supporting member 3, which is a negative electrode, is provided between a pair of brackets 4 standing on the upper edge of the tank 1. A plurality of lead frames 5 are provided below the support tool 3.
Are orthogonal to the positive electrode 2 and are suspended at a predetermined interval D. In the figure, reference numeral 6 is a shield plate having small holes at required positions for adjusting the current distribution, and 7 stabilizes the flow of the plating solution in the tank 1 from the lower side to the upper side, so that each lead frame 5 has This is a discharge pipe that is subjected to uniform plating treatment on the entire surface.

It is obvious that the predetermined spacing D of the lead frame 5 can be made much smaller than the predetermined pitch P in FIG. Therefore, in the same plating tank 1,
A larger number of lead frames 5 than the conventional one can be plated at the same time. That is, many lead frames 5 can be plated at the same time in a small plating tank.

[0011]

As described above, according to the present invention, a large number of lead frames can be plated at the same time in a small plating tank to improve the productivity and save the installation space of the plating tank.

[Brief description of drawings]

FIG. 1 is a perspective view showing an example of a plating tank for carrying out the present invention.

FIG. 2 is a top view illustrating an arrangement of lead frames for a conventional positive electrode.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Plating tank 2 ... Positive electrode 3 ... Lead frame support tool 4 ... Bracket 5 ... Lead frame 6 ... Shielding plate 7 ... Discharge pipe

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiko Hara 11-11 Haneda-Asahicho, Ota-ku, Tokyo Inside EBARA CORPORATION

Claims (1)

[Claims] 1. A method for external solder plating of a semiconductor lead frame, wherein a surface of a strip-shaped lead frame, which is a negative electrode placed between opposing positive electrodes, is orthogonal to a surface of the positive electrode.