JPH06216234A - Method of forming impurity diffusion region for isolation - Google Patents

Method of forming impurity diffusion region for isolation

Info

Publication number
JPH06216234A
JPH06216234A JP797093A JP797093A JPH06216234A JP H06216234 A JPH06216234 A JP H06216234A JP 797093 A JP797093 A JP 797093A JP 797093 A JP797093 A JP 797093A JP H06216234 A JPH06216234 A JP H06216234A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
region
impurity diffusion
impurities
diffusion region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP797093A
Other languages
Japanese (ja)
Inventor
Nobuyuki Takakura
信之 高倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP797093A priority Critical patent/JPH06216234A/en
Publication of JPH06216234A publication Critical patent/JPH06216234A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To make it possible to provide isolation between a predetermined element forming region and other regions of the outside of the element forming region at a low cost without using an epitaxial semiconductor substrate and remarkably reducing the element forming region. CONSTITUTION:When an impurity diffusion region 8 for isolation between a predetermined element forming region A of a semiconductor substrate 1 and other regions B of the outside of the element forming region A is formed, the semiconductor substrate 1 in which a groove 5 is previously formed in the rear of the element forming region A is used as the semiconductor substrate, and conductive type impurity is diffused so as to extend across the front surface of the semiconductor substrate 1 and the bottom of the groove 5, and thus the impurity diffusion region 8 for isolation is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、接合分離用の不純物
拡散領域の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an impurity diffusion region for junction separation.

【0002】[0002]

【従来の技術】従来よりバイポーラトランジスタの場合
には所定の素子形成領域とその外側の他の領域の間を電
気的に分離することが必要である。この分離には、素子
形成領域とその外側の他の領域の間に反対導電型の不純
物を厚み方向に拡散させることにより素子形成領域と他
の領域とを接合分離する不純物拡散領域を形成するいわ
ゆる接合分離法が用いられる。
2. Description of the Related Art Conventionally, in the case of a bipolar transistor, it is necessary to electrically isolate a predetermined element formation region and another region outside thereof. For this separation, what is called an impurity diffusion region is formed between the element formation region and another region outside the element formation region by diffusing impurities of opposite conductivity type in the thickness direction to form a junction separation between the element formation region and the other region. A junction separation method is used.

【0003】さらに、近年はバイポーラ素子とCMOS
を混搭したBiCMOSトランジスタや、制御回路とパ
ワー素子を1チップ化したスマートパワーICなど異種
の素子を混搭することが多くなり、このような場合も、
接合分離法が適用されている。しかしながら、接合分離
法を適用する場合、従来、半導体基板として、図9にみ
るように、p型シリコン基板51の上にn型シリコン層
52をエピタキシャル法で堆積させてなるエピタキシャ
ル半導体基板を使う必要がある。この場合、エピタキシ
ャル法による堆積前にp型シリコン基板51の表面に埋
め込み層用のp型不純物を予備導入しておいて、堆積後
のn型シリコン層52の表面からp型不純物を導入し、
予備導入したp型不純物のn型シリコン層52への拡散
も利用し、p型不純物の横方向への拡散をなるべく抑え
て素子形成領域の減少が少なくてすむように、接合分離
用のp+ 型不純物拡散領域53を形成する。
Furthermore, in recent years, bipolar devices and CMOS
In many cases, heterogeneous elements such as a BiCMOS transistor in which a control circuit and a smart power IC in which a control circuit and a power element are integrated into one chip are mixed.
The junction separation method is applied. However, when the junction isolation method is applied, conventionally, as shown in FIG. 9, it is necessary to use an epitaxial semiconductor substrate formed by depositing an n-type silicon layer 52 on a p-type silicon substrate 51 by an epitaxial method as shown in FIG. There is. In this case, p-type impurities for the buried layer are preliminarily introduced into the surface of the p-type silicon substrate 51 before the deposition by the epitaxial method, and the p-type impurities are introduced from the surface of the n-type silicon layer 52 after the deposition.
The diffusion of the pre-introduced p-type impurity into the n-type silicon layer 52 is also used to suppress the lateral diffusion of the p-type impurity as much as possible to reduce the decrease in the element formation region, so that the p + -type for junction separation is formed. The impurity diffusion region 53 is formed.

【0004】しかしながら、従来の接合分離用の不純物
拡散領域の形成方法は、使用するエピタキシャル半導体
基板がもともと高価である上に埋め込み層用不純物の予
備導入も必要であり、非常にコストの高いものになって
しまうという問題がある。勿論、エピタキシャル半導体
基板を使わずに、全体が同じ導電型の半導体基板に反対
導電型の不純物を基板表面から裏面に達するように拡散
して接合分離を行うことが考えられるが、この場合に
は、反対導電型の不純物の必要拡散距離が長過ぎて実現
は無理である。
However, in the conventional method for forming the impurity diffusion region for junction separation, the epitaxial semiconductor substrate to be used is originally expensive and it is necessary to preliminarily introduce the impurities for the buried layer, which makes the cost very high. There is a problem of becoming. Of course, without using an epitaxial semiconductor substrate, it is conceivable to diffuse impurities of opposite conductivity type into a semiconductor substrate of the same conductivity type so as to reach from the substrate surface to the back surface, and perform junction separation. However, the required diffusion distance of impurities of opposite conductivity type is too long to be realized.

【0005】[0005]

【発明が解決しようとする課題】この発明は、上記事情
に鑑み、エピタキシャル半導体基板を使わずに済むとと
もに、素子形成領域の大幅な減少を伴わずに、所定の素
子形成領域とその外側の他の領域の間を低コストで接合
分離することが出来る方法を提供することを課題とす
る。
In view of the above circumstances, the present invention eliminates the need for using an epitaxial semiconductor substrate and, at the same time, provides a predetermined element formation region and other parts outside it without significantly reducing the element formation region. It is an object of the present invention to provide a method capable of performing junction separation at low cost between regions.

【0006】[0006]

【課題を解決するための手段】前記課題を解決するた
め、この発明の接合分離用の不純物拡散領域の形成方法
では、半導体基板の所定の素子形成領域とその外側の他
の領域の間に反対導電型の不純物を基板の厚み方向に拡
散させることにより前記素子形成領域と他の領域とを接
合分離する不純物拡散領域を形成する方法において、前
記半導体基板として、前記素子形成領域の裏側に溝が予
め形成されている半導体基板を用い、前記反対導電型の
不純物を前記半導体基板の表側の表面と前記溝の底面の
間に渡るように拡散させることにより接合分離用の不純
物拡散領域を形成することを特徴とする。
In order to solve the above-mentioned problems, in the method of forming an impurity diffusion region for junction isolation of the present invention, a predetermined element forming region of a semiconductor substrate and another region outside thereof are provided with an opposite structure. In a method of forming an impurity diffusion region that joins and separates the element formation region and another region by diffusing conductivity type impurities in the thickness direction of the substrate, the semiconductor substrate has a groove on the back side of the element formation region. Forming an impurity diffusion region for junction separation by diffusing the impurity of the opposite conductivity type so as to extend between the front surface of the semiconductor substrate and the bottom surface of the groove using a preformed semiconductor substrate. Is characterized by.

【0007】この発明の場合、接合分離用の反対導電型
の不純物の拡散を半導体基板の表側の表面と前記溝の底
面の両方より両不純物の拡散領域が繋がるように行う形
態が、素子形成領域の減少を抑える効果が大きく好まし
い形態であるということが出来るが、この発明の場合、
半導体基板の表側の表面と前記溝の底面のいずれか一方
の側だけからが反対導電型の不純物の拡散を行うように
してもよい。
In the case of the present invention, the diffusion of impurities of opposite conductivity type for junction separation is performed so that the diffusion regions of both impurities are connected from both the front surface of the semiconductor substrate and the bottom surface of the groove. It can be said that this is a preferable mode because it has a large effect of suppressing the decrease of
Impurities of opposite conductivity type may be diffused only from one of the front surface of the semiconductor substrate and the bottom surface of the groove.

【0008】[0008]

【作用】この発明にかかる方法では、反対導電型の不純
物を半導体基板の表側の表面と前記溝の底面の間に渡る
ように拡散させるため、溝の深さ分だけ厚み方向の拡散
距離が短く、半導体基板として導電型の異なる半導体層
が積層された高価なエピタキシャル半導体基板を使わず
とも、全体が同じ導電型の半導体基板でもって、必要な
素子形成領域の減少を抑えつつ、接合分離用の不純物拡
散領域の形成が行える。
In the method according to the present invention, since the impurities of opposite conductivity type are diffused so as to extend between the front surface of the semiconductor substrate and the bottom surface of the groove, the diffusion distance in the thickness direction is shortened by the depth of the groove. Even if an expensive epitaxial semiconductor substrate in which semiconductor layers having different conductivity types are stacked is not used as a semiconductor substrate, a semiconductor substrate having the same conductivity type as a whole can be used for separating a junction while suppressing a reduction in a necessary element formation region. Impurity diffusion regions can be formed.

【0009】加えて、この発明の方法において、接合分
離用の反対導電型の不純物の拡散を半導体基板の表側の
表面と前記溝の底面の両方から行う場合、一方の側のみ
から不純物を拡散する場合に比べ半分ですみ、反対導電
型の不純物の横方向の拡散がより短くなるため、素子形
成領域の減少を抑える効果が大きい。また、埋め込み層
用の不純物を予備導入する方式をとる従来の場合は、不
純物拡散領域の不純物濃度の制限が比較的厳しいのであ
るが、この発明の場合、通常の不純物拡散方式をとるた
め、不純物拡散領域の不純物濃度の制限が緩和されると
いう利点もある。
In addition, in the method of the present invention, when the impurities of opposite conductivity type for junction separation are diffused from both the front surface of the semiconductor substrate and the bottom surface of the groove, the impurities are diffused from only one side. It is only half that in the case, and the lateral diffusion of impurities of the opposite conductivity type becomes shorter, so the effect of suppressing the reduction of the element formation region is great. Further, in the conventional case of adopting the method of preliminarily introducing the impurities for the buried layer, the limitation of the impurity concentration of the impurity diffusion region is relatively strict, but in the case of the present invention, since the normal impurity diffusion method is adopted, There is also an advantage that the restriction on the impurity concentration in the diffusion region is relaxed.

【0010】[0010]

【実施例】以下、この発明の実施例を、図面を参照しな
がら説明する。この発明は、下記の実施例に限らないこ
とは言うまでもない。図2にみるように、n型シリコン
のみからなる半導体基板1の両面に熱酸化により厚み5
000Åの熱酸化膜2,3を形成する。なお、図2〜図
7では基板の裏側を上にして図示している。
Embodiments of the present invention will be described below with reference to the drawings. It goes without saying that the present invention is not limited to the following embodiments. As shown in FIG. 2, both sides of the semiconductor substrate 1 made of only n-type silicon were thermally oxidized to a thickness of 5
000 Å thermal oxide films 2 and 3 are formed. 2 to 7, the back side of the substrate is shown as an upper side.

【0011】熱酸化膜2,3の形成に続いて、図3にみ
るように、フォトリソグラフィ工程とRIE工程により
半導体基板1における素子形成領域の上の熱酸化膜2を
部分的に除去して窓2aを開け、残った熱酸化膜2をマ
スクにして異方性エッチングを施す。例えば80℃程度
のKOH水溶液に浸漬することで異方性エッチングを行
えば、窓2aのところには縁が54.5°の角度で傾斜
している溝5が素子形成領域の裏側に出来ることにな
る。この溝5は、接合分離用の反対導電型の不純物を導
入を行う部分にかかるように形成する。
After the thermal oxide films 2 and 3 are formed, as shown in FIG. 3, the thermal oxide film 2 on the element formation region of the semiconductor substrate 1 is partially removed by a photolithography process and an RIE process. The window 2a is opened and anisotropic etching is performed using the remaining thermal oxide film 2 as a mask. For example, if anisotropic etching is performed by immersing in a KOH aqueous solution at about 80 ° C., a groove 5 having an edge inclined at an angle of 54.5 ° can be formed at the window 2a on the back side of the element formation region. become. The groove 5 is formed so as to cover the portion where impurities of opposite conductivity type for junction separation are introduced.

【0012】溝を形成した後、図4にみるように、再び
熱酸化により半導体基板1の裏側の表面を溝5の内面も
含めて熱酸化膜6で全面的に覆ってから、図5にみるよ
うに、溝5の底の熱酸化膜6における素子形成領域とそ
の外側の他の領域の間の位置に沿って窓6aを開ける。
窓6aを形成した後、図6にみるように、p型不純物で
あるボロンをエネルギー:50keV、注入量:5E1
5でイオン注入してから、図7にみるように、熱処理し
窓6aに酸化膜を形成するとともにボロンを予備拡散さ
せるとp型拡散領域11が出来る。
After forming the groove, as shown in FIG. 4, the surface on the back side of the semiconductor substrate 1 is entirely covered with the thermal oxide film 6 including the inner surface of the groove 5 by thermal oxidation again. As can be seen, the window 6a is opened along the position between the element formation region in the thermal oxide film 6 at the bottom of the groove 5 and the other region outside thereof.
After forming the window 6a, as shown in FIG. 6, boron, which is a p-type impurity, has an energy of 50 keV and an implantation amount of 5E1.
As shown in FIG. 7, the p-type diffusion region 11 is formed by ion-implanting the ions in step 5 and then performing a heat treatment to form an oxide film in the window 6a and pre-diffuse boron.

【0013】次に、図8にみるように、半導体基板1の
表側の熱酸化膜3における素子形成領域とその外側の他
の領域の間の位置に沿って窓3aを開け、p型不純物で
あるボロンをエネルギー:50keV、注入量:5E1
5でイオン注入する。この場合、窓3aは先の図5に示
す窓6aと対向する位置に開いており、p型不純物であ
るボロンはp型拡散領域11に対面した位置に注入され
ることになる。
Next, as shown in FIG. 8, a window 3a is opened along the position between the element forming region of the front thermal oxide film 3 of the semiconductor substrate 1 and the other region outside the region, and a p-type impurity is used. Energy of certain boron: 50 keV, injection amount: 5E1
Ion implantation is performed at 5. In this case, the window 3a is opened at a position facing the window 6a shown in FIG. 5, and boron, which is a p-type impurity, is implanted at a position facing the p-type diffusion region 11.

【0014】ボロンのイオン注入の後、半導体基板1を
拡散処理炉に入れ、表側と裏側の両方から注入されたボ
ロンによる拡散領域が接続するように拡散処理を行う。
この結果、図1にみるように、半導体基板1における素
子形成領域とその外側の領域の間の位置には半導体基板
1の表側から裏側に渡るp型不純物拡散領域8が形成さ
れ、p型不純物拡散領域8の内側の素子形成領域Aとそ
の外側の他の領域Bがpn接合で電気的に分離された状
態となる。つまり、p型不純物拡散領域8が接合分離用
の不純物拡散領域となっているのである。
After the boron ion implantation, the semiconductor substrate 1 is placed in a diffusion treatment furnace, and a diffusion treatment is performed so that the diffusion regions made of boron implanted from both the front side and the back side are connected.
As a result, as shown in FIG. 1, a p-type impurity diffusion region 8 extending from the front side to the back side of the semiconductor substrate 1 is formed at a position between the element formation region and the region outside the semiconductor substrate 1, and the p-type impurity diffusion region 8 is formed. The element forming region A inside the diffusion region 8 and the other region B outside thereof are in a state of being electrically separated by the pn junction. That is, the p-type impurity diffusion region 8 is an impurity diffusion region for junction isolation.

【0015】このように、実施例の場合、接合分離のた
めのp型不純物の拡散が表側と溝の底面の両方から行わ
れる上に溝5の深さ分は拡散が省略されることになるた
め、基板厚み方向の拡散距離が短くなり、その結果、p
型不純物拡散領域8は(基板の)横方向に余り広がら
ず、素子形成領域がp型不純物拡散領域8の形成で狭く
なり過ぎるということもない。このように、エピタキシ
ャル半導体基板を使わず、しかも、素子形成領域の大幅
な減少も伴わずに、所定の素子形成領域を接合分離する
ことが出来るのである。
As described above, in the case of the embodiment, p-type impurities for junction separation are diffused from both the front side and the bottom of the groove, and the diffusion is omitted for the depth of the groove 5. Therefore, the diffusion distance in the substrate thickness direction becomes short, and as a result, p
The type impurity diffusion region 8 does not extend so much in the lateral direction (of the substrate), and the element formation region does not become too narrow due to the formation of the p type impurity diffusion region 8. As described above, the predetermined element formation region can be junction-separated without using the epitaxial semiconductor substrate and without significantly reducing the element formation region.

【0016】[0016]

【発明の効果】この発明の接合分離用の不純物拡散領域
の形成方法の場合、基板厚み方向の反対導電型不純物の
拡散距離が溝の深さ分だけ短くなるため、高価なエピタ
キシャル半導体基板を使わずとも、全体が同じ導電型の
安価な半導体基板でもって、必要な素子形成領域の減少
を抑えつつ、接合分離用の不純物拡散領域の形成が行え
る。
According to the method of forming the impurity diffusion region for junction separation of the present invention, an expensive epitaxial semiconductor substrate is used because the diffusion distance of impurities of opposite conductivity type in the substrate thickness direction is shortened by the depth of the groove. Even if an inexpensive semiconductor substrate having the same conductivity type is used as a whole, an impurity diffusion region for junction separation can be formed while suppressing a reduction in a necessary element formation region.

【0017】加えて、この発明の方法において、接合分
離用の反対導電型不純物の拡散を半導体基板の表側の表
面と前記溝の底面の両方から行う場合、一方の側のみか
ら不純物を拡散する場合に比べ半分ですみ、反対導電型
の不純物の横方向の拡散がより短くなるため、素子形成
領域の減少抑制効果が大きい。
In addition, in the method of the present invention, when the opposite conductivity type impurities for junction separation are diffused from both the front surface of the semiconductor substrate and the bottom surface of the groove, the impurities are diffused from only one side. It is only half as compared with, and the lateral diffusion of impurities of opposite conductivity type becomes shorter, so that the effect of suppressing the reduction of the element formation region is great.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例での接合分離済の半導体基板の説明図。FIG. 1 is an explanatory diagram of a semiconductor substrate that has undergone junction separation in an example.

【図2】実施例での熱酸化膜形成工程の説明図。FIG. 2 is an explanatory diagram of a thermal oxide film forming step in the example.

【図3】実施例での溝形成工程の説明図。FIG. 3 is an explanatory diagram of a groove forming step in the example.

【図4】実施例での熱酸化膜形成工程の説明図。FIG. 4 is an explanatory diagram of a thermal oxide film forming step in the example.

【図5】実施例での基板裏側の熱酸化膜への窓開け工程
の説明図。
FIG. 5 is an explanatory diagram of a window opening process in the thermal oxide film on the back side of the substrate in the example.

【図6】実施例での基板裏側へのイオン注入工程の説明
図。
FIG. 6 is an explanatory diagram of an ion implantation step on the back side of the substrate in the example.

【図7】実施例での注入不純物の予備拡散工程の説明
図。
FIG. 7 is an explanatory diagram of a pre-diffusion process of implanted impurities in the example.

【図8】実施例での基板表側への窓開け・イオン注入工
程の説明図。
FIG. 8 is an explanatory diagram of a window opening / ion implantation process on the front side of the substrate in the example.

【図9】従来の接合分離済の半導体基板の説明図。FIG. 9 is an explanatory view of a conventional semiconductor substrate after junction separation.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 熱酸化膜 3 熱酸化膜 5 溝 6 熱酸化膜 8 (接合分離用の)p型不純物拡散領域 A 素子形成領域 B 他の領域 1 semiconductor substrate 2 thermal oxide film 3 thermal oxide film 5 groove 6 thermal oxide film 8 p-type impurity diffusion region (for junction separation) A element formation region B other region

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の所定の素子形成領域とその
外側の他の領域の間に反対導電型の不純物を基板の厚み
方向に拡散させることにより前記素子形成領域と他の領
域とを接合分離する不純物拡散領域を形成する方法にお
いて、前記半導体基板として、前記素子形成領域の裏側
に溝が予め形成されている半導体基板を用い、前記反対
導電型の不純物を前記半導体基板の表側の表面と前記溝
の底面の間に渡るように拡散させることにより接合分離
用の不純物拡散領域を形成することを特徴とする接合分
離用の不純物拡散領域の形成方法。
1. An element formation region and another region are bonded and separated by diffusing impurities of opposite conductivity type between a predetermined element formation region of a semiconductor substrate and another region outside thereof in the thickness direction of the substrate. In the method of forming an impurity diffusion region, a semiconductor substrate having a groove formed in advance on the back side of the element forming region is used as the semiconductor substrate, and the impurities of the opposite conductivity type are used on the front surface of the semiconductor substrate and the semiconductor substrate. A method for forming an impurity diffusion region for junction isolation, which comprises forming an impurity diffusion region for junction isolation by diffusing so as to extend between the bottoms of the grooves.
【請求項2】 接合分離用の反対導電型の不純物の拡散
を半導体基板の表側の表面と前記溝の底面の両方より両
不純物の拡散領域が繋がるように行う請求項1記載の接
合分離用の不純物拡散領域の形成方法。
2. The junction isolation junction according to claim 1, wherein diffusion of impurities of opposite conductivity type for junction isolation is performed such that both impurity diffusion regions are connected from both the front surface of the semiconductor substrate and the bottom surface of the groove. Method of forming impurity diffusion region.
JP797093A 1993-01-20 1993-01-20 Method of forming impurity diffusion region for isolation Pending JPH06216234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP797093A JPH06216234A (en) 1993-01-20 1993-01-20 Method of forming impurity diffusion region for isolation

Publications (1)

Publication Number Publication Date
JPH06216234A true JPH06216234A (en) 1994-08-05

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Family Applications (1)

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JP797093A Pending JPH06216234A (en) 1993-01-20 1993-01-20 Method of forming impurity diffusion region for isolation

Country Status (1)

Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010003928A (en) * 2008-06-20 2010-01-07 Toshiba Corp Solid-state image pickup device and method for manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4960687A (en) * 1972-10-13 1974-06-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4960687A (en) * 1972-10-13 1974-06-12

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010003928A (en) * 2008-06-20 2010-01-07 Toshiba Corp Solid-state image pickup device and method for manufacturing the same

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