JPH06214815A - Serial parity calculation circuit - Google Patents

Abstract

PURPOSE:To calculate a parity value without converting serial data to parallel data and to compress a circuit scale by performing parity calculation between input digital signal sequence and serial digital input delayed by prescribed bits with an accumulation means, and reading out or storing a result in series. CONSTITUTION:A BIP-4 parity calculation circuit 1 is constituted of an AND circuit 6, an EXOR circuit 7, and D flip-flops 8-11. D1-D12 being one frame of the serial data are inputted from an input terminal 3 sequentially, and they are shifted to the D flip-flops 8-11. When D5 is inputted, D1 that is the content of the D flip-flop 11 is inputted to the EXOR circuit 7, and D1(XOR)D5 is inputted to the D flip-flop 8, and the calculation result of BIP-4 is held in the D flip-flops 8-11 by repeating such operation up to D12. Thence, a parity collation circuit 2 collates the calculation result of BIP-4 with BIP-4 signal sequence included in received serial data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity circuit for error detection in digital signal transmission and the like.

[0002]

2. Description of the Related Art In order to detect an error in a transmission path of digital signal transmission, a parity (hereinafter, referred to as BIP-N) every (N-1) bits (N is a natural number) is generated and transmitted. However, the receiving side calculates the serial parity, collates it with the transmitted parity, and detects an error based on the difference between the two. FIG. 8 is a block diagram of a circuit for calculating the parity shown in, for example, "Practical Electronic Circuit Handbook 4" (P.75, FIG. 1-97) of CQ Publisher. Figure 8
3, serial data input terminal, 4 reset input terminal, 5 clock input terminal, 7 exclusive OR circuit, 8
Is a D flip-flop, 26 is a parity calculation circuit, 27
Is a calculated parity output terminal. 9 is a block diagram of a BIP-N error detection circuit using the conventional parity calculation circuit shown in FIG. In FIG. 9, 18 is an error detection signal output terminal, 28 is a 1: N serial-parallel conversion circuit, and 29 is a parity matching circuit.

Next, the operation of the circuit shown in FIG. 8 will be described.
A serial data string is input to the serial data input terminal 3 as D1, D2, ..., Dm (m: the number of data in one frame). Immediately before D1 is input to the D flip-flop 8, (1) (L) is input from the reset input terminal 4 to set the content of the D flip-flop (8) to (L). When the contents (1), (1), of D1 and D flip-flop 8 are input to the exclusive OR circuit 7, the exclusive OR circuit 7 outputs D1 and inputs the D1 to the D flip-flop 8. Next, D2 and D1 which is the content of the D flip-flop 8 are input to the exclusive OR circuit 7, and the D flip-flop 8 receives D1 (XOR) D2 ((X
The exclusive OR is input to OR). When this operation is repeated up to Dm, the serial data string 1 is stored in the D flip-flop 8.
Frame parity D1 (XOR) D2 (XOR) (XO
R) Dm is held and output to the calculated parity output terminal 27.

The operation of the circuit shown in FIG. 9 will be described. , Dm are input from the serial data input terminal 3, and BI
It is input to the P-N error detection circuit. Further, the 1: N serial / parallel conversion circuit 28 converts the data into N parallel data strings as described below. After the parity calculation circuit 26 calculates the parity of the signal sequences (1), (2), ..., (3), the transmitted parity and the calculated parity are compared by the parity comparison circuit 29. If there is a difference between the two, a pulse is output from the error detection signal output terminal 18.

[0005]

In the conventional system as described above, the BIP-N is calculated from the serial digital signal sequence and the calculated BIP-N signal and the received BIP-N signal are collated with each other in a serial / parallel manner. There is a problem in that a conversion circuit is required, and N pieces of parity calculation circuits and N pieces of parity collation circuits are required, which makes the circuit scale large and complicated.

The present invention has been made in order to solve such a problem, and a digital signal train is serially connected to a BIP.
An object of the present invention is to obtain a circuit capable of calculating −N, and thus a circuit capable of collating the parity between the calculated BIP-N and the received serial BIP-N signal sequence.

[0007]

A serial parity calculating circuit according to the present invention comprises storage means for serially storing a serial digital input string synchronized with a clock, and reset means for resetting the storage means at an arbitrary time. A parity calculating means for reading data from the accumulating means and calculating a parity value, and a second accumulating means for serially storing the calculation result of the parity calculating means are provided as needed.

[0008]

In the serial parity calculating circuit of the present invention, the parity is calculated between the input digital signal sequence and the serial digital input delayed by a predetermined bit by the accumulating means, and the result is read out or serially stored if necessary. And read when required.

[0009]

【Example】

Example 1. A parity calculating circuit and a parity collating circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a BIP-4 error detection circuit in which the parity calculation circuit and the parity collation circuit of the present invention are applied to every 4 bits / parity. In FIG. 1, 1 is a BIP-4 calculation circuit and 2 is a BIP-4 matching circuit. As components of the calculation circuit, 6 is an AND circuit, and 8 to 11 are D flip-flops, which form a 4-bit shift register. Further, as components of the matching circuit, 12 is a control circuit and 13 to 16 are D.
The flip-flop constitutes a 4-bit shift register. Reference numeral 17 is a matching circuit. This parity calculation circuit 1
The parity check circuit 2 has a function of replacing the conventional four sets of parity calculation circuits and parity check circuits.

Next, the operation of the circuit of FIG. 1 will be described based on the time chart of FIG. First, the operation of the parity calculation circuit will be described. One frame of serial data is composed of 12 data strings D1 to D12, of which D7,
D8, D9, and D10 are the BIP-4 signal sequence P of the previous frame
It means 1, P2, P3, and P4. The calculation formula of BIP-4 is represented by the following formula. P1 _n = D1 _n-1 (XOR) D5 _n-1 (XOR) D9 _n-1 (4) P2 _n = D2 _n-1 (XOR) D6 _n-1 (XOR) D10 _n-1 (5) P3 _n = D3 _n-1 (XOR) D7 _n-1 (XOR) D11 _n-1 (6) P4 _n = D4 _n-1 (XOR) D8 _n-1 (XOR) D12 _n-1 (7) where (XOR ) Represents an exclusive logical wheel as described in the conventional example.

Serial data is input from the serial data input terminal 3 to B.
It is input to the IP-4 error detection circuit. When inputting D1 to D4 at the beginning of the serial data signal sequence to the D flip-flop 8, the output of the AND circuit 7 is changed to ■ L so that the contents of the D flip-flop 11 are not affected. ■ to When D1 to D4 and {circle around (L)} are input to the exclusive OR circuit 7, outputs become D1 to D4, which are sequentially input to the D flip-flop 8 and are shifted to the D flip-flops 9, 10 and 11. Reset input terminal 4 when D5 is input to D flip-flop 8
Input H to D5 and D flip-flop 11
The content of D1 is input to the exclusive OR circuit 7,
1 (= D1 (XOR) D5) is output and input to the D flip-flop 8. If this operation is continued until D8, * 4 (= D
4 (OXR) D8), * 3 (= D3 (XOR) D7), * 2 (=
D2 (XOR) D6), * 1 is retained. Continuing similarly, the contents of D flip-flop 11 D1 (XOR) D5 and D
Exclusive OR of 9 # 1 (= D1 (XOR) D5 (XOR) D9)
Is input to the D flip-flop 8. Repeat up to D12, and the D flip-flops 8, 9, 10, 11 will show B
The calculation result of IP-4 is # 4 (= D4 (XOR) D8 (XO
R) D12), # 3 (= D3 (XOR) D7 (XOR) D1
1), # 2 (= D2 (XOR) D6 (XOR) D10) and # 1 are held. In this way, BIP-4 can be calculated.

Next, the operation of the parity matching circuit will be described. BIP-4 calculated by the parity calculation circuit
And the BIP-4 signal sequence P1 (= D7), P2 (= D8), P3 (= D9) included in the received serial data,
The operation of collating with P4 (= D10) will be described.
When the 4-bit parity BIP-4 of the serial data is calculated, the control circuit 12 generates a control clock for extracting the BIP-4 signal, and the D flip-flops 13 to 16 start operating. D flip-flops 13, 14, 15, 1
When # 4, # 3, # 2, and # 1 are input to 6 respectively,
The control circuit 12 stops the clock and transmits the BIP-4.
The contents of the D flip-flops 13 to 16 are held until they are in phase. When the phases are aligned, a clock is generated again, and the D flip-flop 16 causes the matching circuit 17 to
Then, the calculated BIP-4s # 1, # 2, # 3, and # 4 are sequentially output. The matching circuit 17 transmits the BI at the same timing.
P-4 and calculated BIP-4 are input bit by bit. If there is an error in the data string during transmission, there is a difference between the two, and the matching circuit 17 outputs the detection signal strings A1, A2, A3, and A4 to the error detection signal output terminal 18 in order.

Example 2. BI according to another embodiment of the present invention
A configuration diagram of the P-4 error detection circuit is shown in FIG. Although the first embodiment is a BIP-4 error detection circuit in the case where the serial data also includes the BIP-4 of the previous frame, FIG. 3 shows a case where the serial data does not include the BIP-4 of the previous frame and is distinguished. It is a BIP-4 error detection circuit.

Next, the operation of the circuit of FIG. 3 will be described based on the time chart of FIG. D flip-flop 8,
The operation up to the point where # 4, # 3, # 2, and # 1 are input to 9, 10, and 11 is the same as the operation of the circuit of the first embodiment. After that, the D flip-flop 11 outputs # 1, but since the phase of # 1 and the phase of P1 of the transmitted BIP-4 are aligned, # 1 is sent to the matching circuit 17 at this timing.
Should be output. It is not necessary to prepare another shift register to store the calculated BIP-4 and to match the BIP-4 phase when it is transmitted as in the first embodiment. The matching circuit 17 transmits the transmission BIP-4 and the calculation BIP at the same timing.
-4 is input bit by bit. If there is a difference between the two due to a transmission error or the like, the matching circuit 17 outputs the error detection signal output terminal 18
The detection signal trains A1, A2, A3 and A4 are output to.

Example 3. FIG. 5 shows the configuration of the BIP-4 error detection circuit according to another embodiment of the present invention. In the figure, 19 is a memory having a serial input / parallel output function, 20
Is an adder, 21 is a memory control circuit, and 22 is a memory. The storage / reset means is performed by the memory 19. In this case, the capacity of the memory 19 is required for one frame of data.

Next, the operation of the circuit of FIG. 5 will be described based on the time chart of FIG. One frame is composed of 12 data strings D1 to D12. At the beginning of the frame, a reset signal is input to the reset signal input terminal 4, and the memory control circuit 21 resets the address to the initial value. After that, the address is operated to sequentially write the serial data in the memory 19. When writing is completed up to D9, D1, D
When 5 and D9 are read all at once and input to the adder 20,
The BIP-4 calculation result appears in the least significant bit of the adder 20 and is written in the memory 22. By repeating the same operation, the above-mentioned # 1 to # 4 are written in the memory 22. The collation is a comparison between the written calculation result and the transmission data. That is, the memory control circuit 21 controls the written # 1 to # 4 to be read at an appropriate time,
The collation circuit 17 collates with P1 to P4 of the transmission data, and the error detection signal terminal 18 receives the detection signal strings A1, A2, A3, A.
4 is output.

Embodiment 4. An embodiment of another parity calculation circuit of the present invention will be described. FIG. 7 shows a BIP-4 generation circuit for a serial digital signal sequence according to the parity calculation method of the present invention. In FIG. 7, 23 is a BIP-4 generation circuit, and 24 is B.
IP-4 insertion circuit, 25 is a serial data output terminal.
In this way, the parity can be calculated.

[0018]

As described above, according to the present invention, since the parity value can be calculated without converting serial data into parallel, the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a BIP-4 error detection circuit which is an embodiment of a parity calculation circuit and a parity check circuit of the present invention.

FIG. 2 is a time chart diagram of the BIP-4 error detection circuit of the first embodiment.

FIG. 3 is a configuration diagram of a BIP-4 error detection circuit which is another embodiment of the parity calculation circuit and the parity check circuit of the present invention.

FIG. 4 is a time chart of the BIP-4 error detection circuit according to the second embodiment.

FIG. 5 is a configuration diagram of a BIP-4 error detection circuit which is another embodiment of the parity calculation circuit and the parity check circuit of the present invention.

FIG. 6 is a time chart of the BIP-4 error detection circuit according to the third embodiment.

FIG. 7 is a configuration diagram of a BIP-4 parity calculation circuit according to a fourth embodiment.

FIG. 8 is a configuration diagram of a conventional parity generation circuit.

9 is a BIP-N error detection circuit using the parity generation circuit of FIG.

[Explanation of symbols]

 1 BIP-4 calculation circuit 2 BIP-4 collation circuit 3 Serial data input terminal 4 Reset input terminal 5 Clock input terminal 6 AND circuit 7 Exclusive OR circuit 8-11 D flip-flop 12 Control circuit 13-16 D flip-flop 17 collation circuit 18 error detection signal output terminal 19 memory 20 addition circuit 21 memory control circuit 22 memory 23 BIP-4 generation circuit 24 BIP-4 insertion circuit 25 serial data output terminal 26 parity calculation circuit 27 calculated parity output terminal 28 1: N Serial-parallel conversion circuit 29 Parity matching circuit

Claims (1)

[Claims] 1. A storage means for serially storing a digital input string synchronized with a clock, a reset means for resetting the storage means at an arbitrary time, and a parity calculation means for reading data from the storage means and calculating a parity value. And a second storage means for serially storing the calculation result of the parity calculation means, if necessary, and a serial parity calculation circuit.