JPH06209319A - Network connection device - Google Patents

Abstract

PURPOSE:To improve the conversion processing efficiency of the address bit sending order by writing an address in a storage means as address data which is converted to the bit sending order of a network of the conversion destination. CONSTITUTION:A CPU 41 instructs an access control part 42 to select a port P2 or set a memory 34 to the writable state. As the result, the output enable signal from the access control part 42 is inputted to only the port P2, and the write signal from the access control part 42 is inputted to the memory 34, and the CPU 41 writes address data in a register A in the memory 34. At this time, address data of the bit sending order of D7 to D0 which is made opposite to the bit sending order of D0 to D7 of inputted address data by conversion is outputted from the port P2. As the result, address data according with the bit sending order of LAN-B is written in the memory 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network connection device connected to a plurality of networks having different bit transmission order of addresses.

[0002]

2. Description of the Related Art Conventionally, in some local area networks (hereinafter referred to as LAN), the bit transmission order of addresses differs depending on the access control method. For example, I
In the CSMA / CD system of the IEEE802.3 standard, the address is transmitted from the LSB, and the IEEE802.
In the standard 5 token ring system, the address is transmitted from the MSB.

In order to connect LANs in which the bit transmission order of the addresses is different from each other, a network connection device is provided between the LANs, and the network connection device has an address matching the bit transmission order of the addresses of each LAN. By performing the conversion, communication between each LAN is enabled. As the address conversion method, Japanese Patent Laid-Open No.
The one disclosed in Japanese Patent No. 132233 is known.

FIG. 3 shows a block diagram of a conventional system. In FIG. 3, in the system, the terminal 1 is connected to the LAN-A adopting the CSMA / CD method, and the LAN adopting the token ring method.
-A terminal 2 is connected to -B, and these LAN
The network connection device 3 is interposed therebetween.

The network connection device 3 is mainly used for each LAN.
Connection control units 31 and 32 for controlling transmission / reception to and from each other, a protocol conversion unit 33 that performs protocol conversion of the frame extracted by each connection control unit, and a frame relay between each connection control unit and protocol conversion unit 13. And a memory 34.

Communication in such a conventional system will be briefly described. First, when the terminal 1 sends data (frame) to the terminal 2, this frame has L bits so that the bit sending order of the address is sent from the LSB.
After passing through the AN-A and the connection control unit 31, the connection control unit 31 responds to the command from the protocol conversion unit 33, and then the memory 3
Stored in 4. Then, the protocol conversion unit 33 sets the address of the frame stored in the memory 34 to the LAN-
The bit transmission order is converted (rewritten) so that the data can be transmitted in the bit transmission order of the address that can be transmitted in B (in this case, the address is transmitted from the MSB). Then, when the protocol conversion unit 33 gives a command to the connection control unit 32 that it can be read, the connection control unit 32 reads the address-converted frame from the memory 34 and sends it to the LAN-B. As a result, the address-converted frame is input to the terminal 2. On the other hand, when data (frame) is sent from the terminal 2 to the terminal 1, the same processing as above is performed.

Incidentally, in the past, the protocol conversion unit 3
All the bit transmission order conversion of the address executed in No. 3 was performed by software.

Here, a more detailed structure of the protocol conversion unit 33 is shown in FIG. In FIG. 4, the protocol conversion unit 3
3 is a CPU 41 for accessing the memory 34,
An access control unit 42 is provided which sends an address / control signal to the memory 34 under the control of the CPU 41 and sends a control signal to each of the connection control units. Further, the CPU 41 is provided with registers A and B (not shown) for temporarily storing addresses.

Next, the address conversion process will be described with reference to FIG.

When the connection control unit 31 stores the frame input via the LAN-A in the memory 34 and notifies the protocol control unit 33 that the frame data from the LAN-A has been written in the memory 34, the protocol is notified. In the control unit 33, the CPU 41 controls the access control unit 4
2 is instructed to read the above data.

As a result, the access control unit 4 is stored in the memory 34.
Since the read signal from 2 is input, CP
U41 defines n = 8, reads 8-bit address data (for example, 11001111) from the memory 34, and registers in its own register A (not shown).
(Step 51). Next, the CPU 41 writes the bit data of the bit position of the address in the register A according to the right rotate (from the least significant bit to the most significant bit) order to the buffer C (not shown) provided in itself (carry bit). (Set to flag) (step 52), and this value is written to a register B (not shown) provided in the self at a bit position according to the left rotate (most significant bit to least significant bit) order (step 52). 53). Further, n = n-1 is calculated (step 54), and it is determined whether or not n = 0 (step 55). If n ≠ 0, the above step 52 is performed.
And step 52 to step 55 are repeated until n = 0 is reached. Then, in step 55, n = 0
In the case of, the address data (11110011 in this example) in the register B is written in the memory 34 (step 56).

The frame data from the LAN-A including the address data whose address transmission order has been converted in this way is read by the connection control unit 32 according to the instruction of the CPU 41 and is transmitted to the LAN-B. It will be.

When transmitting a frame from LAN-B to LAN-A, the same conversion process as described above is performed.

As described above, while the bit order conversion is performed by software, the bit order conversion processing is realized by hardware as disclosed in Japanese Patent Laid-Open No. 3-268132, thereby reducing the processing time. It is also known to shorten the length.

Furthermore, the hardware shown in FIG. 6 in which the bit order conversion is performed by combining the above-described software processing and hardware processing is also possible. The example shown in FIG. 6 has a configuration in which an address conversion register 60 is added to the configuration of the example shown in FIG. The address conversion register 60 is set so as to match the bit transmission order of LAN-A and LAN-B described above.

Next, the address conversion process will be described with reference to FIG.

When the CPU 41 receives from the connection control unit 31 that the frame from LAN-A has been written in the memory 34 in the same manner as described above, the CPU 41 causes the access control unit 42 to make the memory 34 readable. , And instructing the address conversion register 60 to be in a writable state. Then, the read signal from the access control unit 42 is input to the memory 34, and the address conversion register 6
Since a write signal from the access control unit 42 is input to 0, the CPU 41 controls the memory 3 via the data bus 1.
Address data of 4 to 8 bits (for example, 110011)
11) is read and written in the register A (not shown) provided in itself (step 71),
The address data in the register A is transferred to the data bus 1,
The data is written in the address conversion register 60 via the data bus 2 (step 72).

Next, the CPU 41 makes the memory 34 writable by the access control unit 42.
It also instructs the address conversion register 60 to be in a readable state. Then, since the write signal from the access control unit 42 is input to the memory 34 and the read signal from the access control unit 42 is input to the address conversion register 60, the CPU 41 causes the data bus 3 and the data bus 1 to operate. The address data is read from the address conversion register 60 via the memory and written to the register A in the self (in this case, 11110011) (step 73), and the address in the register A is written to the memory 34 via the data bus 1. (Step 74).

The frame data from the LAN-A including the address data whose address transmission order has been converted in this way is read by the connection control unit 32 according to the instruction of the CPU 41 and is transmitted to the LAN-B. It will be.

When transmitting a frame from LAN-B to LAN-A, the same conversion process as described above is performed.

[0021]

However, in the above-mentioned prior art, in the case where the bit order conversion processing is performed by software, the address conversion must be performed for each bit position, and therefore, Since the number of processing steps increases, it is difficult to improve the processing efficiency of the bit sending order.

In the case where the bit order conversion is performed by combining software processing and hardware processing, reading and writing of an address between the memory and a register in the CPU, and the conversion of the register and the address are performed. Since it is necessary to read and write addresses between registers, it cannot be said that the bit transmission order processing efficiency is necessarily good.

It is an object of the present invention to provide a network connection device capable of improving the conversion processing efficiency of the bit transmission order of addresses.

[0024]

According to the present invention, in a network connection device connected to a plurality of networks having different address bit transmission orders, a plurality of connection control means for controlling transmission / reception of data to / from the plurality of networks are provided. A storage means for relaying data between the plurality of connection control means, and a bidirectional input / output for inputting / outputting address data matching the bit transmission order of addresses corresponding to each of the plurality of networks to / from the storage means. Address data from the conversion source network is read from the storage unit via a plurality of ports and a port corresponding to the conversion source network, and the read address data is read via a port corresponding to the conversion destination network. And an access unit for writing in the storage unit.

[0025]

In the present invention, by the access means,
The address data from the conversion source (transmission source) network stored in the storage means is read out as address data in a predetermined bit transmission order through a bidirectional port corresponding to the conversion source network, and this address is also read. Since the data is written to the storage means as address data converted into the bit transmission order of the conversion destination network via the bidirectional port corresponding to the conversion destination (transmission destination) network, the address bit Data can be transmitted / received between a plurality of networks having different transmission orders.

[0026]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a network connection device according to the present invention. In this block diagram, the address translation register 60 is deleted from the conventional block diagram shown in FIG.
It has a configuration in which 1 and 2 are added. Note that, in FIG. 1, portions that perform the same functions as the components shown in FIG. 6 are denoted by the same reference numerals.

The port P1 is an address data input / output terminal MD7, MD6, MD5, MD on the memory data bus 1 side.
4, MD3, MD2, MD1, MD0, and address data input / output terminals CD7, CD6 on the CPU data bus 2 side.
CD5, CD4, CD3, CD2, CD1 and CD0 correspond to each other.

The port P2 is an address data input / output terminal MD0, MD1, MD2, MD on the memory data bus 1 side.
3, MD4, MD5, MD6, MD7 and address data input / output terminals CD7, CD6 on the CPU data bus 2 side.
CD5, CD4, CD3, CD2, CD1 and CD0 correspond to each other.

In these ports, the input / output terminal M
Data D7 of 2 ⁷ bit positions input / output from D7 is input / output from the input / output terminal CD7.

Data D6 of 2 ⁶ bit positions input / output from the input / output terminal MD6 is input / output from the input / output terminal CD6.

Data D5 of 2 ⁵ bit positions input / output from the input / output terminal MD5 is input / output from the input / output terminal CD5.

Data D4 of 2 ⁴ bit positions input / output from the input / output terminal MD4 is input / output from the input / output terminal CD4.

Data D3 of 2 ³ bit positions input / output from the input / output terminal MD3 is input / output from the input / output terminal CD3.

The data D2 of 2 ² bit positions input / output from the input / output terminal MD2 is input / output from the input / output terminal CD2.

Data D1 of 2 ¹ bit positions input / output from the input / output terminal MD1 is input / output from the input / output terminal CD1.

[0037] Data D0 bit position 2 ⁰ which is output from the output terminal MD0 is output from the output terminal CD0.

Therefore, D0, D1, D2, D3, D
When the address data in the bit transmission order of 4, D5, D6, D7 is input to the port P1 via the memory data bus 1, the port P1 outputs D0, D1, D2, D3, D.
Address data in the bit transmission order of 4, D5, D6, and D7 is output to the CPU data bus 2. D0 to D7
When the address data of the bit transmission order of is input to the port P1 via the CPU data bus 2, the address data of the bit transmission order of D0 to D7 is output to the memory data bus 1 from the port P1. .

D7, D6, D5, D4, D3, D
When the address data in the bit transmission order of 2, D1 and D0 is input to the port 2P via the memory data bus 1, D0, D1, D2, D3, D4 and D are input from the port P2.
Address data in the bit transmission order of 5, D6, and D7 is C
It is output to the PU data bus 2. When the address data in the bit transmission order of D0 to D7 is input to the port 2P, the address data in the bit transmission order of D7 to D0 is output to the memory data bus 2 from the port 2P.

Address conversion processing in the above configuration will be described with reference to FIG.

The access control unit 31 receives a frame sent from the terminal 1 on the LAN-A to the terminal 2 on the LAB-B, stores the frame in the memory 34, and stores the frame in the memory 34 in the LAN-A. When the protocol control unit 33 is notified of the fact that the frame data has been written and the destination information, the CPU 41
Instructs the access control unit 42 to select the port P1 and to put the memory 34 in a readable state. As a result, the output enable signal from the access control unit 42 is input only to the port P1, and the read signal from the access control unit 42 is input to the memory 34.

Since the bit transmission order of each of LAN-A and LAN-B is defined in advance, the CPU 41
Knows the connection control unit that has notified that the frame data has been written and the destination information, so that the conversion source (source)
You can find out the port corresponding to the network, and based on the received destination information, the conversion destination (destination)
You can find out which port corresponds to your network.

When the memory 34 becomes readable and the port P1 is selected, the CPU 41 reads the address data in the frame data from the memory 34 via the memory data bus 1, the port P1 and the CPU data bus 2. , Write to a register A (not shown) provided in itself (step 100).

At this time, D0, D1, D2, D3, D input via the memory data bus 1 from the port P1.
Address data in the bit transmission order of 4, D5, D6, and D7 is output in the same bit transmission order. LA here
The address data of the frame from NA is, for example, “11”.
If it is 001111 ", the address data of" 11001111 "is written in the register A.

Next, the CPU 41 instructs the access control unit 42 to select the port P2, and the memory 34.
To write to. As a result,
The output enable signal from the access control unit 42 is input only to the port P2, and the write signal from the access control unit 42 is input to the memory 34. Then CPU4
1 writes the address data in the register A to the memory 34 via the CPU data bus 2, port P2, and memory data bus 1 (step 200).

At this time, D0, D1, D2, D3, D input from the port P2 via the CPU data bus 2 is input.
The address data in the bit transmission order of 4, D5, D6, and D7 is converted in the reverse order of the bit transmission order, that is, D7,
Address data in the bit transmission order of D6, D5, D4, D3, D2, D1, and D0 is output. As a result, the memory 34 stores the address data (“11110011” in this example) according to the LAN-B bit transmission order.
Data of the bit transmission order of) will be written.

The frame data from the LAN-A including the address data whose address transmission order has been changed in this way is read by the connection control unit 32 according to the instruction of the CPU 41 and is transmitted to the LAN-B. It will be.

When transmitting a frame from LAN-A to LAN-B, the address conversion processing similar to the above is carried out.

In the above-described embodiment, the ports P1 and P2 are provided corresponding to the two LAN-A and LAN-B whose bit transmission order is different, but when there are three or more networks whose bit transmission order is different. By providing a port corresponding to each network and performing the conversion processing as described above, the address conversion can be performed quickly.

At this time, in FIG. 1, the arrangement of the input / output terminals on the memory data bus 1 side of the ports corresponding to the network is set so that the bit arrangement is in accordance with the bit transmission order of the network, while the CPU The arrangement of the input / output terminals on the data bus 2 side is the same as the above-mentioned ports P1 and P2.
It may be set so as to be the same as the bit arrangement on the CPU data bus 2 side.

As described above, according to this embodiment, the protocol conversion unit 33 reads out the address data written in the memory 34 through the port corresponding to the network of the conversion source (transmission source) and converts the address data. By writing to the memory 34 via the port corresponding to the destination (destination) network, the bit transmission order of the addresses can be converted, and the conversion processing can be performed quickly. Therefore, the frame packet relay capability can be improved.

In the conventional protocol conversion unit 33 shown in FIG. 6, the address data in the memory 34 is converted into CP.
After once writing to the register A in U41, this address data is written to the address conversion register 60, and then the address data in the address conversion register 60 is written to the CPU.
This address data must be written in the memory 34 once it has been written in the register A in 41, which requires a lot of time for the address conversion process.

[0053]

As described above, according to the present invention, the address data from the network of the conversion source (transmission source) stored in the storage means is corresponded to the network of the conversion source by the access means. It is read out as address data in a predetermined bit transmission order via the port for the destination, and this address data is also converted (transmission destination).
Since the address data converted into the bit transmission order of the conversion destination network is written in the storage means via the bidirectional port corresponding to the network of the above, it is possible to transmit the data between a plurality of networks having different address bit transmission orders. Data can be sent and received.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a network connection device according to the present invention.

FIG. 2 is a flowchart showing a conversion processing operation of an address bit transmission order according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional system composed of networks having different bit transmission orders of addresses.

FIG. 4 is a diagram showing a configuration of a conventional protocol conversion unit.

5 is a flowchart showing a processing operation of a protocol conversion unit shown in FIG.

FIG. 6 is a diagram showing the configuration of another conventional protocol conversion unit.

7 is a flowchart showing the processing operation of the protocol conversion unit shown in FIG.

[Explanation of symbols]

33 ... Protocol converter, 34 ... Memory, 41 ... CP
U, 42 ... Access control unit, P1, P2 ... Port.

Claims (1)

[Claims] 1. A network connection device connected to a plurality of networks having different bit transmission order of addresses, wherein a plurality of connection control means for controlling transmission and reception of data to and from the plurality of networks, and a plurality of the connection control means are provided. Storage means for relaying data between the storage means, a plurality of bidirectional ports for inputting and outputting address data matching the bit transmission order of addresses corresponding to each of the plurality of networks, to the storage means, Access means for reading address data from the conversion source network through the port corresponding to the network and writing the read address data in the storage means through the port corresponding to the conversion destination network; A network connection device comprising: