JPH06209245A - Delay circuit - Google Patents

Abstract

PURPOSE:To minimize the power supply voltage dependence of a delay circuit, and to reduce the fluctuation of a delay time by supplying the voltage of an inside delay circuit by a regulator at the time of operating an LSI ship in a wide power supply voltage range. CONSTITUTION:An input signal 11 is delayed by an inside delay circuit 1, and becomes a delay signal 12 having the common-phase of the input signal 11 and a delay signal 13 having the opposite phase of the input signal 11. A flip- flop circuit 4 performs set/reset based on the delay signals 12 and 13, and outputs an output signal 16. An exclusive OR circuit 3 turns a regulator 2 into an operation state or non-operational state based on the input signal 11 and the output signal 16. A regulator 2 generates the voltage established as the threshold voltage of a transistor constituting the circuit, and the voltage is supplied as an operating voltage 14 of the inside delay circuit 1. Thus, even when the power supply voltage fluctuates, the fluctuation of the voltage 14 supplied to the delay circuit 1 can be reduced, and the fluctuation of the delay time can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit using a complementary field effect transistor circuit, and more particularly to a delay circuit in which delay time has a small power supply voltage dependency.

[0002]

2. Description of the Related Art Delay circuits are used in various places inside an LSI chip such as a microcomputer. There is a circuit that generates a clock operation of an LSI as a typical one using a delay circuit, and the clock generation circuit of the LSI will be described with reference to FIG. 5 showing a circuit diagram and a time chart thereof.

The clock generation circuit is composed of two AND gates 50 and 51, three inverters 52 to 54 and two delay circuits 55 and 56, and has a clock input φi.
The clock output φout of the positive phase and the clock output inversion φout of the opposite phase are generated from n.

Here, the clock input φin is used as an input A
A clock output inversion φout having an opposite phase is input to the ND gate 50 via the delay circuit 56 and the inverter 54, and the inverter 5 which is an opposite phase signal of the clock input φin.
A positive-phase clock output φout is input to the AND gate 51 that receives the output of 2 via the delay circuit 55 and the inverter 53.

When the clock input φin changes from "L" level to "H" level, the inverted clock output inversion φout becomes "L" level via the AND gate 51.
When the delay time t1 of the delay circuit 56 elapses, the inverter 5
4 becomes "H" level, and the positive-phase clock output φout becomes "H" level via the AND gate 50.

Next, when the clock input φin changes from "H" level to "L" level, the positive phase clock output φout becomes "H" level via the AND gate 50.
Reversed clock output φout via D gate 51
Becomes "H" level. By repeating this, the positive phase clock output φout and the reverse phase clock output φout
Generates a signal in which the "H" level periods do not overlap and there is an interval of delay time t1 and delay time t2. The delay circuit for generating the clock interval has a delay time of several tens ns, and a circuit in which inverters 61 to 68 as shown in FIG. 6 are connected in series is used. In a logic gate such as an inverter, there is a switching delay between the input of a signal and the change in the output. By connecting the gates in multiple stages in series, this delay is used as a value that can be regarded as a certain amount of time.

[0007]

In recent years, there has been a tendency toward lowering of the chip operating voltage in the application equipment utilizing the LSI. For example, it is required to be able to operate over a wide range from an operating voltage of 2 [V] in a battery to an operating voltage of 6 [V] in a standard logic. In the conventional delay circuit shown in FIG. 6, when the operating voltage range is wide, the delay time is highly dependent on voltage, and when the power supply voltage is reduced from 5 [V] to 2 [V], the delay time is significantly increased by about 3.3 times. (See FIG. 7). When this circuit is used in the operation clock generation circuit shown in FIG. 5, there is a problem that the clock interval becomes wide at a low voltage, the clock pulse width becomes narrow, and normal operation cannot be performed.

It is an object of the present invention to provide a delay circuit having a small delay time voltage dependence, that is, a good voltage dependence characteristic.

[0009]

A delay circuit according to the present invention includes a voltage generating circuit for generating a voltage related to a threshold voltage of a transistor forming the circuit, and a voltage generating circuit using the delayed signal as an input signal. Is a power supply voltage, and a flip-flop that stores the output of the internal delay circuit.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A detailed description will now be given with reference to the drawings of the present invention.

FIG. 1 shows a delay circuit according to the first embodiment of the present invention. The delay circuit according to this embodiment comprises an internal delay circuit 1, a regulator 2, an exclusive OR circuit 3 and a flip-flop 4. .

The internal delay circuit 1 is composed of, for example, a plurality of stages of inverting circuits and outputs a delay signal in phase with the input signal 11 12
A delay signal having a phase opposite to that of the input signal 11 is output to the output 13. The power supply voltage 14 of the internal delay circuit 1 is supplied by the regulator 2. When the power supply voltage 14 is not supplied, the internal delay circuit 1 is in the inactive state and the outputs 12, 13
Are both at "L" level. When the power supply voltage 14 is supplied, the internal delay circuit 1 is activated and the delay signals 12 and 13 are output.

The regulator 2 is in an operating state when the output 15 of the exclusive OR circuit 3 is at "H" level, and is in a non-operating state when the output 15 is at "L" level.

The input of the exclusive logic circuit 3 is the input signal 11
Is connected to the output 16 of the flip-flop 4, and when the respective states match, the output 15 becomes the "L" level, and when they do not match, the output 15 becomes the "H" level.

The flip-flop 4 operates based on the signals 12 and 13 delayed by the internal delay circuit 1, and when the delay signal 12 in phase with the input signal 11 is at "H" level, the flip-flop 4 is set. The output 16 becomes "H" level, the flip-flop 4 is reset and the output 16 becomes "L" level when the delay signal 13 having a phase opposite to the input signal 11 is "L" level.

Next, the detailed operation of the delay circuit of the first embodiment will be described.

For example, consider the case where the input signal 11 is at "L" level as the initial state. The input signal 11 is at "L" level, and therefore the output 15 of the exclusive OR circuit 3 is at "L" level because both inputs are in agreement at "L" level. Since the output 15 of the exclusive OR circuit 3 is at the “L” level, the regulator 2 is in a non-operating state, the voltage 14 is not supplied to the internal delay circuit 1, and the internal delay circuit 1
Also becomes non-operational state, and the flip-flop 4 holds the previous state, that is, the "L" level.

Here, consider the case where the input signal 11 changes to the "L" level. When the input signal 11 becomes the “H” level, it does not match the input 16 of the flip-flop 4, so the exclusive OR circuit 3 outputs the “H” level to the regulator 2 via the signal 15. When the signal 15 becomes the “H” level, the regulator 2 enters the operating state and supplies the voltage to the internal delay circuit 1 through the voltage supply line 14, and the internal delay circuit 1
Becomes active. Along with this, the input signal 11 becomes “H”.
The level is delayed by the internal delay circuit 1 and the input signal 11
The delayed signal 12 in phase with the input signal 11
Since the delay signal 13 of the opposite phase is at the "L" level, the flip-flop 4 is set and the delayed signal is "H".
The level is output to the output signal 16. When the output signal 16 becomes "H" level, the inputs of the exclusive OR circuit 3 coincide with each other. Therefore, when the output 15 of the exclusive OR circuit 3 becomes "L" level, the regulator 2 becomes inactive and the internal delay circuit The supply of voltage to 1 is stopped. Then, the internal delay circuit 1 becomes inactive, and the signals 12 and 13 are both "L".
Hold the level.

Next, consider the case where the input signal 11 changes to "L" level. Since the value of the output 16 of the flip-flop 4 does not match when the input signal 11 becomes "L" level, the output 15 of the exclusive logic circuit 3 becomes "H" level, and the regulator 2 receives the voltage from the voltage supply line 14 and the internal delay circuit 1 outputs. Supply voltage to. When the voltage is supplied, the internal delay circuit 1 is activated, the "L" level of the input signal 11 is delayed, and the delay signal 12 in phase with the input signal 11 is the "L" level signal 1
When 3 becomes "H" level, the flip-flop 4 is reset and outputs "L" level as a delayed signal.
Output to 6. When the output signal 16 becomes "L" level,
Since the inputs of the exclusive OR circuit 3 match, the output 15 of the exclusive OR circuit 3 changes to "L" level. When the output 15 of the exclusive OR circuit 3 becomes the "L" level, the regulator 2 becomes inactive and the supply of the voltage to the internal delay circuit 1 is stopped. Then, the internal delay circuit 1 becomes inactive, and the signals 12 and 13 both become "L" level, so that the flip-flop 4 holds the "L" level of the previous state.

The delay circuit of this embodiment generates a delay signal by repeating the above operation.

The feature of the present invention resides in that the fluctuation of the power supply voltage of the internal delay circuit for generating the delay time is minimized by the regulator to reduce the fluctuation of the delay time.

A concrete circuit diagram thereof will be described with reference to FIG.

The internal delay circuit 1 has a structure in which inverting circuits 21 to 28 are connected in series. The inverting circuit 21 includes a P-channel transistor 201 and an N-channel transistor 10 between the voltage 14 supplied from the regulator 2 and GND.
1 are connected in series, and the inverting circuits 22 to 2
8 also has the same structure as the inverting circuit 21, and is composed of P-channel transistors 202 to 208 and N-channel transistors 102 to 108, respectively. The inverting circuit causes a delay due to switching from the input of the signal to the output of the result. The internal delay circuit 1 functions as a delay circuit by connecting inversion circuits in the required number of stages in series. Therefore, in the internal delay circuit 1, the delay signal in phase with the input signal 11 is output to the output 12 of the inverting circuit 28 (even stage), and the delay signal in phase with the input signal 11 is inverting circuit 2.
It is output to the output 13 of 7 (odd stage).

Next, the regulator 2 will be described. When the output of the exclusive OR circuit 3 is at "H" level, the N-channel transistor 109 and the P-channel transistor 209
Since the output of the inverting circuit composed of is at "L" level, the P-channel transistors 210 and 211 and the N-channel transistor 11 are connected from the power supply voltage terminal VDD to GND.
A current flows through 1. N-channel transistor 111 when the threshold voltage is V _TN of the time N-channel transistor 111 acts as a diode to a threshold voltage V _TN clamp the gate and drain connected. Similarly, the P-channel transistor 211 can be regarded as a diode that clamps to the threshold voltage V _TP , so that the voltage supply 14 is ultimately the threshold voltage V _TN and the threshold voltage V _TP.
A regulated voltage is generated that is clamped at the voltage of the absolute _TP signature (V _TN + | V _TP |). For example V
_{When TN} is 0.8 [V] and V _TP is 0.7 [V], the voltage 14 supplied to the internal delay circuit 1 is 3 even if the power supply voltage changes from 7 [V] to 2 [V]. 1 [V] to 1.7
[V], that is, only about 1.4 [V] changes.

In the exclusive OR circuit 3, when the input signal 11 and the output 16 of the flip-flop 4 do not match, the output 17 of the NOR circuit composed of the N-channel transistors 112 and 113 and the P-channel transistors 212 and 213 is "L". Become a level. In this state, N-channel transistors 114-116 and P-channel transistors 214-2
In the output 15 of the AND-NOR circuit configured by 16, either the input signal 11 or the output 16 of the flip-flop 4 is at the "L" level, so that the P-channel transistor 215 or the P-channel transistor 216 is conductive, and The output 17 of the NOR circuit is "L"
Since the level is the level, the P-channel transistor 214 is in a dynamic state, and thus becomes the “H” level.

When both the input signal 11 and the output 16 of the flip-flop 4 are at "H" level, the N-channel transistors 115 and 116 become conductive and the output 15 becomes "L" level. When both the input signal 11 and the output 16 of the flip-flop 4 are at "L" level, the N-channel transistor 11
2, the output 17 of the NOR circuit composed of P-channel transistors 212 and 213 is "H" level, the N-channel transistor 214 becomes conductive, and the output 15
Goes to "L" level.

In the flip-flop 4, when the set terminal S is at "H" level and the reset terminal R is at "L" level,
Since the set terminal S is at "H" level, the N-channel transistor 117 becomes conductive and the contact 18 becomes "L" level. The “L” level of the contact 18 is the value “H” level inverted by the inversion circuit composed of the N-channel transistor 120 and the P-channel transistor 218, and the contact 1
9 is output. When the contact 19 becomes "H" level, the N-channel transistor 119 and the P-channel transistor 2
The inverting circuit constituted by 17 tries to output the inverted value "L" level to the contact 18, and the stable state is maintained at the "L" level. On the contrary, this is the opposite of the case where the set terminal S is at "L" level, and the contact 18 maintains a stable state at "H" level.

Both the set terminal S and the reset terminal R are L
At the "L" level, both N-channel transistors 117 and 118 do not conduct, and the previous state is maintained.

In the delay circuit of the present invention, the voltage 14 of the internal delay circuit 1 is supplied from the regulator 2 as shown in FIG. 1, so that the fluctuation of the voltage applied to the internal delay circuit 1 is minimized and the delay time is reduced. The purpose is to reduce the fluctuation of. Referring to FIG. 3 showing the characteristic diagram, the power supply voltage is 5
Even if the voltage decreases from [V] to 2 [V], the delay time changes only about 1.4 times.

Next, the delay circuit of the second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the voltage 14 supplied from the regulator 2 to the internal delay circuit 1 is the sum of the threshold voltage V _TN of the N-channel transistor 111 and the threshold voltage V _TP of the P-channel transistor 211 (V _TN +
_{│V TP} │). On the other hand, in the second embodiment, if the threshold voltage of the N-channel transistors 121 and 122 is V _TN 'and the threshold voltage of the P-channel transistors 221 and 222 is V _TP ', the N-channel transistors 121 and 122 are Since the gate and drain are connected, and the gates and drains of the P-channel transistors 221, 222 are also connected, the threshold values V _TN '
And acts as a diode that clamps to the voltage of V _TP '. Therefore, the voltage supply 14 has 2 × V _TN 'or 2
A regulated voltage is supplied to the lower voltage of × | V _TP '|.

Those skilled in the art will understand that the regulator can be implemented in various configurations other than the first and second embodiments. Further, in the present embodiment, the voltage supplied from the regulator output is used as the voltage of the internal delay circuit, but it can be realized by controlling the switching speed of the inverting circuit forming the internal delay circuit.

[0032]

As described above, according to the present invention, since the voltage of the delay circuit is supplied by the regulator, the fluctuation of the voltage supplied to the delay circuit can be small even if the power supply voltage changes. Accordingly, there is a result that the fluctuation of the delay time can be small.

Therefore, in the conventional delay circuit, L at a low voltage is used.
In some cases, the normal operation of SI cannot be guaranteed, but by using the delay circuit of the present invention, the normal operation can be guaranteed even in the low voltage region.

[Brief description of drawings]

FIG. 1 is a block diagram of a delay circuit according to a first exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram of the delay circuit shown in FIG.

FIG. 3 is a characteristic diagram of the delay circuit shown in FIG.

FIG. 4 is a circuit diagram of a delay circuit according to a second embodiment of the present invention.

5A and 5B are diagrams showing an operation clock generation circuit, in which FIG. 5A is a circuit diagram thereof and FIG. 5B is a timing chart.

FIG. 6 is a block diagram of a conventional delay circuit.

7 is a characteristic diagram of the delay circuit shown in FIG.

[Explanation of symbols]

 1 Internal delay circuit 2 Regulator 3 Exclusive OR circuit 4 Flip-flop 11 Input signal 12 Delay signal in phase with input signal 13 Delay signal with opposite phase to input signal 14 Supply voltage from regulator to delay circuit 15 Exclusive OR circuit Regulator control signal 16 Output signal 17 NOR circuit output of exclusive OR circuit 18 Displacement point of flip-flop set terminal 19 Displacement point by flip-flop set terminal 50,51 AND gate 52-54 Inverter 55,56 Delay circuit φin Input signal φout Positive Phase clock output Inversion φout Reverse phase clock output 61-68 Inverters 101-120 N-channel transistors 201-218 P-channel transistors

Claims (2)

[Claims] 1. A voltage generation circuit that generates a voltage related to a threshold voltage of a transistor that forms a circuit, and an internal circuit that uses a delay signal as an input signal and a voltage generated by an output voltage of the voltage generation circuit as a power supply voltage. A delay circuit comprising a delay circuit and a flip-flop for storing the output of the internal delay circuit. 2. The delay circuit according to claim 1, further comprising a mismatch detection circuit that receives the input signal and the output of the flip-flop as input and controls the operation of the voltage generation circuit.