JPH06208464A - Microcomputer - Google Patents

Abstract

PURPOSE:To obtain a microcomputer capable of changing the register number of a general purpose resister. CONSTITUTION:An adder 33 (or 34) adds the value of a pointer 30 indicating the start point information of an access to a general purpose register group 4 to a value relating to a register field LX (or LY) on a signal line 31 (or 32). The added result is sent to an RX decoder 45 (or RY decoder 46) or an RZ decoder 47 through the 5th (or 6th) latch circuit 35 (or 36), the 9th latch circuit 37 and the 10th latch circuit 38 and the RX decoder 45 (or RY decoder 46) or the RZ decoder 47 selects a general purpose resister in the register group 4 in accordance with a register number indicated by the added result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a register file.

[0002]

2. Description of the Related Art FIG. 8 shows "MC68020 32-Bit Microprocesso".
FIG. 3 is a block diagram showing a microprocessor MC68020 disclosed in “r User's Manual Second Edition”. In the figure, 61 is an instruction cache unit for temporarily storing an instruction word transferred from a memory (not shown) via a data bus 92. The instruction cache unit 61 is connected via an internal bus 66 to a decoding unit 62 that decodes an instruction code and outputs a control signal 67. The decoding unit 62 is a sequence unit that controls devices in the microprocessor based on the control signal 67.
Connected to 63. The sequence unit 63 is connected to the decoding unit 62 via an internal bus 66, and is further connected to an execution unit 65 that executes an instruction code, an input / output operation of an external device (not shown), and a bus controller 60 that gives other instructions. There is.

The execution unit 65 is connected to the instruction cache unit 61, the bus controller 60 is connected to the control signal line 91, and the instruction cache unit 61 and the execution unit 65 are connected to the address bus 90 and the data bus 92. . The sequence unit 63
Has a control unit 64 for controlling the operation of the sequence unit 63.

The operation of this microcomputer will be described below. The instruction code read from the memory (not shown) is transferred to the instruction cache unit 61 via the data bus 92 and stored in the instruction cache unit 61, and the instruction code stored in the instruction cache unit 61 is transferred via the internal bus 66. Is transferred to the decoding unit 62, the instruction code transferred to the decoding unit 62 is decoded and converted into a control signal 67, the control signal 67 is sent to the sequence unit 63, and the sequence unit 63 outputs the control signal 67. A signal for controlling the operations of the execution unit 65, the instruction cache unit 61, and the decoding unit 62 is sent out based on the internal bus 66. The execution unit 65 executes the instruction, reads the instruction stored in the instruction cache unit 61 from the instruction cache unit 61 whenever necessary, and executes the instruction.
The address information is sent to an external device (not shown) or a memory via the drive to drive the external device (not shown) or read an instruction code stored in the memory (not shown).

FIG. 9 is a schematic register configuration diagram showing a part of the configuration of a general-purpose register group as a register file included in the microprocessor 68020. The data registers D0, D1 ... D7 for users, the address registers A0, A1 ... A6 for temporarily storing address information, the stack pointer and the program counter used in the user stack memory are each 32 bits long. Furthermore, the condition code register for temporary storage of the condition code of the microprocessor is 16 bits long,
The interrupt stack pointer, which indicates the stack memory pointer used during interrupt processing, is 32 bits long.

In FIG. 10, the data stored in the OFF1 address and the OFF2 address are added using the instruction code used in the microprocessor MC68020, and the addition result is registered in the register D7.
3 is a flowchart showing a procedure for storing the data in a sub-routine and is configured to be processed by a subroutine. In the flowchart shown in the figure, save the value of register D6 to a memory not shown.
(S1), read the data stored at memory OFF1 address and transfer to register D6 (S2), read the data at memory OFF2 address and transfer to register D7 Transfer frequency (S3), register
After adding the value of D6 and the value of register D7 and storing the addition result in register D7 (S4), the value of register D6 saved in the memory is read and restored to the original register D6 (S5), and the return instruction (S6) to return the program processing from the subroutine to the main routine.

FIG. 11 is a program list for performing the processing of the flowchart of FIG. MOV D6,-(USP) is an instruction code that saves the value of register D6 to the user stack memory. MOV (OFF 1). W, D6 is the instruction code to transfer the value at address OFF1 to register D6. MOV (OFF 2).
W and D7 are instruction codes that transfer the value at address OFF2 to register D7. ADD D6, D7 are instruction codes for adding the value of register D6 and the value of register D7 and storing the addition result in register D6. MOV (USP) +, D6 is an instruction code that reads the value of the user stack memory and returns to register D6. RTS is an instruction code indicating a return instruction that returns the processing of the program from the subroutine to the main routine.

In this subroutine, the instruction code RT
The value saved in the user stack memory is restored to register D6 by the instruction code MOV (USP) +, D6 immediately before S. Such a technique is an important technique to consider when creating a subroutine, because the value of the register used in the main routine is destroyed during the execution of the subroutine, and restoration is impossible when returning to the main routine by the return instruction. The value of the register that needs to be saved at the beginning of the subroutine is temporarily saved in the memory so that it does not happen. Processing returns.

[0009]

In the conventional microcomputer, the value of the general-purpose register is saved in the memory every time the processing of the program moves from the main routine to the subroutine or from the subroutine to the main routine.
Since it is necessary to execute the instruction code that restores the memory value to the general-purpose register, the number of steps in the subroutine becomes longer accordingly. Furthermore, when adding or deleting a global register that can be used as the same register number in the subroutine and the main routine in the subroutine, it is necessary to add or delete the instruction code of the subroutine each time according to the number of global registers. Therefore, there is a problem that it requires the labor and time of the programmer.

The present invention has been made in view of the above problems, and when a general register in a register file is used in a subroutine and a main routine, the register number of the general register is changed between the subroutine and the main routine. By doing so, an object of the present invention is to provide a microcomputer that does not require an instruction code for saving the value of the general-purpose register in the memory and an instruction code for restoring the value of the memory in the general-purpose register. Furthermore, by configuring so that the number of general-purpose registers that can be used as global registers in the general-purpose register group in the subroutine and the main routine can be increased or decreased, the global registers used in the subroutine can be added or deleted. It is an object of the present invention to provide a microcomputer in which it is not necessary to add or delete the instruction code according to.

[0011]

A microcomputer according to a first aspect of the present invention adds first information stored in a first storage means and second information included in an instruction code by using an addition means. Then, after sending the addition result to the decoder, the decoder is used to select the register for reading or writing data. In the microcomputer according to the second aspect, the addition means adds the second information included in the instruction code and the third information stored in the second storage means by the comparison means. Had first and second
The result of addition of the information or the second information is selected, and after the selected information is sent to the decoder, the register to be read or written using the decoder is selected.

[0012]

According to the first aspect of the invention, the second information as the general-purpose register number of the instruction code is added to the first information for storing the information of the access starting point by using the adding means. Information is changed to information indicating a general-purpose register number different from the general-purpose register number, so that the general-purpose register selected by the decoder can be changed by using the adding means. Therefore, if you do not want to use the general-purpose register used in the main routine in the subroutine, save the value of the general-purpose register in the memory by executing the instruction to change the general-purpose register number using the adding means at the beginning of the subroutine. , It becomes unnecessary to restore the value stored in the memory to the general-purpose register.

According to the second aspect of the invention, the comparison means is used to compare the second information as the general-purpose register number of the instruction code or the value obtained by adding the first information to the second information using the addition means. Is selected and sent to the decoder,
The decoder can select a register by using the added value, and can select a register for reading and writing by using the second information itself without adding the first information to the second information. it can. Therefore, when the second information is greater than or equal to the third information indicating the number of global registers, the second information is sent to the decoder to send the second information to the same general-purpose register number in the subroutine and the main routine. Can be used as the number of a global register having. Further, when the second information is smaller than the third information, the addition result of the first and second information is sent to the decoder and the second information is used as a general-purpose register having different general-purpose register numbers in the subroutine and the main routine. It can be used as a register number.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments thereof. 1 and 2 are block diagrams showing a microcomputer of the present invention. In the figure, reference numeral 23 is a bus interface unit (hereinafter referred to as BIU) which controls the external data bus 80 and the external address bus 81 to read and write data from a memory (not shown). The BIU 23 is connected via an internal bus 24 to a data register 5 used for memory reference and an instruction register 25 for storing an instruction code. The instruction register 25 is connected to an immediate value offset register 26 that stores immediate value data or offset data extracted from the instruction code, and the immediate value offset register 26 is connected to the internal bus 2. The instruction register 25 is a decoder for designating a control circuit 27 for controlling a microcomputer in accordance with an instruction word indicated by a program and a general register in the general register group 4 as a register file and a data register 5 for reading and writing. 9 is connected.

The decoder 9 is connected to the general purpose register group 4 and the data register 5. The general-purpose register group 4 and the data register 5 send the contents of these registers to the internal bus 1 and the internal bus 2, respectively.
It is connected to each of the second buffers 7. The first buffer 6 is connected to the internal bus 1 and the second buffer 7
Is connected to the internal bus 2. The first latch circuit 12 connected to the internal bus 2 in order to take in the data on the internal bus 2 has an output terminal which is the first latch circuit 12 further.
Is connected to the input terminals of the evaluation registers 10 and 11 to evaluate the value stored in the, and the output terminals of the evaluation registers 10 and 11 temporarily store the values of the evaluation registers 10 and 11 or the internal buses 2 and 1.
Is input to the input terminals of the second latch circuit 13 and the third latch circuit 14. The output terminals of the second latch circuit 13 and the third latch circuit 14 are connected to the input terminal of the ALU 15 that executes arithmetic logic operation, and the output terminal of the ALU 15 together with the output terminal of the third latch circuit 14 is an evaluation register. It is connected to 10,11. Furthermore, the output terminal of ALU 15 is connected to the input terminal of register 16 which temporarily stores the value of ALU 15.

The output terminal of the register 16 is connected to the internal bus 1 and the internal bus 2, and the output terminal of the register 16 is connected via the internal bus 3 to the general-purpose register in the general-purpose register group 4 or the data register 5 to the internal bus 3. The write circuit 8 is connected to the input terminal of the write circuit 8 for writing the above data.
The output terminal of is connected to the input terminals of the general-purpose register group 4 and the data register 5. The output terminal of the register 16 stores the address of the next instruction code to be executed Next P
It is connected to the input terminal of a rogram Counter (hereafter NPC) 19. The output terminal of the NPC 19 is connected to the input terminal of the program counter 17 that stores the address of the instruction code currently executed, and the output terminal of the program counter 17 is the value of the program counter 17 +2 It is connected to the input terminal of the adder 18 in order to obtain the stored address, and the output terminal of the adder 18 is in NPC 19 to temporarily store the address to be executed next obtained in the adder 18.
Is connected to the input terminal of.

The output terminal of the program counter 17 is connected to the internal bus 2 and the internal bus 3, and the output terminal of the program counter 17 is an input terminal of a fourth latch circuit 21 for temporarily storing the value of the program counter 17. It is connected to the. The output terminal of the fourth latch circuit 21 is connected to the input terminal of the exception address register 22 that holds the address when the interrupt occurs or the exception occurs,
22 output terminals are connected to the internal bus 3. The ALU
The output terminal of 15 is connected to the input terminal of the MA register 20 that temporarily stores the address of the memory (not shown) calculated by the ALU 15, and the output terminal of the MA register 20 is connected to the BIU 23 to transfer the address to the memory (not shown). Then, the BIU 23 evaluates the data in the memory (not shown) in the evaluation register 10,1.
Connected to 1. The circles in the figure are electric switches such as transfer gates and buffers, and all the electric switches are connected to a control circuit 27 that controls connection or non-connection of the electric switches.

The operation of this microcomputer will be described below. The instruction word used in the microcomputer of the present invention is executed by using an instruction code decoding section and a two-stage pipeline consisting of the first ten. The decoding unit of the pipeline transfers the instruction code read from the memory (not shown) by the BIU 23 to the instruction register 25 via the internal bus 24. The instruction code of the instruction register 25 is simultaneously transferred to the decoder 9, the immediate offset register 26, and the control circuit 27, and the decoder 9 selects the general register or the data register 5 in the general register group 4, and the control circuit 27 outputs the instruction code. And the operation of extracting the immediate data and the offset data from the instruction code by the immediate offset register 26 are simultaneously performed in parallel. Note that the register selection operation by the decoder 9 is performed by register fields R _X and R _Y describing the register number in the instruction code.
Is performed using. First by register field R _X
The register that transfers the data to the buffer 6 of is selected,
Further, a register for transferring data to the second buffer 7 is selected by the register field R _Y.

The operation indicated by the execution unit of the pipeline differs depending on the instruction word. The operation of the execution unit of the pipeline during the execution of the main instruction word will be specifically described below. (1) LDD R _X, read out the values of # n the operation of the execution unit of the pipeline is started in synchronism with the rising edge of the synchronous clock signal input to the microcomputer of the present invention the first buffer 6 Then, the value of the immediate offset register is transferred to the third latch circuit 14 via the internal bus 1 and stored in the third latch circuit 14, and at the same time, the value of the immediate offset register is transferred via the internal bus 2 to the first latch circuit.
The value read from the first latch circuit 12 is transferred to and stored in the evaluation register 12 in synchronization with the fall of the clock signal. At the same time, the value read from the second latch circuit 14 is transferred to and stored in the evaluation register 11.

(2) FLD (FUNC1), R _{Y When} the operation of the execution unit of the pipeline is started in synchronization with the rising edge of the synchronizing clock signal, the value of the second buffer 7 is read out and the internal bus is read. 1 through the first latch circuit 12
The value of the evaluation register 10 is read in parallel with the operation of being transferred to and stored in the first latch circuit 12 and transferred to the second latch circuit 13 and stored in the second latch circuit 13 and simultaneously. The value of the evaluation register 11 is read out, transferred to the third latch circuit 14, and stored in the third latch circuit 14.
The ALU 15 determines the value of the second latch circuit 13 and the third value based on the instruction of arithmetic logic operation described in FUNC1 in the instruction code.
A predetermined operation is performed between the value of the latch circuit 14 and the value of the latch circuit 14, and the execution result is obtained at the fall of the synchronization clock signal.
Is transferred to and stored.

(3) FST (FUNC1), When the operation of the execution unit of the R _Z pipeline is started in synchronization with the rising edge of the clock signal, the value of the evaluation register 10 is read out and the second latch circuit is read. In parallel with the operation of being transferred and stored in 13 and the value of the evaluation register 11 being read and transferred to the third latch circuit 14 and being stored in the third latch circuit 14, the ALU 15 has an instruction code Second latch circuit 13 based on the instruction of arithmetic logic operation described in FUNC1
A predetermined operation is executed between the value of the above and the value of the third latch circuit 14, and the operation result is transferred to the register 16 and stored in the register 16 at the falling edge of the synchronizing clock signal. The calculation result is sent to the internal bus 3 in synchronization with the rising of the next clock signal that newly occurs after the clock signal disappears, and the value on the internal bus 3 is fetched and stored in the write circuit 8 to be stored in the write circuit. The value of 8 is transferred to the designated general purpose register in the general purpose register group 4 or the data register 5.

(4) JCN (FUN4), OFF When the operation of the execution unit of the pipeline is started in synchronization with the rising edge of the synchronizing clock signal, the value of the evaluation register 10 is read out and the second latch is read. The value of the evaluation register 11 is read in parallel with the operation of being transferred to and stored in the circuit and transferred to and stored in the third latch circuit 14. ALU 15
Executes a predetermined operation between the value of the second latch circuit 13 and the value of the third latch circuit 14 based on the instruction of the type of arithmetic logic operation described in FUN1 in the instruction code, and the operation result Is transferred to the register 16 and stored in the register 16 in synchronization with the falling edge of the synchronizing clock signal. The value of the program counter 17 is set to the internal bus in parallel with the operation of judging whether the value of the register 16 is 0 or not in synchronization with the rising of the next clock signal newly generated after the synchronizing clock signal disappears. After being transferred to the third latch circuit 14 via 1 and then stored in the third latch circuit 14, the value of the immediate offset register 26 is transferred to the second latch circuit 13 via the internal bus 2 Stored in the second latch circuit 13, the ALU 15 adds the value of the second latch circuit 13 and the value of the third latch circuit 14 to obtain the addition result.

Only when the judged value is not 0, the addition result obtained by the ALU 15 in synchronization with the rising edge of the next synchronizing clock signal newly generated after the synchronizing clock signal disappears is the synchronizing clock signal. Is transferred to the register 16 and stored in the register 16 at the falling edge of, and further transferred to the BIU 23 and stored in the BIU 23. The value of register 16 is transferred to NPC 19 in parallel with the operation of BIU 23 accessing an instruction from a memory (not shown) in synchronization with the next rising edge of the next synchronizing clock signal generated after the synchronizing clock signal disappears. Are stored in the NPC 19, and the value of the NPC 19 is read in synchronization with the falling edge of the synchronization clock signal, transferred to the program counter 17, and stored therein. If the determined value is 0, the value added in ALU 15 is discarded,
The added value is not used for other circuits.

(5) When the operation of the MOV R _X , R _Z pipeline execution unit is started in synchronization with the rising edge of the synchronizing clock signal, the value read from the second buffer 7 is transferred to the internal bus. Is transferred to the second latch circuit 13 via 2 and stored in the second latch circuit 13,
The value of the second latch circuit 13 and the third latch circuit preset to 0 are synchronized with the falling edge of the synchronizing clock signal.
The value of 14 and the value of 14 are added by using the ALU 15, transferred to the register 16, and stored in the register 16. The value of the register 16 is written to the write circuit via the internal bus 3 in synchronization with the rising edge of the clock signal newly generated after the synchronization clock signal disappears.
It is transferred to 26 and stored in the write circuit 26, and the value of the write circuit 26 is transferred to and stored in the designated general-purpose register or data register 5.

(6) RDM R _X , OFF When the operation of the execution unit of the pipeline is started in synchronization with the rising of the synchronizing clock signal, the value read from the first buffer 6 is transferred to the internal bus 1 The value read from the immediate value offset register 26 is transferred to the second latch circuit 13 via the internal bus 2 at the same time as the operation stored in the second latch circuit 13. It is transferred to the latch circuit 14 and stored in the third latch circuit 14. The ALU 15 adds the value of the second latch circuit 13 and the value of the third latch circuit 14 in synchronization with the fall of the synchronization clock signal, and the addition result is transferred to the MA register 20 and the MA register 20 Stored in. The value of the MA register 20 is transferred to the BIU 23 as address information in synchronization with the rising edge of a new synchronization clock signal that occurs after the synchronization clock signal disappears, and the BIU 23 is transferred to a memory (not shown) via the external address bus 81. The address information is transferred, a memory (not shown) reads the stored instruction code according to the address transferred from the BIU 23, and sends the instruction code to the external data bus 80.
U 23 takes in the instruction code on the external data bus 80 and transfers it to the instruction register 25.

[0026] (7) WRM R _X, when the operation of the execution unit of the OFF pipeline is started in synchronization with the rising edge of the synchronous clock signal, the value read from the first buffer 6 internal bus 1 The value read from the immediate offset register 26 at the same time as the operation of being transferred to the third latch circuit 14 and stored in the third latch circuit 14 through the second latch via the internal bus 2. It is transferred to the circuit 13 and stored in the second latch circuit 13. The ALU 15 adds the value of the second latch circuit 13 and the value of the third latch circuit 14 to obtain the addition result, and the ALU 15 synchronizes the addition result with the MA register in synchronization with the fall of the synchronizing clock signal. 20 and the MA register 20 stores the addition result. The value of the MA register 20 and the value of the data register 5 are transferred to the BIU 23 in synchronization with the rising edge of a new synchronizing clock signal that occurs after the synchronizing clock signal disappears, and the BIU 23 changes the value of the MA register 20. The data is transferred to the external address bus 81 and the value of the data register 5 is sent to the external data bus 80.

(8) When the operation of the execution unit of the JMP OFF pipeline is started in synchronization with the rising edge of the synchronizing clock signal, the program counter
The value of 17 is read out, transferred to the third latch circuit 14 via the internal bus 1, and stored in the third latch circuit 14. At the same time, the value of the immediate offset register 26 is read out. Are transferred to the second latch circuit 13 via the internal bus 2 and stored in the second latch circuit 13. The ALU 15 has the second latch circuit 13 in synchronization with the falling edge of the synchronization clock signal.
Value and the value of the third latch circuit 14 are added to obtain an addition result, and the addition result is transferred to and stored in the register 16 and BIU 23. The register 16 is synchronized with the rising edge of a new synchronizing clock signal generated after the synchronizing clock signal disappears.
The value of BIU 23 is read out and transferred to NPC 19 and stored in NPC 19 at the same time as the value of BIU 23 is transferred to the memory (not shown) as address information, and the instruction code is read from the memory (not shown). Then, the value of the NPC 19 is transferred to the program counter 17 and stored in the program counter 17 in synchronization with the falling edge of the synchronizing clock signal.

(9) When the operation of the execution unit of the ALL _RY pipeline is started in synchronization with the rising edge of the clock signal, the information of the starting point of access of the general-purpose register group 4 existing in the decoder 9 is stored. The contents of the pointer 30 being read are read out via the internal bus 1 to the third
Value of the second buffer 7 is read in parallel with the operation of being transferred to the latch circuit 14 and stored in the third latch circuit 14 and transferred to the second latch circuit 13 via the internal bus 2. It is stored in the second latch circuit 13. In synchronization with the falling edge of the synchronization clock signal, the ALU 15 is connected to the third latch circuit 14
Is subtracted from the value of the second latch circuit, and the subtraction result is transferred to the register 16 and stored in the register 16.
The value of the register 16 is read in synchronization with the falling edge of a new synchronizing clock signal that occurs after the synchronizing clock signal disappears, and is transferred to the pointer 30 via the internal bus 3 and stored therein.

(10) The FRE _RY ALL _RY instruction instructs the ALU 15 to perform subtraction when the operation of the value of the second latch circuit 13 and the value of the third latch circuit 14 is executed. Instructs ALU 15 to add. Except for this point, the ALL _RY instruction and the instruction operate in the same manner, and therefore the description of the instruction is omitted.

FIG. 3 is a detailed block diagram of the decoder 9 of FIGS. In the figure, 30 is a pointer as a first storage means for storing first information indicating the starting point of access to the general-purpose register group 4. The pointer 30 and the signal line 31 (or 32) carrying the complementary signal of the register field R _X (or R _Y ) in the instruction code are connected to the input terminal of the adder 33 (or 34). An output terminal of the adder 33 (or 34) is connected to the input terminal of the R _X-decoder 45 to provide the addition result (or R _Y decoder 46), an output terminal signal of R _X decoder 45 (or R _Y decoder 46) Is the first buffer 6
(Or the second buffer 7) In order to select a register for transferring data, it is given to the general-purpose register group 4 and the data register 5.

The output terminal of the adder 33 (or 34) is connected to the input terminal of the fifth latch circuit 35 (or sixth latch circuit 36) for temporarily latching the addition result.
The output terminal of the fifth latch circuit 35 (or the sixth latch circuit 36) is connected to the input terminal of the ninth latch circuit 37. The output terminal of the ninth latch circuit 37 is the tenth latch circuit.
Connected to 38 input terminals. The output terminal of the tenth latch circuit 38 is connected to the input terminal of the R _Z decoder 47. The output signal of the R _Z decoder 47 is given to the general-purpose register group 4 and the data register 5 for selecting the register to transfer the data of the write circuit 8 from the general-purpose register group 4 and the data register 5. The detection circuit 39 (or 40) connected to the signal line 31 (or 32) is
(Or 32), when a signal designating the data register 5 is detected, the data from the general-purpose register group 4 and the data register 5 is sent to the R _X decoder 45 (or R _Y decoder 46) and the R _Z decoder 47. A signal is sent to select the register 5. Further, the output terminal of the detection circuit 39 (or 40) is connected to the input terminal of the R _X decoder 45 (or R _Y decoder 46). The output terminal of the detection circuit 39 (or 40) is a seventh latch circuit 41 for temporarily latching its output.
(Or is connected to the input terminal of the eighth latch circuit 42).

The output terminal of the seventh latch circuit 41 (or the fifth latch circuit 35) and the output terminal of the eighth latch circuit 42 (or the sixth latch circuit 36) serve as a signal delay means for the eleventh latch circuit. 43 (or ninth latch circuit 37) connected to the input terminal of the eleventh latch circuit 43 (or ninth latch circuit 37)
The output terminal of 37) is connected to the input terminal of the 12th latch circuit 44 (or the 10th latch circuit 38) as the signal delay means, and the output of the 12th latch circuit 44 (or the 10th latch circuit 38). The terminal is connected to the input terminal of the R _Z decoder 47. 5th, 6th, 7th, 8th, 9th, 10th, 11th
And the twelfth latch circuits 35, 36, 41, 42, 37, 38, 43 and 44 send the value of the signal lines 31, 32 or the value of the addition result of the adder 33 or 34 to the R _Z decoder 47. It is a signal delay means for

The ninth latch circuit 37 and the eleventh latch circuit 43
Latches data at the rising edge of the synchronizing clock signal.
A fifth latch circuit 35, a sixth latch circuit 36, a seventh latch circuit 41, an eighth latch circuit 42, a tenth latch circuit 38,
The twelfth latch circuit 44 latches data at the falling edge of the synchronizing clock signal. The circles in the figure are electrical switches such as transfer gates and buffers,
All electrical switches are connected to a control circuit 27 which controls their connection or disconnection.

There are 32 general-purpose registers in the general-purpose register group 4, and serial numbers R0, R1, R2, R3 ... R31 are assigned to the 32 general-purpose registers as register numbers 0 to 31, respectively. The register fields R _X and R _Y indicating the register number in the instruction code are each composed of 4 bits, so that the register number can be specified from 0 to 15. Further, when the register number 0 is designated in the register field R _X (or R _Y ), the R _X decoder 45 (or R _Y decoder 4
6) and the R _Z decoder 47 designates the data register 5. It is now assumed that the pointer 30 stores a numerical value of "16". When the register field R _X (or R _Y ) specifies "15", "15" becomes a binary number "1111", and the signal line 31 ( Or 32) becomes "0000", that is, the numerical value {circle around (0)}. Therefore, the adder 33 (or 34) adds the numerical value {circle around (16)} and the numerical value {circle around (0)} to obtain the numerical value {circle around (16)}. The R _X decoder 45 (or R _Y decoder 46) selects the general register of R16 in the general register group 4 by using.

Next, the data stored in the OFF1 address and the OFF2 address of the memory (not shown) are added and the addition result is R11.
A method of describing the program stored in the above as a subroutine will be described with reference to FIGS. FIG. 4 is a program list of this processing, and FIG. 5 is a flowchart of the program of FIG. When the subroutine shown in FIG. 4 is executed, the trigger for using the subroutine is known in advance by the subroutine call instruction, and the subroutine is used by the interrupt signal from the outside of the microcomputer. Sometimes it is unknown to be used. Here, the general-purpose registers R13, R14, and R15 are prepared as general-purpose registers that can always be used in the subroutine in any of the above cases.

In FIG. 5, the value of the pointer 30 for storing the information of the access starting point is set to 3 by using the instruction code of ALL # 3.
And the general register number selected by the R _X decoder 45 (or the R _Y decoder 46) is decreased by 3. At this time, the value of pointer 30 has been reduced from 16 "to 13", so general register R13, R14 and
R15 remains the same after decrementing the value of pointer 30 by 3, R13, R1
4 and R15 can be used as a combination, so that R13, R14 and R15 can be reserved as a combination of working registers having the same register number (S1).
Next, the value of data register 5 is saved in R13 using the instruction code of MOV DATA, R13 (S2), and the value of R14 is MOV # 0, R14.
Clear using the instruction code of (S3), read the data of the OFF1 address using the instruction code of RDM R14, OFF1 and transfer it to the data register 5 (S4), and move the value of the data register 5 to MOV.
Saved to general-purpose register R15 using the instruction code of DATA and R15 (S5), read the data at the OFF2 address using the instruction code of RDM R14 and OFF2, and transfer it to data register 5 (S6). LDD (A
It is stored in the general-purpose register R11 using the instruction code of DD) and R11 (S7), and the value of the general-purpose register R13 is restored to the data register 5 using the instruction code of MOV R13, DATA (S8). Then, the value of the pointer 30 is set to 3 using the instruction code of FRE # 3.
R13, R14 and R1 by increasing the general register number selected by R _X decoder 45 or R _Y decoder 46
An instruction code indicating the return instruction by releasing 3 of 5 (S9)
Return from the subroutine to the main routine using RET (S
Ten) .

As described above, the data register 5, general-purpose registers R13, R14 and
Since the process of saving the value of the register of R15 in the memory is unnecessary, the microcomputer of the present invention can perform the process at a high speed when executing the subroutine as compared with the conventional microcomputer. In addition, the general registers of R13, R14, and R15 are all
It was secured and released using the instruction code of FRE # 3.
Numerical value of instruction code of ALL # 3 and FRE # 3 ■ 3 "to ■ 4"
Since more general-purpose registers can be secured when the above numerical values are changed, when adding or decreasing general-purpose registers used as working registers in a subroutine, the number of general-purpose registers to be added or decreased is changed accordingly. There is no need to add or reduce the instruction code of the subroutine, and the labor and time of the programmer can be saved.

FIG. 6 is a block diagram showing another embodiment of the decoder 9 shown in FIGS. In the figure, 94 is a register as a second storage means for storing the number of usable global registers as third information. Now, it is assumed that there are four global registers that can be used. Then, (4) becomes a binary number "0100", and the complementary signal "1011" is stored in the register 94. 31 (or 3
2) is a signal line on which a complementary signal of the value of the register field R _X (or R _Y ) in the instruction code is carried as the second information.

The comparator circuit 390 (or 400) is connected to the signal line 31 (or 3).
Compare the value of 2) with the constant "1011", and then use the signal line 31 (or 32).
When the value of 2 is smaller than the constant "1011", it is connected to the switch 90 (or 92) to output the signal 0 "and turn off the electric switch 90 (or 92), and the electric switch 91 (or 93). Is connected to the input terminal of the inverting circuit 48 (or 49), and the output terminal of the inverting circuit 48 (or 49) is connected to the switch 91 (or 93).
One end of (or 91 and 93) is connected to the terminal (or the output terminal of pointer 30) which is signal 0 ", and the other end is connected to the input terminal of adder 33 (or 34) by signal line 31 (or 32). Is connected with.

The adder 33 (or 34) is a switch 90 (or 9
2) Or adder 33 via switch 91 (or 93)
(Or 34) and the value of the register 94 or the value of the pointer 30 and the value of the signal line 31 (or 32) input to the R _X decoder 45 (or R _Y decoder 46) and the fifth addition result. It is connected to the latch circuit 35 (or the sixth latch circuit 36) for output. Except for these circuits, the circuit of the block diagram of FIG. 6 is the same as the circuit of the block diagram of FIG. 3, and the same reference numerals are given to omit the description.

The operation will be described below. Signal line 31 (or 3
When the value of 2) is greater than or equal to the value of the register 94, the comparison circuit 39 (or 40) turns on the electric switch 90 (or 92) and turns off the electric switch 91 (or 93). (Or 34) on signal line 31 (or 32) and constant ■ 0 "
And are entered. The adder 33 (or 34) is connected to the signal line 31 (or
32) and the constant {circle around (0)} are added, and the addition result is obtained by the R _X decoder 45 (or R _Y decoder 46) or the fifth (or sixth).
Latch circuit 35 (or 36), ninth latch circuit 37,
It is sent to the R _Z decoder 47 via the latch circuit 38. R
_X decoder 45 (or R _Y decoder 46) or R _Z decoder
47 selects a general-purpose register corresponding to the addition result in the general-purpose register group 4 as a global register according to the addition result.

When the value of the signal line 31 (or 32) is smaller than the value of the register 94, the comparison circuit 39 (or 40) turns off the electric switch 90 (or 92) and turns on the electric switch 91 (or 93). Therefore, adder 33 (or 34) to signal line 31 (or 3
2) and the value of pointer 30 are input. Adder 39 (or 4
0) adds the value of the signal line 31 (or 32) and the value of the pointer 30, and the addition result is the R _X decoder 45 (or R _Y decoder 4).
6) Or, or 5th (or 6th) latch circuit 35 (or 36)
, Through the ninth latch circuit 37 and the tenth latch circuit 38 to the R _Z decoder. The R _X decoder 45 (or R _Y decoder 46) or R _Z decoder 47 selects a general-purpose register corresponding to the addition result in the general-purpose register group 4 according to the addition result.

Now, the register field R of the instruction code
_X (or R _Y ) is a binary number “0011” (register number 3)
Shall be At that time, the value of the signal line 31 (or 32) becomes "1100" which is a complementary signal of "0011". Therefore, the detection circuit 390 (or 400) compares the value "1100" of the signal line 31 (or 32) with the constant "1011" of the register 94, and as a result, the former value is larger than the latter constant. Via electrical switch 90 (or 92) and inverting circuit 48 (or 49) to electrical switch 91 (or 93), so that electrical switch 90 (or 92) is on and electrical switch 91 (or 93).
Since turned off, the adder 33 (or 34) is "adds the numerical result of addition ■ 12" and the value of the signal line 31 (or 32) "1100" Numerical ■ 0 is R _X decoder 45 (or _RY decoder 4
6) is transferred to the R _Z decoder 47, and the R _X decoder 45 (or the R _Y decoder 46) and the R _Z decoder 47 select the general purpose register R12 from the general purpose register group 4 using the addition result.

Therefore, when the value of the register field R _X (or R _Y ) is a binary number "0011" (register number 3), the general register R12 can be used as a global register. Further register field R _X
If the value of (or R _Y ) is the binary number “0010” (register number 2) or “0001” (register number 1),
The complementary signal "1011", "1101" or "1110" is smaller than or equal to the value of the register 94, and therefore is not changed and is not changed by the R _X decoder 45 (or R _Y decoder 46) or the R _Z decoder 47. Transferred to general purpose registers R11, R12, R13 and
R14 can be used as a global register.

Further, the constant "1011" stored in the register 94
Can be changed to another constant to change the number of general-purpose registers used as global registers in the general-purpose register group 4. Therefore, general-purpose registers R11, R12, R13 and R1 are used in the subroutine and main routine.
Register 94 when using 4 as a working register
By setting the value of "1011" to the general-purpose register R11
, R12, R13 and R14 can be used as global registers whose register numbers do not change. At this time, the general-purpose registers except general-purpose registers R11, R12, R13, and R14 are ordinary general-purpose registers that cannot be used as global registers.

FIG. 7 is a block diagram showing another embodiment of the decoder 9. In the figure, the output terminal of the general-purpose register 53 in the general-purpose register group 4 is connected to the input terminal of the comparison circuit 390 (or 400). Except for this, the circuit of the block diagram of FIG. 7 is the same as the circuit of the block diagram of FIG. 6, and the same reference numerals are given to omit the description.

The operation of the block diagram of FIG. 7 will be described below. A constant is set in the general-purpose register 53 using an instruction code such as MOV #n, R _Z (sets a constant n in the general-purpose register R _Z ). Now register field R _X (or R
_If the value of signal line 31 (or 32), which is the complementary signal of _Y ), is greater than or equal to the value of general register 53, a comparison circuit
390 (or 400) outputs signal 1 "and electric switch 90
(Or 92) is turned on, the adder 33 (or 34) turned off so that the electrical switch 91 (or 93) by adding a constant ■ 0 "to the signal line 31 (or 32) R _X decoder 45 (or R _Y decoder
46) Or, send it to the R _Z decoder 47. At this time, the R _X decoder 45 (or the R _Y decoder 46) or the R _Z decoder 47 selects the global register.

On the other hand, when the value of the signal line 31 (or 32) is smaller than the value of the general-purpose register 53, the comparison circuit 390 (or 400) outputs the signal {circle around (1)} "and the electric switch 90 (or 92) is turned off. Then, the electric switch 91 (or 93) is turned on.
33 (or 34) adds the value of the pointer 30 to the signal line 31 (or 32) and adds the value to the R _X decoder 45 (or R _Y decoder 46) or R
_It is sent to the _Z decoder 47. At this time, the R _X decoder 45 (or R _Y decoder 46) or R _Z decoder 47 selects a general-purpose register.

Now, let us say that the set value of the general-purpose register 53 is "1100". Value of register field R _X (or R _Y ) "000
1 ”,“ 0010 ”or“ 0011 ”complementary signals“ 1110 ”,“ 1 ”
Only when 101 or 1100 is placed on the signal line 31 (or 32), the value of the signal line 31 (or 32) is greater than or equal to the value of the general-purpose register 53, so the complementary signals “1110” and “110
1 ”or“ 1100 ”is the R _X decoder 45 (or R _Y decoder 4
6) or to the R _Z decoder 47, so that the R _X decoder 45 (or the R _Y decoder 46) is the general purpose registers R14, R13.
Or, select three of R12 as global registers.

As described above, since the number of global registers of the general-purpose register 53 can be set by the instruction code, when the global register is used as the working register and the global register is used as the stack memory, the global register is set to the global register. The number of registers can be set freely. Therefore, the number of global registers does not become insufficient, and it is not necessary to save the general-purpose register value in the memory, and the program can be simplified and speeded up.

[0051]

As described above, according to the first aspect of the present invention, the register selected by the decoder is selected by adding the first information regarding the register number to the second information regarding the register number included in the instruction code by using the adding means. Can be changed. Therefore, an instruction code for saving the value of the register in the memory becomes unnecessary, and the subroutine program can be simplified and speeded up.

Furthermore, in the second invention, the number of usable global registers can be changed by changing the third information stored in the second storage means. Therefore, it becomes unnecessary to add or delete the instruction code each time the number of global registers is increased or decreased.
The program can be simplified and speeded up. In both the first and second inventions, it is not necessary to add or delete the instruction code according to the number of registers used in the program, so that the labor and labor of the programmer can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a microcomputer of the present invention.

FIG. 2 is a block diagram showing a microcomputer of the present invention.

3 is a detailed block diagram of the decoder 9 of FIG.

FIG. 4 is a list shown as an example of a program of the microcomputer of the present invention.

5 is a flow chart of the program of FIG.

FIG. 6 is a block diagram showing another embodiment of the decoder 9 of FIG.

FIG. 7 is a block diagram showing another embodiment of the decoder 9 of FIG.

FIG. 8 is a block diagram showing a conventional microcomputer.

FIG. 9 is a schematic diagram of a general-purpose register of a conventional microcomputer.

FIG. 10 is a flowchart as an example of a program of a conventional microcomputer.

11 is a list of programs of the flowchart in FIG.

[Explanation of symbols]

4 general purpose register set 5 data register 9 decoder 30 pointer 33 adders 39 and 40 detection circuit 45 R _X-decoder 46 R _Y-decoder 47 R _Z decoder 48 and 49 inverting circuit 390 and 400 comparing circuit

[Procedure amendment]

[Submission date] June 16, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

[0011]

A microcomputer according to a first aspect of the present invention adds first information stored in a first storage means and second information included in an instruction code by using an addition means. Then, after sending the addition result to the decoder, the decoder is used to select the register for reading or writing data. In the microcomputer according to the second aspect, the addition means adds the second information included in the instruction code and the third information stored in the second storage means by the comparison means. Had first and second
The result of addition of the information of or the constant added by the adding means and the second
The result of addition of the information is selected, the selected information is sent to the decoder, and then the decoder is used to select the register for reading or writing.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

[0012]

[Action] In the first invention, les having instruction code
Second information by adding the first information storing starting point information of the accessed using the adding means and the second information as register number is changed to information indicating the general-purpose register number different from said register number Therefore, the general-purpose register selected by the decoder can be changed using the adding means. Therefore, the register used in the main routine
If you do not want to use the data in subroutine saves the value of the register by executing an instruction to change the general-purpose register number by using the adding means at the beginning of the subroutine in the memory, the register values stored in the memory There is no need to return to.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

In the second aspect of the invention, the addition means is used.
Then, either the value obtained by adding the constant and the second information as the register number of the instruction code or the value obtained by adding the first information to the second information by using the adding means is selected by using the comparing means. since sent to the decoder Te, the value which the decoder can select a general purpose register with a value obtained by adding said constant, and further adding the first information to the second information
You can use to select a general-purpose register for reading and writing. Therefore, when the second information is greater than or equal to the third information indicating the number of global registers, the addition result of the constant and the second information is sent to the decoder and the second information is subroutined. And the main routine can be used as a global register number having the same general-purpose register number. Further, when the second information is smaller than the third information, the addition result of the first and second information is sent to the decoder, and the second information is a register having different general register numbers in the subroutine and the main routine. Can be used as a number.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

The operation of this microcomputer will be described below. The instruction word used in the microcomputer of the present invention is executed by using a two-stage pipeline including an instruction code decoding unit and an execution unit . The decoding unit of the pipeline transfers the instruction code read from the memory (not shown) by the BIU 23 to the instruction register 25 via the internal bus 24. The instruction code of the instruction register 25 is simultaneously transferred to the decoder 9, the immediate offset register 26, and the control circuit 27, and the decoder 9 selects the general register or the data register 5 in the general register group 4, and the control circuit 27 outputs the instruction code. And the operation of extracting the immediate data and the offset data from the instruction code by the immediate offset register 26 are simultaneously performed in parallel. Note that the register selection operation by the decoder 9 is performed by register fields L _X and L _Y which describe the register number in the instruction code.
Is performed using. First by register field L _X
The register that transfers the data to the buffer 6 of is selected,
Further, a register for transferring data to the second buffer 7 is selected by the register field L _Y.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

The operation indicated by the execution unit of the pipeline differs depending on the instruction word. The operation of the execution unit of the pipeline during the execution of the main instruction word will be specifically described below. (1) When the operation of the execution unit of the LDD L _X , #n pipeline is started in synchronization with the rising edge of the synchronization clock signal input to the microcomputer of the present invention, the value of the first buffer 6 is read out. Then, the value of the immediate offset register is transferred to the third latch circuit 14 via the internal bus 1 and stored in the third latch circuit 14, and at the same time, the value of the immediate offset register is transferred via the internal bus 2 to the first latch circuit.
The value read from the first latch circuit 12 is transferred to and stored in the evaluation register 12 in synchronization with the fall of the clock signal. At the same time, the value read from the second latch circuit 14 is transferred to and stored in the evaluation register 11.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

[0020] (2) FLD (FUNC1), L Y operation of the execution unit of the pipeline synchronously Once started the value of the second buffer 7 is read out by the rise of the synchronization clock signal internal bus 1 through the first latch circuit 12
The value of the evaluation register 10 is read in parallel with the operation of being transferred to and stored in the first latch circuit 12 and transferred to the second latch circuit 13 and stored in the second latch circuit 13 and simultaneously. The value of the evaluation register 11 is read out, transferred to the third latch circuit 14, and stored in the third latch circuit 14.
The ALU 15 determines the value of the second latch circuit 13 and the third value based on the instruction of arithmetic logic operation described in FUNC1 in the instruction code.
A predetermined operation is performed between the value of the latch circuit 14 and the value of the latch circuit 14, and the execution result is obtained at the fall of the synchronization clock signal.
Is transferred to and stored.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

(3) FST (FUNC1), When the operation of the execution unit of the L _Z pipeline is started in synchronization with the rising edge of the clock signal, the value of the evaluation register 10 is read out and the second latch circuit is read. In parallel with the operation of being transferred and stored in 13 and the value of the evaluation register 11 being read and transferred to the third latch circuit 14 and being stored in the third latch circuit 14, the ALU 15 has an instruction code Second latch circuit 13 based on the instruction of arithmetic logic operation described in FUNC1
A predetermined operation is executed between the value of the above and the value of the third latch circuit 14, and the operation result is transferred to the register 16 and stored in the register 16 at the falling edge of the synchronizing clock signal. The calculation result is sent to the internal bus 3 in synchronization with the rising of the next clock signal that newly occurs after the clock signal disappears, and the value on the internal bus 3 is fetched and stored in the write circuit 8 to be stored in the write circuit. The value of 8 is transferred to the designated general purpose register in the general purpose register group 4 or the data register 5.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

(5) When the operation of the MOV L _X , L _Z pipeline execution unit is started in synchronization with the rising edge of the synchronizing clock signal, the value read from the second buffer 7 is transferred to the internal bus. Is transferred to the second latch circuit 13 via 2 and stored in the second latch circuit 13,
The value of the second latch circuit 13 and the third latch circuit preset to 0 are synchronized with the falling edge of the synchronizing clock signal.
The value of 14 and the value of 14 are added by using the ALU 15, transferred to the register 16, and stored in the register 16. The value of the register 16 is written to the write circuit via the internal bus 3 in synchronization with the rising edge of the clock signal newly generated after the synchronization clock signal disappears.
It is transferred to 26 and stored in the write circuit 26, and the value of the write circuit 26 is transferred to and stored in the designated general-purpose register or data register 5.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

(6) RDM L _X , OFF When the operation of the execution unit of the pipeline is started in synchronization with the rising edge of the synchronizing clock signal, the value read from the first buffer 6 is transferred to the internal bus 1 Through the third latch times
The value read from the immediate offset register 26 in parallel with the operation stored in the third latch circuit 14 after being transferred to the path 14 is transferred to the second latch circuit 13 via the internal bus 2. , And are stored in the second latch circuit 13 . The ALU 15 adds the value of the second latch circuit 13 and the value of the third latch circuit 14 in synchronization with the fall of the synchronization clock signal, and the addition result is transferred to the MA register 20 and the MA register 20 Stored in. The value of the MA register 20 is transferred to the BIU 23 as address information in synchronization with the rising edge of a new synchronization clock signal that occurs after the synchronization clock signal disappears, and the BIU 23 is transferred to a memory (not shown) via the external address bus 81. The address information is transferred, a memory (not shown) reads the stored value according to the address transferred from BIU 23 , and
The value is sent to the external data bus 80, and the BIU 23 takes in the instruction code on the external data bus 80 and transfers it to the data register 5 .

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

(7) When the operation of the execution unit of the WRM L _X , OFF pipeline is started in synchronization with the rising edge of the synchronizing clock signal, the value read from the first buffer 6 is transferred to the internal bus 1 The value read from the immediate offset register 26 at the same time as the operation of being transferred to the third latch circuit 14 and stored in the third latch circuit 14 through the second latch via the internal bus 2. It is transferred to the circuit 13 and stored in the second latch circuit 13. The ALU 15 adds the value of the second latch circuit 13 and the value of the third latch circuit 14 to obtain the addition result, and the ALU 15 synchronizes the addition result with the MA register in synchronization with the fall of the synchronizing clock signal. 20 and the MA register 20 stores the addition result. The value of the MA register 20 and the value of the data register 5 are transferred to the BIU 23 in synchronization with the rising edge of a new synchronizing clock signal that occurs after the synchronizing clock signal disappears, and the BIU 23 changes the value of the MA register 20. The data is transferred to the external address bus 81 and the value of the data register 5 is sent to the external data bus 80.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction content]

(9) When the operation of the execution unit of the ALL _LY pipeline is started in synchronization with the rising edge of the clock signal, the information of the starting point of access of the general-purpose register group 4 existing in the decoder 9 is stored. The contents of the pointer 30 being read are read out via the internal bus 1 to the third
Value of the second buffer 7 is read in parallel with the operation of being transferred to the latch circuit 14 and stored in the third latch circuit 14 and transferred to the second latch circuit 13 via the internal bus 2. It is stored in the second latch circuit 13. In synchronization with the falling edge of the synchronization clock signal, the ALU 15 is connected to the third latch circuit 14
Is subtracted from the value of the second latch circuit, and the subtraction result is transferred to the register 16 and stored in the register 16.
The value of the register 16 is read in synchronism with the rising edge of a new synchronizing clock signal that occurs after the synchronizing clock signal disappears, and is transferred to the pointer 30 via the internal bus 3 and stored therein.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Name of item to be corrected] 0029

[Correction method] Change

[Correction content]

[0029] _{(10) FRE L Y ALL L} Y instruction is for instructing the subtraction on ALU 15 when executing the operation between the value and the value of the first latch circuit 14 of the second latch circuit 13, the instruction Instructs ALU 15 to add. Except for this point, the ALL _LY instruction and the instruction perform the same operation, and therefore the description of the instruction is omitted.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

Registers in general-purpose register group 4 are designated by Rn below.
Show. Rn is 31 from R30 to R0 (add data register 5
32) and L _{1 to} L ₁₅ are consecutive ₁₅ in Rn.
(L ₀ is always the data register 5). FIG. 3 is a detailed block diagram of the decoder 9 of FIGS. In the figure, 30 is a pointer as a first storage means for storing first information indicating the starting point of access to the general-purpose register group 4. Pointer 30 and register field in instruction code
Signal line 31 (or 32) carrying the complementary signal of L _X (or L _Y )
And are connected to the input terminal of the adder 33 (or 34). The output terminal of the adder 33 (or 34) is connected to the input terminal of the R _X decoder 45 (or R _Y decoder 46) to give the addition result, and the R _X decoder 45 (or R _Y decoder 46) is connected.
The output terminal signal of 1 is supplied to the general-purpose register group 4 and the data register 5 in order to select a register for transferring data to the first buffer 6 (or the second buffer 7).

[Procedure Amendment 14]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

The output terminal of the seventh latch circuit 41 and the eighth
An output terminal of the latch circuit 42 11 La as a signal delay means
11th latch circuit 43 connected to the input terminal of the switch circuit 43.
The output terminal of is a twelfth latch circuit 44 as a signal delay means.
Is connected to the input terminal, an output terminal <br/> twelfth latch circuit 44 is connected to an input terminal of R _Z decoder 47. Here, the fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth latch circuits 35, 36, 41, 42, 37, 38, 43 and 44 are signal lines 31, 32.
Value of R, the value of either of the addition results of the adder 33 or 34 is R _Z
It is a signal delay means for sending to the decoder 47.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction content]

There are 31 general-purpose registers in the general-purpose register group 4, and serial numbers R0, R1, R2 ... R30 are assigned to the 31 general-purpose registers as register numbers 0 to 30, respectively. Register field L indicating the register number in the instruction code
Each of _X and _LY is composed of 4 bits, so that the register number can be specified from 0 to 15. Further, when the register number 0 is designated in the register field L _X (or L _Y ) , the R _X decoder 45 (or R _Y decoder 46) and the R _Z decoder 47 designate the data register 5. It is now assumed that the pointer 30 stores a numerical value of 16 ". Register field R _X (or R _Y )
If you specify 15 ”, 15” will be “1111” in binary, and the signal line 31 (or 32) will be “0000”, that is,
0 ". Therefore, the adder 33 (or 34) has a numerical value of 16".
And the numerical value {circle around (1)} are added, and the numerical value {circle around (16)} obtained as a result of the addition is used for the R _X decoder 45 (or R _Y decoder
6) selects the general-purpose register of R16 in the general-purpose register group 4.

[Procedure Amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

Next, the data stored in the OFF1 address and the OFF2 address of the memory (not shown) are added, and the addition result is L11.
A method of describing the program stored in the above as a subroutine will be described with reference to FIGS. FIG. 4 is a program list of this processing, and FIG. 5 is a flowchart of the program of FIG.

[Procedure Amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

In FIG. 5, the value of the pointer 30 for storing the information of the access starting point is set to 3 by using the instruction code of ALL # 3.
And the general register number selected by the R _X decoder 45 (or the R _Y decoder 46) is decreased by 3. At this time, the value of pointer 30 has been reduced from 16 "to 13", so general register L13 (R18), L14
(R17) and L15 (R16) can be used as a combination of L13 (R15), L14 (R14) and L15 (R13) after decrementing the value of pointer 30 by 3, and thus R13, R14 and R15. Is poi
Have the same register number Ln before and after the value of
It can be secured as a combination of different general-purpose registers Rn (S1). Next, set the value of data register 5 to MOV DATA , L13
Save to general-purpose register R15 using the instruction code of (S2),
The value of general-purpose register R14 is cleared using the instruction code of MOV # 0 and L14 (S3), and the data of the OFF1 address is RDM L14, OFF1
Is read using the instruction code of No.1 and transferred to the data register 5 (S4), the value of the data register 5 is saved to the general-purpose register R13 using the instruction code of MOV DATA , L15 (S5), and the data at the OFF2 address is stored in the RDM. Read using the instruction code of R14, OFF2 and transfer to the data register 5 (S6).
Values and the LDD and the value of the general register R13 L15, DATA, TST (AD
D), stored in general-purpose register R17 using L11 instruction code
(S7), the value of the general-purpose register R15 is restored to the data register 5 using the instruction code of MOV L13, DATA (S8). Then, the value of the pointer 30 is set to 3 using the instruction code of FRE # 3.
Only increases, R _X decoder 45, or R _Y general register R13 by increasing the general-purpose register number decoder 46 selects
, R14 and R15 are released (S9), and the instruction code RET indicating the return instruction is used to return from the subroutine to the main routine (S10).

[Procedure 18]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Change

[Correction content]

As described above, the data register 5, registers L13, L14 and L15 in the subroutine are
Since it is not necessary to save the value of the register in the memory to the memory, the microcomputer of the present invention can perform the processing at a high speed when executing the subroutine as compared with the conventional microcomputer. Furthermore, in the relevant subroutine, the registers of L13, L14 and L15 are ALL # 3, FRE #
It was secured and released using the instruction code of 3, but ALL # 3,
If you change the numerical value of FRE # 3 instruction code (3) to (4) or more, more registers can be secured, so add or decrease the number of registers used as working registers in the subroutine. In this case, it is not necessary to add or reduce the instruction code of the subroutine each time according to the register to be added or reduced, and the labor and labor of the programmer can be omitted.

[Procedure Amendment 19]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

FIG. 6 is a block diagram showing another embodiment of the decoder 9 shown in FIGS. In the figure, 94 is a register as a second storage means for storing the number of usable global registers as third information. Now, it is assumed that there are four global registers that can be used. Then, (4) becomes a binary number "0100", and the complementary signal "1011" is stored in the register 94. 31 (or 3
2) is a signal line on which a complementary signal of the value of the register field L _X (or L _Y ) in the instruction code is carried as the second information.

[Procedure amendment 20]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction content]

The comparator circuit 390 (or 400) is connected to the signal line 31 (or 3).
Compare the value of 2) with the constant "1011", and then use the signal line 31 (or 32).
When the value of 2 is smaller than the constant "1011", it is connected to the switch 90 (or 92) to output the signal 0 "and turn off the electric switch 90 (or 92), and the electric switch 91 (or 93). Is connected to the input terminal of the inverting circuit 48 (or 49), and the output terminal of the inverting circuit 48 (or 49) is connected to the switch 91 (or 93).
One terminal of (or 91 and 93) has a constant "10000"
(Or the output terminal of the pointer 30), and the other end is connected to the input terminal of the adder 33 (or 34) by the signal line 31 (or 32).
Is connected with.

[Procedure correction 21]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction content]

The operation will be described below. Signal line 31 (or 3
If the value of 2) is greater than or equal to the value of the register 94, the comparison circuit 390 (or 400) turns on the electric switch 90 (or 92) and turns off the electric switch 91 (or 93), so that the adder 33 (Or 34) to signal line 31 (or 32) and constant "10000
"And it is input. Adder 33 (or 34) is signal line 31
(Or 32) and the constant "10000" are added, and the addition result is the R _X decoder 45 (or R _Y decoder 46) or the fifth (or sixth) latch circuit 35 (or 36), the ninth Latch circuit
The signal is sent to the R _Z decoder 47 via the 37th and 10th latch circuits 38. R _X decoder 45 (or R _Y decoder 46) or R _Z
The decoder 47 selects a general-purpose register corresponding to the addition result in the general-purpose register group 4 as a global register according to the addition result.

[Procedure correction 22]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

When the value of the signal line 31 (or 32) is smaller than the value of the register 94, the comparison circuit 390 (or 400) turns off the electric switch 90 (or 92) and turns on the electric switch 91 (or 93). Therefore, adder 33 (or 34) to signal line 31 (or 3
2) and the value of pointer 30 are input. Adder 39 (or 4
0) adds the value of the signal line 31 (or 32) and the value of the pointer 30, and the addition result is the R _X decoder 45 (or R _Y decoder 4).
6) Or, or 5th (or 6th) latch circuit 35 (or 36)
, Through the ninth latch circuit 37 and the tenth latch circuit 38 to the R _Z decoder. The R _X decoder 45 (or R _Y decoder 46) or R _Z decoder 47 selects a general-purpose register corresponding to the addition result in the general-purpose register group 4 according to the addition result.

[Procedure amendment 23]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction content]

Now, the register field L of the instruction code
_X (or L _Y ) is a binary number "0100" (register number 4)
Shall be At that time, the value of signal line 31 (or 32) is
It becomes "1011" which is a complementary signal of "0100" . Therefore, the detection circuit 390 (or 400) compares the value “1011” of the signal line 31 (or 32) with the constant “1011” of the register 94, and as a result, the former value is equal to the latter constant , so that the output signal (1) Via electrical switch 90 (or 92) and inverting circuit 48 (or 49) to electrical switch 91 (or 93), so that electrical switch 90 (or 92) is on and electrical switch 91 (or 93) is Since it is turned off, the adder 33 (or 34) is connected to the signal line 31 (or
The value "1100" of 32) and the constant "10000" are added, and the numerical value of the addition result ■ 27 " is R _X decoder 45 (or R _Y decoder 4
6) is transferred to the R _Z decoder 47, and the R _X decoder 45 (or the R _Y decoder 46) and the R _Z decoder 47 select the general register R27 from the general register group 4 using the addition result.

[Procedure correction 24]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction content]

Therefore, the register field L _X (or
When the value of L _Y ) is a binary number “0100” (register number 4) , the general register R27 can be used as a global register. Further register field L _X
The value of (or L _Y ) is binary number “0011” (register number
3), "0010" (register number 2) or "0001" (register number 1), the complementary signal "1100" ,
“1101” or “1110” is larger than the value in register 94.
Therefore, it is added to the constant "10000" and transferred to the R _X decoder 45 (or R _Y decoder 46) or R _Z decoder 47, and the general purpose registers R27, R28, R29 and R30 can be used as global registers.

[Procedure correction 25]

[Document name to be amended] Statement

[Name of item to be corrected] 0045

[Correction method] Change

[Correction content]

Further, the constant "1011" stored in the register 94
By changing to another constant, the number of general-purpose registers used as global registers in L1 to L15 can be changed. Therefore, the registers L4, L3, L2, and L1 are registered globally in the subroutine and main routine.
When used as a data register, set the value of register 94 to "1011" to set general purpose registers R27, R28, R29 and R30.
Can be used as global registers corresponding to the registers L4, L3, L2 and L1, respectively . At this time, registers other than registers L4, L3, L2, and L1 (L15
~ L5) are normal registers that cannot be used as global registers.

[Procedure Amendment 26]

[Document name to be amended] Statement

[Correction target item name] 0047

[Correction method] Change

[Correction content]

The operation of the block diagram of FIG. 7 will be described below. A constant is set in the general-purpose register 53 using an instruction code such as MOV #n, L _Z (set the constant n in the register L _Z ). Now register field L _X (or
If the value of the signal line 31 (or 32), which is the complementary signal of L _Y ) is greater than or equal to the value of the general-purpose register 53, the comparison circuit 390 (or 400) outputs the signal 1 ″ to output the electric switch 9
Since 0 (or 92) is turned on and the electric switch 91 (or 93) is turned off, the adder 33 (or 34) adds the constant "10000" to the signal line 31 (or 32) to add the R _X decoder 45 (or It is sent to the R _Y decoder 46) or the R _Z decoder 47. At this time R
_X decoder 45 (or R _Y decoder 46) or R _Z decoder 4
7 selects the global register.

[Procedure Amendment 27]

[Document name to be amended] Statement

[Correction target item name] 0049

[Correction method] Change

[Correction content]

Now, let us say that the set value of the general-purpose register 53 is "1100". Value of register field L _X (or L _Y ) "000
1 ”,“ 0010 ”or“ 0011 ”complementary signals“ 1110 ”,“ 1 ”
Only when 101 or 1100 is placed on the signal line 31 (or 32), the value of the signal line 31 (or 32) is greater than or equal to the value of the general-purpose register 53, so the complementary signals “1110” and “110
The addition result of "1" or "1100" and the constant "10000" is R _X.
Decoder 45 (or R _Y decoder 46) or R _Z decoder 47
To the R _X decoder 45 (or R _Y decoder
46) selects three general-purpose registers R30, R29 or R28 as global registers.

[Procedure correction 28]

[Document name to be amended] Statement

[Correction target item name] 0050

[Correction method] Change

[Correction content]

[0050] Since the above number of global register of the general register 53 as described can be set by the instruction code, the global register when using the global registers as if and the stack pointer using a global register as a register The number can be set freely. Therefore, the number of global registers does not become insufficient, and it is not necessary to save the general-purpose register value in the memory, and the program can be simplified and speeded up.

[Procedure correction 29]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure amendment 30]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

[Procedure correction 31]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

[Procedure correction 32]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure amendment 33]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

[Procedure amendment 34]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction content]

[Figure 7]

Claims (2)

[Claims] 1. A microcomputer for selecting a predetermined register from a plurality of registers by a decoder based on information about a register number and reading or writing data by using the selected register, the first register related to the register number. First storage means for storing information,
And a second addition means for adding the second information and the first information on the register number included in the instruction code, and for sending the result obtained by the addition means to the decoder as information on the register number. Computer. 2. A microcomputer for selecting a predetermined register from a plurality of registers by a decoder based on information about a register number and reading or writing data using the selected register, First storage means and second storage means for respectively storing information and third information; comparison means for comparing the third information with second information relating to the register number of the instruction code; An adding means for adding the information and the second information, and an addition result obtained by the adding means or the second information is selected according to the comparison result of the comparing means, and the selected value is sent to the decoder as information concerning the register number. And a selection unit for performing the selection.