JPH06205330A - Muse audio signal processing circuit - Google Patents

Abstract

PURPOSE:To smooth the signal processing and to reduce the circuit scale by processing modes A,B of a MUSE audio signal with the same circuit configuration. CONSTITUTION:In order to implement the signal processing in modes A,B in the same way, the method of processing data by each sample is adopted. Through the circuit configuration above, a clock signal whose frequency is 4 times of a sampling frequency in the mode A or a clock signal whose frequency is 2 times of the sampling frequency in the mode B is inputted to D flip-flops 1k,19l,1m connected in series in a pre-stage, and a clock signal whose frequency is a normal standard frequency is inputted four D flip-flops 1n,1o,1p,1q connected in parallel. Thus, data of one sample are inputted to a selector 3 in the same timing. Through such constitution, a selection signal of the selector 3 is controlled by a counter 4 and a decoder 5, and a data signal line is processed by one system to attain the same function as that of a conventional technology.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MUSE audio signal processing circuit used for audio signal processing of a high definition system.

[0002]

2. Description of the Related Art Generally, one sample of MUSE voice is 4
There are two types, A mode which is channel data and B mode which is 2 channel data. The sampling frequency is 32 kHz in A mode and 48 kHz in B mode.

In order to process such two types of different audio data, the conventional MUSE audio signal processing circuit
The circuit configuration is as shown in FIG. The conventional MUSE audio signal processing circuit will be described below. In FIG. 2, 1a to 1j are D flip-flops and 2a to 2c.
Is a selector. In the conventional MUSE voice signal processing circuit, data signal lines are connected to seven D flip-flops 1a, 1
a system composed of b, 1c, 1d, 1e, 1f, 1g,
It is divided into two parts of a system composed of three D flip-flops 1h, 1i, 1j, channel data of each system is selected by selectors 2a, 2b, and a signal of either system is selected by a selector 2c. It is configured to choose.
This is for sending the signal to the subsequent signal processing circuit by matching the timing of the data of one sample in the A mode, which is 4-channel data, and the B mode, which is 2-channel data.

[0004]

However, the conventional M
In the USE audio signal processing circuit, there are two types of MUSE audio data, A mode and B mode, which have different data formats, and one channel is 16-bit data. In order to process this data, the conventional MUSE audio signal processing circuit divides the data signal line into two systems for processing. Since the data signal line is divided into two systems and the data timing of one sample is adjusted by the D flip-flop 1, the circuit scale becomes large when data signal processing is performed in parallel, and it is divided into two systems. Along with this, there was a problem that the reliability of the circuit also deteriorated.

The present invention is intended to solve the above-mentioned conventional problems. The data signal line is not divided into two systems, but is processed by only one system, thereby facilitating signal processing and reducing the circuit scale. , And to improve the reliability of the circuit.

[0006]

In order to solve the above-mentioned problems, the MUSE audio signal processing circuit according to the present invention does not divide the data signal line into two systems, but adds a counter circuit and a decoder circuit, It is characterized by processing only by the system. That is, a plurality of D flip-flops arranged in series, which are input with a plurality of channel modes having different channel data, and a plurality of D flip-flops arranged in parallel, which output a plurality of channel data at the same timing, A selector circuit for selecting one from outputs of a plurality of D flip-flops arranged in parallel, a counter circuit for controlling a select signal of the selector circuit, and a decoder circuit for decoding a counter value from the counter circuit. It is characterized by Also, three D flip-flops arranged in series to which a clock having a sampling frequency of four times is input and twice that of a B mode is input, and four D flip-flops arranged in parallel to which a clock of a normal sampling frequency is input. A flip-flop, a selector circuit that selects one from the outputs of the four D flip-flops that are arranged in parallel, a counter circuit that controls a select signal of the selector circuit, and a counter value that is decoded from the counter circuit. In the B mode, when two channels of data are input to the selector circuit at the same timing, the counter circuit and the decoder circuit select one of two samples. It is configured to do.
Instead of dividing the data signal line into two systems, a counter circuit and a decoder circuit are added and processing is performed by only one system.

[0007]

With the above structure, the number of D flip-flops and selectors is reduced, and the number of data signal lines is only one. Therefore, the signal processing of the MUSE audio signal processing circuit and the associated peripheral circuits according to the present invention can be smoothly performed. Therefore, the circuit scale can be reduced, and the reliability of the circuit can be improved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a MUSE audio signal processing circuit according to an embodiment of the present invention.

In FIG. 1, 1 is a D flip-flop, 3 is a selector, 4 is a counter, and 5 is a decoder.

The MUSE audio signal processing circuit of this embodiment is
Three D flip-flops 1k, 1l, 1m are arranged in series, and then four D flip-flops 1n are arranged in parallel to output one sample of data (channel 1 to channel 4) at the same timing. , 1o, 1
p, 1q and these four D flip-flops 1n,
Selector 3 for selecting one from the outputs of 1o, 1p and 1q
And a counter 4 for controlling the selection signal of the selector 3 and a decoder 5 for decoding the value of the counter.

As described above, one sample in the A mode is 4 channel data, and one sample in the B mode is 2 channels.
Since the data formats such as channel data are different, it is difficult to perform the same signal processing in A mode and B mode. Therefore, in this embodiment, in order to perform the same signal processing in the A mode and the B mode, a method of processing the data for each sample of data is adopted. According to the circuit configuration of this embodiment, four times the sampling frequency in the A mode and twice the B frequency in the B mode are input to the three D flip-flops 1k, 1l, 1m arranged in series in the preceding stage. After that, a clock having a normal sampling frequency is input to the four D flip-flops 1n, 1o, 1p, 1q arranged in parallel. As a result, one sample of data can be input to the selector 3 at the same timing. The operation of the selector 3 sequentially selects the D flip-flops 1n, 1o, 1p, and 1q for 16-bit data, and repeats 16 times. This operation is performed within the sampling frequency. However, in the above configuration, in the case of the B mode, since the data of two channels are input to the selector 3 at the same timing, the counter 4 and the decoder 5 select the previous sample of the two samples. There is. That is, the samples output from the D flip-flops 1n and 1o are selected.

As described above, according to this embodiment, by controlling the selection signal of the selector 3 by the counter 4 and the decoder 5, the data signal line is not divided into two systems, but 1
It is possible to perform the same function as in the prior art by processing only by the system.

In the above embodiment, the selection operation of the selector 3 is not limited to the order described above, and it goes without saying that the selection operation may be performed in any order.

[0015]

According to the present invention, the A of the MUSE audio signal is
By processing the B mode and the B mode with the same circuit configuration, the reliability of the circuit is improved and the MU with a small circuit scale is excellent.
It realizes an SE audio signal processing circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a MUSE audio signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional MUSE audio signal processing circuit.

[Explanation of symbols]

 1a to 1q D flip-flop 2a to 2c selector 3 selector 4 counter 5 decoder

Claims (2)

[Claims] 1. A plurality of serially arranged D flip-flops to which a plurality of channel modes having different channel data are input, and a plurality of parallel D flip-flops to output a plurality of channel data at the same timing. A selector circuit for selecting one of the outputs of the plurality of D flip-flops arranged in parallel, a counter circuit for controlling a select signal of the selector circuit, and a decoder circuit for decoding a counter value from the counter circuit. And a MUSE audio signal processing circuit. 2. Three Ds arranged in series to which a clock of 4 times in A mode and a clock of 2 times in B mode are input.
A flip-flop, four D flip-flops arranged in parallel to which a clock having a normal sampling frequency is input, and a selector circuit for selecting one from outputs of the four D flip-flops arranged in parallel, It has a counter circuit which controls the select signal of the selector circuit and a decoder circuit which decodes the counter value from the counter circuit. In the case of the B mode, two channels of data are input to the selector circuit at the same timing. 2. The MUSE audio signal processing circuit according to claim 1, wherein, in the case of being performed, the counter circuit and the decoder circuit are configured to select one of two samples.