JPH06204991A - Transmission delay adjustment circuit - Google Patents

Abstract

PURPOSE:To provide a transmission delay adjustment circuit capable of making transmission delay small for a signal whose VT size is small at the time of coping with the signals of all the VT sizes by one memory circuit. CONSTITUTION:In a piece of digital synchronous communication equipment provided with a serial/parallel conversion circuit 10, the memory circuit 20 and a parallel/serial conversion circuit 30, a transmission speed detection means 40 and a memory number of stage adjustment means 50 are provided. Then, a bit for displaying a transmission speed in input data is extracted by the transmission speed detection means 40, the output of the transmission speed detection means 40 is decoded by the memory number of stage adjustment means 50, the transmission speed is judged from a decoded result and the operation number of stage of the memory circuit 20 is adjusted to the number of stage corresponding to the transmission speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission delay adjusting circuit when a pointer is replaced in a digital synchronous communication system.

[0002] In recent years, digital communication devices are called SONET (Synchronous Optical Network).
Called)) is increasing. In this method, a synchronization method using a signal that indicates the beginning of a multiplexed signal called a pointer is used.

In the SONET trunk line system, the optical signal is O
C-3 (155.52 Mbps), OC-12 (62
A large capacity such as 2.08 Mbps) is being put to practical use, and in this system, it is possible to multiplex signals having different transmission speeds (VT sizes) in a multiplexed signal.

FIG. 4 is a diagram for explaining a SONET pointer. (A) shows a frame structure of STS-1 (Synchronous Transport Signal-level) which is an electric signal of OC-1 of SONET, and one frame is composed of 9 rows × 90 bytes, and this frame is repeated at 125 μS. Results in 51.84 Mbps. The first 3 bytes of this 90 bytes are the overhead bytes, and the last 87 bytes
The bytes contain the main data.

The pointer is stored in the H1 and H2 bytes in the fourth row of the overhead byte shown in the figure. J1 is S
It indicates the head of main data called TS-SPE and is pointed to by a pointer.

Further, in the STS-SPE signal,
A signal called VT is multiplexed, and pointers are stored in V1 and V2 bytes. V5 byte is VT-S
It indicates the beginning of data called PE, and is indicated by the pointers in the V1 and V2 bytes.

(B) shows the structure of V1 and V2 bytes.
The first 4 bits are NDF (New Data Flag), which is a bit indicating that the pointer has been updated, the next 2 bits indicate the VT size, and the next 10 bits are pointer bits.

FIG. 5 is a diagram for explaining the add / drop multiplexer. In the figure, three adders of CH1 to CH3 of 50 Mbps are input to the add / drop multiplexer 100. Signals of a plurality of VT sizes are accommodated in 50 Mbps of CH1 to CH3, respectively, and a channel of a designated VT size in CH1 to CH3 drops as CHA in the communication device 200, and CH1
A signal from the communication device 200 is inserted into a designated VT size channel in CH3.

Therefore, it is the same that the input side CH1 to CH3 and the output side CH1 'to CH3' have three 50 Mbps signals, but since the contents of each channel change, they are replaced with new pointers. Will be needed.

Even if a VT size signal is input to the memory circuit necessary for such pointer replacement, a single memory circuit is used to reduce the size of the device. Transmission delay is large for small signals. There is a demand for a circuit that can reduce the transmission delay when the pointer is replaced.

[0011]

2. Description of the Related Art FIG. 6 is a block diagram for explaining a conventional example. 10 in the figure is a serial / parallel conversion circuit (hereinafter S
/ P conversion circuit), 21 is a multi-stage memory, 22A is a write pulse generator, 23A is a read pulse generator, 2
Reference numeral 4 is a phase comparator, 25 is a reference pulse generator, and 30 is a parallel / serial conversion circuit (hereinafter referred to as P / S conversion circuit).

The input data is converted from serial data to parallel data by the S / P conversion circuit 10 and then written in the multistage memory 21 in accordance with the signal generated by the write pulse generator 22A.

The written data is read according to a signal generated by the read pulse generator 23A, and P /
The S conversion circuit 30 converts parallel data to serial data and outputs the serial data.

[0014]

In the above-mentioned conventional example, the multi-stage memory 21 can cope with signals of all VT sizes, and here, the VT6 (6 Mbps means the largest number of stages). Since the number of stages is compatible with
In the case of VT1.5, the transmission delay becomes the largest.

In order to reduce the transmission delay, the write pulse generator 22A and the read pulse generator 23A are made to have a pulse having a fixed cycle according to the VT size, and the multistage memory 21 is also fixed according to the VT size. Since the operation is performed in the number of stages, different hardware is required for signals with different VT sizes.

According to the present invention, when a memory circuit necessary for pointer replacement is handled by one memory circuit, no matter what VT size signal is input, even when a signal having a small VT size is transmitted, the transmission is performed. An attempt is made to realize a transmission delay adjustment circuit that can reduce the delay.

[0017]

FIG. 1 is a block diagram for explaining the principle of the present invention. 10 in the figure is the input data S
Reference numeral 20 denotes a S / P conversion circuit for performing P / P conversion, reference numeral 20 denotes a memory circuit for writing / reading data output from the S / P conversion circuit 10, and reference numeral 30 denotes P / S conversion of the data written in the memory circuit 20 for output. P / S conversion circuit.

Further, 40 and 50 are provided by the present invention, 40 is a transmission rate detecting means for extracting a bit indicating the transmission rate in the input data, and 50 is an output of the transmission rate detecting means 40. Memory stage number adjusting means for decoding and adjusting the number of operation stages of the memory circuit 20,
The bit indicating the transmission rate in the input data is extracted by the transmission rate detecting means 40, input to the memory stage number adjusting means 50, the output of the transmission rate detecting means 40 is decoded by the memory stage number adjusting means 50, and the result is decoded. The transmission speed is determined from the above, and the number of operation stages of the memory circuit 20 is adjusted to the number of stages corresponding to the transmission speed.

[0019]

For example, in SONET digital synchronous communication, the VT size is written in the pointer in the overhead byte. The bit indicating the VT size is detected by the transmission rate detecting means 40, and the memory stage number adjusting means 5 is detected.
Enter 0.

The memory stage number adjusting means 50 decodes the output of the transmission rate detecting means 40, determines the transmission rate, and outputs it as a signal for controlling the number of operating stages of the memory circuit 20,
The number of operation stages of the memory circuit 20 is controlled. That is, when the transmission speed is slow, the number of operation stages of the memory circuit 20 is reduced,
It is possible to reduce the transmission delay.

[0021]

FIG. 2 is a block diagram illustrating an embodiment of the present invention. In the figure, 10 is an S / P conversion circuit, and 30 is a P / S conversion circuit.

In addition, the memory circuit 20 described in the principle diagram is composed of a multi-stage memory 21, a write pulse generator 22, a read pulse generator 23, a phase comparator 24, a reference pulse generator 25.
And the transmission speed detecting means 40 as the VT size detector 4
In this example, the memory stage number adjusting means 50 is composed of a decoder 51.

In the figure, first, the VT size detector 41 extracts a bit indicating the VT size of the pointer in the input data, the decoder 51 decodes the bit, determines the received VT size, and the write pulse generator 22. , VT size information is sent to the read pulse generator 23.

The write pulse generator 22 and the read pulse generator 23 control an internal counter (not shown) based on the VT size information received from the decoder 51 to receive the VT.
The clocks, the timing signals, and the phase comparison signals passed to the phase comparator 24 are changed so that the multistage memory 21 operates with the number of memory stages corresponding to the size.

The multi-stage memory 21 has a number of memory stages capable of supporting a VT size that requires the largest number of memory stages, and clocks and timing signals output from the write pulse generator 22 and the read pulse generator 23 are output. When the switching is performed, the number of memory stages is also switched. For a signal having a small VT size, the transmission delay can be reduced by reducing the number of operating stages of the multi-stage memory 21.

The write pulse generator 22 operates based on the input clock (indicated by CLK in the figure).
The read pulse generator 23 operates with the output of the reference pulse generator 25 as a reference. The phase comparator 24 compares the phases of the write pulse generator 22 and the read pulse generator 23, and controls the phase of the read pulse generator 23 when the two phases come close to each other and there is a risk of causing a data error. is doing.

FIG. 3 is a block diagram for explaining another embodiment of the present invention. The configuration of FIG. 3 is different from the configuration of the embodiment of FIG. 2 in that the VT size detector 41 is replaced by the VT size setter 4.
2, a processing device (hereinafter referred to as CPU) 60, and a terminal 70.

Many of various transmission devices are software-controlled by using the CPU 60. Through the CPU 60 incorporated in such a transmission device, the terminal 7
The VT size set by 0 is input to the VT size setting unit 42, and the VT size setting unit 42 inputs the input VT size information to the decoder 51. The operation after the decoder 51 is the same as that of the embodiment described in FIG. 2, and for a signal with a small VT size, the transmission delay can be reduced by reducing the number of operation stages of the multi-stage memory 21.

[0029]

According to the present invention, when one VT size is handled by one memory circuit when pointers are replaced, the number of operating stages of the memory circuit is reduced for a VT size signal having a slow signal speed. As a result, the transmission delay can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the present invention.

FIG. 3 is a block diagram illustrating another embodiment of the present invention.

FIG. 4 is a diagram illustrating a SONET pointer.

FIG. 5 is a diagram illustrating an add / drop multiplexer.

FIG. 6 is a block diagram illustrating a conventional example.

[Explanation of symbols]

 10 S / P conversion circuit 20 Memory circuit 21 Multi-stage memory 22, 22A Write pulse generator 23, 23A Read pulse generator 24 Phase comparator 25 Reference pulse generator 30 P / S conversion circuit 40 Transmission speed detection means 41 VT size detection 42 VT size setting device 50 Memory stage number adjusting means 51 Decoder 60 CPU 70 Terminal 100 Add / drop multiplexer 200 Communication device

Claims (2)

[Claims] 1. A transmission delay adjusting circuit for changing pointers of a digital synchronous communication system with a single memory circuit, the serial / parallel converting circuit (10) converting serial / parallel input data, and the serial / parallel converting circuit. A memory circuit (20) for writing and reading data output from the parallel / parallel conversion circuit (10) and a parallel / serial conversion circuit (30) for performing parallel / serial conversion of the data written in the memory circuit (20) and outputting the data. In a digital synchronous communication device provided, a transmission rate detecting means (40) for extracting a bit indicating a transmission rate in input data, and an output of the transmission rate detecting means (40) is decoded to obtain the memory circuit (20). A memory stage number adjusting means (50) for adjusting the number of operation stages of the The bit indicating the transmission rate in the data is extracted by the transmission rate detecting means (40) and input to the memory stage number adjusting means (50), and the memory stage number adjusting means (50).
And decodes the output of the transmission rate detecting means (40),
A transmission delay adjusting circuit, characterized in that the transmission speed is judged from the decoded result and the number of operating stages of the memory circuit (20) is adjusted to the number of stages corresponding to the transmitting speed. 2. The transmission delay adjusting circuit according to claim 1, wherein a terminal (70) for inputting transmission speed information is provided, and the transmission speed information input from the terminal (70) is processed in the digital synchronous communication device. The number of operating stages of the memory circuit (20) is adjusted by writing to the VT size setter (42) via (60) and decoding the transmission rate information by a decoder (51). The transmission delay adjustment circuit described in 1.