JPH0620496A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten a reliability acceleration test time by providing a word line simultaneous selection means, making the output ends of the signals of the same level and the inverse level as each bit of the address signal of an address buffer an active level also and making plural word lines a selection level simultaneously. CONSTITUTION:When a test signal TSTb becomes the active level, the levels in the output ends of the signals A1, A1b, A2, A2b... of the address buffer 1 become 'H' also. Thus, the output ends, as well of the inverters IV9-IV12... of an X decoder 3 become 'H' also, and transistors Q3-Q6 are turned on, and the word line drive voltage VWd of higher level than at a regular operation time is applied to each word line. In such a manner, since plural pieces of word lines become the higher level than at the regular operation time simultaneously, the reliability acceleration test time is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a semiconductor memory device that performs a reliability acceleration test.

[0002]

2. Description of the Related Art A conventional semiconductor memory device reliability acceleration test includes a voltage acceleration method of applying a voltage higher than a specified voltage to a semiconductor memory device to be tested, and a test method of withstanding voltage, heat resistance and the like. However, the voltage acceleration method among them will be described.

3 and 4 are a block diagram of a conventional semiconductor memory device in which a reliability acceleration test is performed by a voltage acceleration test method and a circuit diagram showing a concrete example of an internal circuit of each part thereof.

This semiconductor memory device includes an inverter (IV
1 to IV8 ...) and a plurality of bits of the address signal Aj
(J = 1, 2, ...) Is input and the same level (Aj) as each bit of this address signal Aj and its inversion level (Aj).
The address buffer circuit 1a which outputs the signal of b) and the test signal TSTb are inactive level (high level).
Of the word line drive circuit 2 for generating the word line drive voltage Vwd of the first level (normal selection level) when it is, and the second level which is higher than the first level when it is the active level. Transistor Q1,
A plurality of memory cells MC which are provided with Q2 and are arranged in the row direction and the column direction are brought into a selected state when the transistors Q1 and Q2 are in an ON state to write and read data, and a plurality of memory cells MC which are at a selected level. A memory cell array 4 including a plurality of word lines WL for turning on the transistors Q1 and Q2 of the memory cells in the corresponding rows, a NAND gate (G5 to G8 ...), an inverter (IV9 to IV12 ...), a transistor (Q3 ~ Q6
...) and a word decoder X decoder 3 for driving a predetermined word line of the plurality of word lines WL to a selection level corresponding to the word line drive voltage Vwd in accordance with the output signal of the address buffer circuit 1a. ing. A plurality of X decoders 3 and memory cell arrays 4 are provided.

When the test signal TSTb is at the inactive level, that is, in the normal operation, the word line drive circuit 2 supplies transistors Q1 and Q2 with respect to the power supply voltage.
The word line drive voltage Vwd of the normal selection level which is higher by the threshold voltage of is output. The address buffer circuit 1a and the X decoder 3 set one of the plurality of word lines WL to a selection level corresponding to the word line drive voltage Vwd according to the address signal Aj.

As a result, the transistors Q1 and Q2 of the memory cell MC are turned on and the memory cell MC is in the selected state. Then, the data from the digit lines DL1 and DL2 is written, and the stored data is read out to the digit lines DL1 and DL2.

When the test signal TSTb is at the active level (low level), the operation is the same as the above-mentioned normal operation except that the word line drive voltage Vwd is higher than the normal selection level.

As a result, a voltage higher than that in the normal operation is applied to the gates of the transistors Q1 and Q2 of the selected memory cell MC, and the reliability acceleration test is performed.

[0009]

In the conventional semiconductor memory device, one of the plurality of word lines WL is set to the selection level according to the address signal Aj even when the reliability acceleration test is performed. Therefore, there is a problem that the test time becomes longer as the memory capacity increases.

An object of the present invention is to provide a semiconductor memory device capable of shortening the time required for the reliability acceleration test.

[0011]

SUMMARY OF THE INVENTION A semiconductor memory device of the present invention includes an address buffer circuit which receives an address signal of a plurality of bits and outputs a signal of the same level as each bit of the address signal and an inverted level thereof, and a test signal. A word line drive circuit for generating a word line drive voltage of a first level when is an inactive level and a second level higher than the first level when is an active level, and a selection transistor respectively. A plurality of memory cells which are arranged in the row direction and the column direction and are in a selected state when the transistors are in an ON state and for writing and reading data, and when the selected level is selected, the memory cells in a corresponding row of the plurality of memory cells A memory cell array including a plurality of word lines for turning on a transistor, and the address buffer. In a semiconductor memory device having a word decoder that drives a predetermined word line of the plurality of word lines to a selection level corresponding to the word line drive voltage according to an output signal of a path, when the test signal is at an active level, The word line simultaneous selection means for simultaneously setting at least two of the plurality of word lines to the selection level is provided.

Further, the word line simultaneous selection means is provided in the address buffer circuit, and when the test signal is at the active level, the output terminals of the signal of the same level as the predetermined bit of the address signal and its inverted level are simultaneously set to the active level. It is formed by a logic gate.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

1 and 2 are a block diagram of an embodiment of the present invention and a circuit diagram showing a concrete example of an internal circuit of each part of this embodiment.

This embodiment differs from the conventional semiconductor memory device shown in FIGS. 3 and 4 in that the address buffer circuit 1 is replaced by the inverters (IV5 to IV8 ...) Of the conventional address buffer circuit 1a. A 2-input NAND gate (G1 to G1) for inputting the test signal TSTb to the first input terminal
G4 ...) are provided, and these NAND gates (G1 to G4) are provided.
...), the test signal TSTb is at an active level (low level) and includes an output end of a signal having the same level as that of each bit of the address signal Aj and an inverted level thereof and a word line simultaneous selection means for making a high level active level. A plurality of word lines are simultaneously set to the selection level by the high level at the output end.

In FIG. 2, when the test signal TSTb becomes the active level, all the output terminals of the signals (A1, A1b, A2, A2b ...) Of the address buffer circuit 1 become the high level. As a result, all the output terminals of the inverters (IV9 to IV12 ...) Of the X decoder 3 also become high level, the transistors (Q3 to Q6 ...) Are turned on, and the word line drive voltage Vw at a higher level during normal operation.
d is applied to each word line.

In this way, since the plurality of word lines simultaneously reach a higher level selection level during normal operation, the time required for the reliability acceleration test can be shortened.

When the test signal TSTb is a high level inactive level, the NAND gates (G1 to G1
G4 ...) operates simply as an inverter,
The circuit is equivalent to the conventional example shown in FIG.

[0019]

As described above, according to the present invention, a plurality of word lines are simultaneously set to the selection level while the output terminals of the signal having the same level as that of each bit of the address signal of the address buffer circuit and its inverted level are both set to the active level. Since the word line simultaneous selection means is provided, the number of memory cells that can be tested at one time is significantly larger than that of the conventional example, so that there is an effect that the time of the reliability acceleration test can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of an internal circuit of each part of the embodiment shown in FIG.

FIG. 3 is a block diagram showing an example of a conventional semiconductor memory device.

FIG. 4 is a circuit diagram showing a specific example of an internal circuit of each part of the semiconductor memory device shown in FIG.

[Explanation of symbols]

 1, 1a Address buffer circuit 2 Word line drive circuit 3 X decoder 4 Memory cell array DL1, DL2 Digit line G1 to G8 NAND gate IV1 to IV12 Inverter MC Memory cell Q1 to Q6 Transistor WL Word line

Claims (2)

[Claims] 1. An address buffer circuit which inputs an address signal of a plurality of bits and outputs a signal of the same level as each bit of the address signal and its inverted level, and a first level when a test signal is an inactive level, A word line drive circuit that generates a word line drive voltage of a second level higher than the first level when the active level is provided, and transistors for selecting each are arranged in the row direction and the column direction, and the transistors are turned on. And a plurality of word lines for turning on the transistors of the memory cells of the corresponding row of the plurality of memory cells when the selected level is set. A memory cell array and a plurality of word lines of the plurality of word lines according to an output signal of the address buffer circuit. In a semiconductor memory device having a word decoder for driving a predetermined word line of the word line to a selection level corresponding to the word line drive voltage, at least two of the plurality of word lines are activated when the test signal is at an active level. A semiconductor memory device characterized in that word line simultaneous selection means for simultaneously setting selection levels is provided. 2. A word line simultaneous selection means is provided in the address buffer circuit, and when the test signal is at the active level, the output terminals of the signal at the same level as the predetermined bit of the address signal and its inverted level are simultaneously set to the active level. The semiconductor memory device according to claim 1, which is formed by a logic gate.