JPH0817040B2 - Semiconductor memory - Google Patents

Description

The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory capable of significantly shortening a test time.

[Conventional technology]

In the conventional semiconductor memory of this type, means for collectively writing information to a plurality of memory cells at the time of testing, and expected value information input at the time of testing and read information from the plurality of memory cells are collectively compared. Had no means and.
Therefore, in the conventional test of this kind of semiconductor memory, information is written in and read from each memory cell in the memory cell array, and a comparison is made on the side of the memory tester for detection of coincidence between the read information and expected value information. I was doing in. This is described, for example, in Masaki Kumanoya, 90-nanosecond 1-megabit DRAM with multi-bit test mode, IEE
E, Solid State Circuit International Conference, pp. 240-241, 1985 "(1985IE
EE, International Solid State Circuits Conference, p
p.240 to 241, A 90ns 1Mbit DRAM with multi bit test m
ode, KUMANOYA).

Further, in the conventional semiconductor memory, the test is performed by the comparison operation for each memory cell, so that the test time is significantly increased due to the increase in the capacity of the semiconductor memory. For example, "MSCAN", which is one of the simplest test patterns, and "CHECKER BO
When a test is performed using the ARD with a cycle time of 300 ns, the test time of a semiconductor memory having a memory capacity of 256 kb (kilobit) is 0.3 seconds each.

[Problems to be solved by the invention]

However, when the memory capacity is increased to 16 Mb (megabit), the test time reaches 20 seconds each. The increase in the test time causes an increase in the cost of the semiconductor memory, which in turn hinders mass production.

The present invention has been made in view of such a point,
An object of the invention is to obtain a semiconductor memory which does not increase the test time and does not increase the cost even if the capacity of the semiconductor memory is increased, and thus does not hinder the mass production.

[Means for solving problems]

According to the present invention, test information of "0" or "1" applied from an external terminal is applied to a plurality of memory cells selected by a word line in response to a test pattern write control signal that instructs writing of test information. A batch writing means for writing in a batch, test information written in a plurality of memory cells selected by a word line, and expected value information of "0" or "1" applied from an external terminal in a batch. And a batch comparison means for performing comparison, and the batch write means is a data write means for writing data to a memory cell corresponding to an address input by outputting arbitrary data to a bit line during normal operation. Separately provided for each bit line and writing the test information to the memory cell by outputting the test information to the corresponding bit line according to the test pattern write control signal. The batch comparison means having a control gate is provided for each bit line, and is composed of a transistor which is turned on / off according to the test information read from the corresponding memory cell to the bit line. By inputting, the comparison circuit that outputs the comparison result of the test information and the expected value information according to the ON / OFF operation, and the test information and the expected value that all the comparison results output from each comparison circuit respectively correspond And a determination circuit for determining and outputting that the test result for the word line is normal when it indicates a match with the information.

[Action]

In the present invention, at the time of semiconductor memory test, it is possible to carry out batch writing and batch comparison corresponding to a word line or a part of a word line with respect to several specific types of test patterns.

〔Example〕

FIG. 1 shows the configuration of the first embodiment of the present invention. FIG. 1 is an example of a folded bit line configuration in which a pair of bit lines in the same memory cell array is connected to a sense circuit, and a unit of collective writing and collective comparison is a word line. In the figure, 1 is a memory cell array, 2, 2'is a word line, and 3a, 3b, 3a ', 3b' are memory cells. For example, all memory cells connected to the word line 2 are simplified and represented by two. There is. 4,4 'are bit lines, similarly simplified to 2
Represented in pairs. Here, BL1 and ▲ ▼, BL2
And ▲ ▼ form a bit line pair, respectively, and BL1 and ▲ ▼ are operated by the action of a dummy cell (not shown) and the sense circuit 7.
The opposite information appears in ▼. Further, 5 is a row decoder, 6 is a word driver, 7 is a sense circuit, 8 is a test pattern write control gate corresponding to a bit line, 9 is a test pattern write control line, 10 is a test pattern write control terminal,
Reference numerals 11 and 12 are test pattern write lines, and reference numerals 13 and 14 are test pattern write terminals, which apply test patterns inverted to each other to the test pattern write lines 11 and 12. Further, 15 is a comparison circuit corresponding to a pair of bit lines, 16 is a NOR circuit (decision circuit) that performs match detection corresponding to word lines based on output information of a plurality of comparison circuits 15, and 17 is an output of 16 of the NOR circuit. A node, 18 is an output terminal of the collective comparison result, and 19 is an output node of the comparison circuit 15.

In such a configuration, the test pattern writing control gate 8, the test pattern writing control line 9, the test pattern writing control terminal 10, the test pattern writing lines 11 and 12, the test pattern writing terminals 13 and 14 constitute a batch writing means. Then, the test pattern write control line 9, the test pattern write control terminal 10, the test pattern write lines 11 and 12, the test pattern write terminals 13 and 14, the comparison circuit 15, the NOR circuit 16, the output terminal 18 and the like constitute a batch comparison means. To do.

Here, the test pattern write control terminal 10 is applied with the "H" level only when writing the test pattern, and is at the "L" level in other cases. The test pattern writing terminals 13 and 14 are applied with the “H” level or the “L” level only during the test, and are in the open state in other cases. In the figure, the supply of the power supply voltage Vcc through the resistor is for bringing both the test pattern write lines 11 and 12 to the "L" level in this open state. The output terminal 18 of the collective comparison result becomes the "L" level at the time of precharging and when all the bits are good as the collective comparison result, and becomes the "H" level when the defective bit is obtained as the collective comparison result. Further, Φ _W applied to the word driver 6 is a word line drive clock, Φ _SA applied to the sense circuit 7 is a sense circuit drive clock, and Φ _P in the NOR circuit 16 is a precharge clock.

Next, an example of the test according to the first embodiment will be described with reference to the timing chart shown in FIG. First, batch writing of test patterns corresponding to word lines is performed as follows. The precharge clock Φ _P shown in FIG. 2A is set to the “L” level and the row decoder 5 is operated to select the only word line 2. Next, the word line drive clock Φ _W shown in FIG. 2B is set to the “H” level, and the word driver 6 is operated to raise the selected word line 2 to the “H” level. After the information of all memory cells connected to the word line 2 appears on the bit line, the sense circuit drive clock Φ _SA shown in FIG. 2C is set to the “H” level to operate the sense circuit 7. After the voltage level of the bit line is determined by the operation of the sense circuit 7, as shown in FIG. 2D, the test pattern write terminals 13 and 14 are set to the “H” level or the “L” level according to the test pattern. Apply. Next, as shown in FIG. 2 (e), "H" level is applied to the test pattern write control terminal 10 to transfer the voltage level according to the test pattern onto the bit line. At this time, the word line 2 holds the "H" level, and the test pattern batch writing corresponding to the word line is performed. Next, after setting the test pattern write control terminal 10 to the “L” level and the test pattern write terminals 13 and 14 to the “H” level, the word line drive clock Φ _W and the sense circuit drive at the same timing as the normal memory operation. The clock Φ _{SA is set} to the “L” level to complete the series of write operations.

In this way, the word lines are sequentially selected as 2, 2 ', and the "H" level applied to the test pattern write terminals 13, 14
By sequentially changing the “L” level, “MSCAN”
Test patterns can be written in a batch. That is, in FIG. 1, "H" level or "L" level information is written in all the memory cells 3a, 3b, 3a ', 3b'. In addition, 2 word lines,
By sequentially selecting 2'and switching the "H" level and the "L" level applied to the test pattern writing terminals 13 and 14 for every two word lines, the test pattern of "CHECKER BOARD" can be written in batch. That is, in FIG. 1, the memory cell
"H" level or "L" level in 3a, 3b, memory cell 3
Information of "L" level or "H" level is written in a ', 3b'.

Also, as is clear from the above description of the write operation,
According to the test of the first embodiment, these test patterns can be correctly written even in the semiconductor memory in which the physical arrangement of the memory cells in the memory cell array is different from the logical address arrangement. In order to facilitate this batch writing, when the “H” level is applied to the test pattern writing control terminal 10, the sense circuit drive clock Φ _SA is temporarily set to “L”.
The latch of the sense circuit 7 may be released by setting the level.
In addition, when the voltage level of the bit line is sufficiently determined by applying the voltage from the test pattern writing control terminal 10, the sense circuit 7 does not necessarily need to be operated.

Next, a sequence of a batch comparison corresponding to a word line will be described. First, during the precharge period, the precharge clock Φ _P is at “H” level, and the output node 17 of the batch comparison result is precharged to “H” level. After that, the same operation as the write operation is performed until the timing of operating the sense circuit 7. Next, after confirming the voltage level of the bit line,
A voltage level opposite to the test pattern for the write operation is applied to the test pattern write terminals 13 and 14. At this time, the test pattern writing control terminal 10 holds the "L" level. As a result, when the voltage level of the test pattern applied to the test pattern write terminals 13 and 14 during the comparison operation and the voltage level read from the memory cell and appearing on the bit line match, that is, read from the memory cell If the data is incorrect, the output node 19 of the comparison circuit 15 becomes the “H” level, and the output node 17 of the NOR circuit 16 is output.
Is changed from "H" level to "L" level. Therefore, by observing the change from the “L” level to the “H” level of the output terminal 18 of the batch comparison result, it is possible that the defective bit exists in all the memory cells connected to the selected word line. To be detected. This is shown in FIG. 2 (f). In FIG. 2 (f), the “H” level indicated by the solid line indicates the case where there is a defective bit, and the “L” level indicated by the dotted line indicates the case where all the bits are good or in writing.

Next, a specific example of the operation in which the voltage level of the test pattern and the read data from the memory cell match will be described. Test pattern writing terminal 13 for batch writing
Will be described as an example in which data is set to the "L" level and data of the "H" level is written in the memory cell 3a. In this case, in the batch comparison, the test pattern writing terminal 13 is at "H" level and the test pattern writing terminal 14 is at "L" level.
A level is applied and compared with the data from memory cell 3a. When the level of the data read from the memory cell 3a is erroneously at the "L" level in the batch comparison, the bit line BL1 or the upper transistor 15a of the comparison circuit 15 is compared.
The gate of the transistor becomes "L" level, and the transistor 15a is turned off. In this case, the level of the bit line ▼ becomes “H” level due to the action of the dummy cell and the sense circuit 7, and the gate of the transistor 15b at the lower stage of the comparison circuit 15 becomes “H” level. As a result, the transistor 15b is turned on, the "H" level applied to the comparison circuit 15 appears at the output node 19 by setting the test pattern writing terminal 14 to the "L" level, and the output node 17 of the NOR circuit 16 becomes "H". ”Level to“ L ”level. The above operation has been described for the case where the test pattern writing terminals 13 and 14 are at the “L” level and the “H” level when writing, but the test pattern writing terminals 13 and 14 are at the “H” level and “H” level when writing. The same operation is performed at the "L" level.

In the batch writing / batch comparison test method described above, the test patterns are “MSCAN” and “CHECKERBOARD”.
However, tests using "MARCHING" are also possible. This is performed by writing background data to all memory cells and performing batch comparison of read data that is subsequently performed in the same way as when using "MSCAN", and further by inverting the voltage levels applied to the test pattern write terminals 13 and 14. This can be achieved by the sequence of batch writing / comparing as in the case of using "MSCAN". However, in the present invention, since information of the same level is collectively written in these memory cells connected to the word line, it is impossible to detect a defect in the column address system which can be detected by the conventional test method. Therefore, with respect to the defect detection of the column address system, for example, a test by "MARCHING" for all memory cells connected to one or several word lines in the memory cell array 1 is separately performed.

As described above, according to the test method of the first embodiment, batch writing and batch comparison can be performed corresponding to word lines, so the test time can be shortened to 1 / n of that of the conventional semiconductor memory. Here, n is the number of memory cells connected to the word line for batch writing and batch comparison, and usually takes a large value of 500 or 1000 or more.

FIG. 3 shows the configuration of the second embodiment of the present invention. FIG. 3 shows an example in which the unit of collective writing and collective comparison is a word line, targeting an open bit line configuration in which a bit line pair is formed by different bit lines in different memory cell arrays across a sense circuit. In the figure, 1'is a memory cell array, 4L, 4L ', 4R, 4R' are bit lines, 4L and 4R, 4L '
And 4R 'respectively form a bit line pair. 16 'is a NOR circuit for matching detection corresponding to word lines, 17' is an output node of NOR circuit 16 ', 20 and 20' are test pattern write control gates corresponding to bit lines, and 21 and 21 'are comparisons corresponding to bit lines. Circuit, 22,
23, 24, 25 are test pattern writing lines, 26 is a NOR circuit 16, 16 '
OR that performs match detection for word lines based on the output information of
Circuits 27, 28, 29, 30 are test pattern write terminals 31, 31 ', and output nodes of the comparison circuits 21, 21'. In FIG. 3, the same or corresponding parts as those in FIG. 1 are designated by the same reference numerals.

Here, the test pattern writing terminals 27, 28, 29, 30 are applied with the “H” level or the “L” level only during the test, and are open in the other cases. The row decoder 5, word driver 6, word line drive clock Φ _W and sense circuit drive clock Φ _SA shown in FIG. 1 are also required in the second embodiment, but are omitted in FIG. are doing.

The test according to the second embodiment is the same as the first embodiment except that the control method of batch writing of test patterns and batch comparison is different. In the second embodiment, "CH
ECKERBOARD ”test pattern batch writing is performed by connecting the test pattern writing terminals 27 and 29 to the“ H ”level or the“ L ”level.
"L" level or "H" level is applied to the test pattern writing terminals 28 and 30, and the word lines are sequentially selected.
This is achieved by sequentially switching the "H" level and "L" level applied to these terminals. "MSCAN" test pattern batch writing is performed by the test pattern writing terminals 27 and 28.
It is achieved by applying "H" level or "L" level to, and "L" level or "H" level to 29 and 30, fixing the voltage level applied to these terminals and sequentially selecting word lines. It Further, "MARCHING" can be carried out in the same manner according to the method described in the first embodiment.

On the other hand, batch comparison of these test patterns is performed by applying a voltage level opposite to the above to each terminal and comparing with the voltage level appearing on the bit line in a normal read operation. The first point is that the defective bit is detected using the OR processing result of the output information of the NOR circuits 16 and 16 '.
Is different from the embodiment described above. The output terminal 18 of the batch comparison result becomes "L" level at the time of precharge and when all bits are good as a batch comparison result, and becomes "H" level when a bad bit is obtained as a batch comparison result.

According to the test of the second embodiment, these test patterns can be written correctly even in a semiconductor memory in which the physical arrangement of memory cells in the memory cell array is different from the logical address arrangement. Further, the release of the latch related to the sense circuit 7 described in the case of the first embodiment also holds true in the case of the second embodiment. According to the test of the second embodiment, batch writing and batch comparison can be performed corresponding to the word lines, so that the test time can be shortened to 1 / n of the time in the conventional semiconductor memory. Here, n is the number of memory cells connected to the word line for batch writing and batch comparison, and usually takes a large value of 500 or 1000 or more.

FIG. 4 shows a circuit system including a test pattern writing portion and a test pattern writing terminal sandwiched between the test pattern writing control gate 20 and the comparison circuit 21 and the test pattern writing control gate 20 'and the comparison circuit 21' in FIG. This is an excerpt of another configuration example. The feature of this configuration is that the number of test pattern write terminals is reduced to half by newly providing the test pattern selection terminals as compared with the configuration of FIG. In the figure, 32, 32 ', 33, 33' are test pattern writing lines, 3
4, 34 ', 35, 35' are test pattern selection lines, 36, 37 are test pattern write terminals, 38 are test pattern selection terminals, and 39 are test pattern selection gates, which are provided every other bit line. Further, in FIG. 4, the same or corresponding parts as those in FIG. 3 are designated by the same reference numerals.

Here, the test pattern writing terminals 36 and 37 are applied with the “H” level or the “L” level only during the test, and are in the open state in other cases.

The test method with the configuration of FIG. 4 is different from the test method of batch writing of test patterns and batch comparison, except that
This is similar to the second embodiment. In this configuration, "CHEC
"KERBOARD" test pattern batch writing is performed by the test pattern writing terminal 36 at "H" level or "L" level, the test pattern writing terminal 37 at "L" level or "H" level,
"H" level is applied to the test pattern selection terminal 38, and word lines are sequentially selected, and "H" is applied to the terminals 36 and 37.
This is achieved by sequentially switching the level and the "L" level. The batch writing of the test pattern of "MSCAN" is performed by the test pattern writing terminal 36 at the "H" level or the "L" level, the test pattern writing terminal 37 at the "L" level or the "H" level, and the test pattern selecting terminal 38 at the "L" level. This is accomplished by applying a level, fixing the voltage levels applied to these terminals and sequentially selecting the word lines. Regarding "MARCHING", it can be carried out in the same manner according to the method described in the second embodiment.

On the other hand, batch comparison of these test patterns is performed by applying a voltage level opposite to the above to the terminals 36 and 37 and comparing with the voltage level appearing on the bit line in a normal read operation. The effect of shortening the test time and the like by using the test method having the configuration of FIG. 4 are similar to those of the first and second embodiments.

In the open bit line configuration shown in FIG. 3, the memory cell arrays 1 ′ to 1 are arranged within the sense circuit pitch.
It is clear that if the pass bit line to the memory cell array 1 can be arranged and the test pattern write control gate 8 and the comparison circuit 15 in FIG. 1 can be arranged, only the NOR circuit 16 on the memory cell array 1 side need be provided. Further, the effect of shortening the test time and the like by adopting this configuration are similar to those of the first and second embodiments.

FIG. 5 shows the configuration of the third embodiment of the present invention.
This is applied to a high-density memory cell array configuration intended for an ultra-large capacity semiconductor memory. The features of this memory cell array configuration are as follows.

In order to reduce the decrease in the sense circuit pitch due to the reduction in the memory cell area, the sense circuits are distributed and arranged on both sides of the memory cell array.

The bit lines were split to reduce the bit line capacitance.

A main bit line which is not connected to the memory cell and is formed in a wiring layer different from the bit line is provided, and the main bit line and the bit line are electrically connected.

FIG. 5 shows a configuration example in which the memory cell array 1 is divided into two sub-arrays 40 and 40 'based on the folded bit line configuration, and only one main bit line pair is shown.
With this configuration, by disposing the sense circuit 7 on the left and right sides of the memory cell array 1, the sense circuit pitch can be expanded to four times the memory cell pitch. In the figure, 8'is a test pattern write control gate corresponding to a bit line pair, and 15 '
Is a comparison circuit corresponding to a bit line pair, 19 'is an output node of the comparison circuit 15', 41, 41 ', 42, 42' are main bit lines, 43, 44, 4
Reference numeral 5 is a switch relating to the main bit line, and 46, 47, 48, 49 are switches connecting the bit line and the main bit line. Also, in FIG. 5, the same or corresponding parts as those in FIGS. 1 and 3 are designated by the same reference numerals. The row decoder 5, word driver 6, word line drive clock Φ _W and sense circuit drive clock Φ _SA shown in FIG. 1 are also required in the third embodiment, but they are omitted in FIG. ing.

As a normal memory operation according to the configuration of FIG. 5, a read operation when the word line 2 in the figure is selected will be described below as an example. First, only the switches 43, 45, 46, 47 are turned on at substantially the same timing as the selection of the word line 2. As a result, the information of the memory cell 3a is transmitted to the left-side sense circuit 7 via the switches 46 and 43 and amplified. Also, memory cell 3b
Information via the switches 47 and 45, the right sense circuit 7
To be amplified. Then, the multiplexer and the data output circuit (both not shown) are operated to read only the memory cell information to be read.

Next, an example of the test according to the third embodiment will be described. First, write the test patterns for word lines all at once.
The case where the target word line is 2 in the figure will be described below as an example. Switches 43, 45, 46, 47 along with selection of word line 2
Turn on. Information of the memory cell 3a is the switch 46,43,
After the information of the memory cell 3b appears on the main bit lines 41 and 41 'through the switches 47 and 45, the left and right sense circuits 7 are operated. Here, since the switch 44 is in the off state, the main bit lines 41 and 41 'where the information of the memory cell 3a and the information of the memory cell 3b appear are electrically cut off.
After the voltage level of each main bit line is determined by the operation of the sense circuit 7, the test pattern write terminals 13, 1
Apply "H" level or "L" level to 4 according to the test pattern. Next, an “H” level is applied to the test pattern write control terminal 10 to change the voltage level corresponding to the test pattern to the test pattern write control gate 8 and the switches 43 and 4 respectively.
6 and test pattern writing control gate 8 ', switch 4
Transmission to bit lines 4, 4'via 5, 47. At this point, the word line 2 holds the "H" level, so that the test pattern batch writing corresponding to the word line is performed. next,
After setting the test pattern write control terminal 10 to "L" level and the test pattern write terminals 13 and 14 to "H" level, set the word line to the non-selected state at the same timing as the normal memory operation and perform a series of write operations. To finish. In this way, by sequentially selecting the word lines 2 and 2'and sequentially exchanging the "H" level and the "L" level applied to the test pattern write terminals 13 and 14, the "MSCAN" test patterns are collectively displayed. You can write it. That is, in FIG. 5, "H" level or "L" level information is written in all the memory cells 3a, 3b, 3a ', 3b'. In addition, by selecting the word lines 2 and 2'in sequence and exchanging the "H" level and "L" level applied to the test pattern write terminals 13 and 14 for every 2 word lines, the test pattern of "CHECKER BOARD" is batched. Then write. That is, in FIG. 5, the memory cells 3a and 3b have "H" level or "L" level, and the memory cells 3a 'and 3b'.
The information of "L" level or "H" level is written in. Regarding "MARCHING", it can be carried out in the same manner according to the method described in the second embodiment.

Also, as is clear from the above description of the write operation,
According to the test of the third embodiment, these test patterns can be correctly written even in a semiconductor memory in which the physical arrangement of the memory cells in the memory cell array is different from the logical address arrangement. In order to facilitate this batch writing, the latch of the sense circuit 7 may be released when the "H" level is applied to the test pattern writing control terminal 10.
If the voltage level of the bit lines 4 and 4'is sufficiently determined by applying the voltage from the test pattern writing control terminal 10, the sense circuit 7 does not have to be operated.

Next, a sequence of a batch comparison corresponding to a word line will be described. First, during the precharge period, the output nodes 17, 17 'of the batch comparison result are precharged to the "H" level. After that, the same operation as the write operation is performed until the timing of operating the sense circuit 7. Next, after confirming the voltage level of the main bit line, a voltage level opposite to the test pattern of the write operation is applied to the test pattern write terminals 13 and 14. As a result, when the voltage level of the test pattern applied to the test pattern write terminals 13 and 14 during the comparison operation matches the voltage level read from the memory cell and appearing on the main bit line, the comparison circuits 15 and 15 ' The output nodes 19 and 19 'become "H" level, and the output nodes 17 and 17' of the NOR circuits 16 and 16 'are changed from "H" level to "L" level. Therefore, “L” of output terminal 18 of the batch comparison result
By observing the change from the level to the “H” level, it is detected that the defective bit exists in all the memory cells connected to the selected word line. As described above, according to the test of the third embodiment, batch writing and batch comparison can be performed corresponding to word lines, so that the test time can be shortened to 1 / n of that of the conventional semiconductor memory. Here, n is the number of memory cells connected to the word line and collectively written / compared with each other, usually 500 or 1
Take a large value of 000 or more.

The test pattern writing control gate in FIG.
8, comparison circuit 15, NOR circuit 16 etc. are not provided for the sense circuit,
Provide only on one side of sense circuit, and OR circuit
A configuration in which the output node 17 is directly connected to the output terminal 18 of the batch comparison result without going through 26 also belongs to the category of the present invention. In this case, half of the memory cells connected to the word line are subjected to batch writing and batch comparison, so the test time is shortened to 2 / n of the conventional semiconductor memory. Here, n is the number of memory cells connected to the word line for batch writing / comparison.

Further, the present invention is not limited to the arrangement of the sense circuit 7 in FIG. Therefore, for example, the sense circuit 7
The configurations provided for 40 and 40 'also belong to the scope of the present invention.

Furthermore, the present invention is not limited to the connection relationship between the main bit line and the bit line in FIG. Therefore, for example, in the memory cell array configuration in which the test pattern write control gate 8 and the like are provided only on one sense circuit side, the switches 43, 44 and 45 relating to the main bit lines in FIG. Is also effective for such a memory cell array configuration.

Further, the present invention is not limited to the high-density memory cell array structure based on the folded bit line structure as shown in FIG. For example, FIG. 6 shows an example of application to a high-density memory cell array structure based on the open bit line structure. Similar to FIG. 5, FIG. 6 shows a configuration example in which the memory cell array 1 is divided into two sub-arrays 40 and 40 'only for a pair of main bit lines. Also, in order to simplify the drawing, various switches are represented by bar switches instead of transistors. In the figure, 50,50 ', 51,51', 53,5
3 ', 54, 54' are switches for connecting the bit lines and the main bit lines, and 52, 52 'are switches for the main bit lines. Further, in FIG. 6, the same or corresponding portions as those in FIGS. 1, 3, and 5 are designated by the same reference numerals. The first
The row decoder 5, word driver 6, word line drive clock Φ _W and sense circuit drive clock Φ _SA shown in the figure are also required in this embodiment, but they are omitted in FIG.

The test method with the configuration of FIG. 6 will be described below according to the third embodiment (FIG. 5). First, batch writing of test patterns corresponding to word lines will be described by taking a case where the target word line is 2 in the drawing as an example. When the word line 2 is selected, the switches 50 and 51 'are turned on. Memory cell 3a
Information for switch 50 and information for memory cell 3b is switch 5
After appearing on the main bit lines 41, 42 'via 1', the left and right sense circuits 7 are operated. Since the switches 52 and 52 'are now in the off state, the main bit lines 41 and 41' and 42
And 42 'are electrically cut off. After the voltage level of each main bit line is determined by the operation of the sense circuit 7, the "H" level or "L" level according to the test pattern is applied to the test pattern write terminals 27, 28, 29, 30. Next, an "H" level is applied to the test pattern write control terminal 10 to set the voltage levels corresponding to the test pattern to the test pattern write control gate 8, the switch 50, the test pattern write control gate 8'and the switch 51 ', respectively.
Via bit lines 4, 4 '. At this point, the word line 2 holds the "H" level, so that the test pattern batch writing corresponding to the word line is performed. Next, after setting the test pattern write control terminal 10 to the "L" level and further setting all the test pattern write terminals 27 to 30 to the "H" level, the word line is deselected at the same timing as the normal memory operation. A series of write operations is completed. In this way, the test pattern writing terminals 27 and 30 are at "H" level or "L" level, and the test pattern writing terminals 28 and 29 are at "L" level or "H" level.
By applying a level and sequentially selecting the word lines and sequentially replacing the “H” level and the “L” level applied to these terminals, the “CHECKER BOARD” test pattern can be written at once. In addition, by applying “H” level or “L” level to the test pattern writing terminals 27 and 29, and applying “L” level or “H” level to 28 and 30, the voltage levels applied to these terminals are fixed and word By sequentially selecting the lines, the "MSCAN" test pattern can be written at once. Also,
"MARCHING" can be carried out in the same manner according to the method described in the second embodiment.

Further, as is apparent from the above description, according to the test of the embodiment of FIG. 6, even in a semiconductor memory in which the physical arrangement of the memory cells in the memory cell array is different from the logical address arrangement, these test patterns are correctly You can write. In order to facilitate this batch writing, the latch of the sense circuit 7 may be released when the "H" level is applied to the test pattern writing control terminal 10. If the voltage level of the bit lines 4 and 4'is sufficiently determined by applying the voltage from the test pattern writing control terminal 10, the sense circuit 7 does not have to be operated.

Next, a sequence of a batch comparison corresponding to a word line will be described. First, the write operation is performed in the same manner until the timing at which the sense circuit 7 is operated. Next, after confirming the voltage level of the main bit line,
A voltage level opposite to the write operation test pattern is applied to 30. As a result, when the opposite voltage level applied and the voltage level appearing on the main bit line in the normal read operation match, the output nodes 19, 19 'of the comparison circuits 15, 15' become "H" level. , NOR circuits 16 and 16 'output nodes 17 and 17' are changed from "H" level to "L" level. Therefore, by observing the change from the “L” level to the “H” level of the output terminal 18 of the batch comparison result, it is possible that the defective bit exists in all the memory cells connected to the selected word line. To be detected.

As described above, according to the test of the embodiment shown in FIG. 6, batch writing and batch comparison can be performed corresponding to word lines, so that the test time can be shortened to 1 / n of that of the conventional semiconductor memory. . Here, n is the number of memory cells connected to the word line for batch writing and batch comparison, and usually takes a large value of 500 or 1000 or more.

The test pattern writing control gate shown in FIG.
8, the comparator circuit 15, the NOR circuit 16, the test pattern write lines 22 and 23, the test pattern write terminals 27 and 28, etc. are provided only on one of the sense circuit sides, and the output node 17 is provided without the OR circuit 26. The configuration of directly connecting to the output terminal 18 of the collective comparison result also belongs to the category of the present invention. in this case,
Since half of the memory cells connected to the word line are subjected to batch writing and batch comparison, the test time is shortened to the conventional semiconductor memory 2 / n. Here, n is the number of memory cells connected to the word line for batch writing / comparison.

Further, the present invention is not limited to the connection relationship between the main bit line and the bit line in FIG. Therefore, for example, the present invention is effective for a memory cell array configuration in which only one set of switches provided at both ends of the bit line is used to electrically connect to the main bit line.

FIG. 7 is a comparison circuit in FIGS. 1, 5, and 6.
This is another circuit configuration example in which the connection relationship between 15 and the bit lines 4, 4'or main bit lines 41, 42 is changed. The feature of this configuration is that the bit line 4,
It is a point where 4'or main bit lines 41 and 42 are cross-connected. With this configuration, at the time of batch comparison corresponding to word lines, the same voltage level (not inversion information) as the test pattern during the write operation can be applied to the test pattern write terminal. Therefore, there is an advantage that a desired test pattern can be applied without paying attention to the batch write operation and the batch comparison operation during the test. Furthermore, the test pattern write control gates 8, 8 ', 20, 20', the test pattern write control line 9, and the test pattern write control terminals in FIGS. 1, 3, 5, 6, and 7 are shown. 10, the test pattern write lines 11, 12, 22, 23, 24, 25 and the test pattern write terminals 13, 14, 27 to 30 are not limited to the configuration in the figure. Therefore, for example, the test pattern write lines 11 and 12 in FIG. 1 are combined into one, the test pattern write terminals 13 and 14 are combined into one, and instead, the test pattern write control line 9 is combined into two and the test pattern write control terminals are combined into one. It is also possible to have two 10's and to separately control the two transistors in the test pattern write control gates 8, 8'by these two test pattern write control lines 9.

Although all of the embodiments of the present invention have adopted the method of batch writing and batch comparing corresponding to word lines, for example, by multiple selecting a plurality of word lines collectively, all the memories in the memory cell array can be written in several times. It is also possible to write a test pattern in the cell. Therefore, in the present invention, the unit of collective writing and collective comparison is not limited to word line correspondence. It may be a single or plural word line unit or a part of word line. Further, it goes without saying that the present invention is not limited to the dynamic RAM as the semiconductor memory and can be applied to the static RAM, the ROM and the like in the same manner.

〔The invention's effect〕

As described above, according to the present invention, the test information of “0” or “1” is collectively written to the plurality of memory cells connected to the selected word line from the external terminal, and the test information is written to the selected word line. Between the test information written in the plurality of connected memory cells and the expected value information of "0" or "1" applied from the external terminal to the plurality of memory cells connected to the selected word line. By performing the comparisons in a lump, the writing / comparing time can be significantly shortened, so that there is an effect that a semiconductor memory capable of significantly reducing the test time can be realized.

In addition, when a plurality of word lines are multiple-selected, a specific test pattern can be written in all the memory cells by one or several write operations, so that the same effect as described above can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention, FIG. 2 is a timing diagram showing timings during a test, FIG. 3 is a configuration diagram showing a second embodiment of the present invention, and FIG. Is a block diagram showing a modification thereof, FIG. 5 is a block diagram showing a third embodiment of the present invention, FIG. 6 is a block diagram showing a modification thereof, FIG. 7 is FIG. 1, FIG. It is a block diagram which shows another circuit structural example which changed the connection relation of the comparison circuit and bit line or main bit line in FIG. 1,1 ′ …… Memory cell array, 2,2 ′ …… Word line, 3a, 3
b, 3a ', 3b' ... memory cells, 4,4 '... bit lines, 5 ...
... Row decoder, 6 ... Word driver, 7 ... Sense circuit, 8 ... Test pattern write control gate, 9 ... Test pattern write control line, 10 ... Test pattern write control terminal, 11, 12 ... Test pattern Write line, 13,14 …… Test pattern write terminal, 15 …… Comparison circuit, 15a, 15b ……
Transistor, 16 …… NOR circuit, 17,19 …… Output node,
18 …… Output terminal.

Claims (2)

[Claims] 1. A plurality of memory cells for storing information are arranged in a matrix, a plurality of bit lines for exchanging information of the plurality of memory cells and a plurality of memory cells for selecting the plurality of memory cells. In a semiconductor memory having two word lines, "0" applied from an external terminal to a plurality of memory cells selected by the word line in response to a test pattern write control signal instructing writing of test information, Collective writing means for collectively writing test information of "1", test information written to a plurality of memory cells selected by the word line, and "0" or "1" applied from an external terminal. And a batch comparison unit that collectively compares the expected value information of the memory with the expected value information. The batch writing unit outputs a desired data to the bit line during the normal operation to respond to the address input. The memory cell is provided for each bit line separately from the data write means for writing the data in the recell, and outputs the test information to the corresponding bit line in response to the test pattern write control signal, whereby the memory cell A test pattern write control gate for writing the test information into the bit line, and the batch comparison means is provided for each bit line and is turned on / off in accordance with the test information read from the corresponding memory cell to the bit line. A comparator circuit which is composed of an operating transistor, and outputs the comparison result of the test information and the expected value information according to the on / off operation by inputting the expected value information into the transistor; If all the comparison results output from the above indicate that the corresponding test information and the expected value information correspond to each other, the word line is addressed. The semiconductor memory; and a decision circuit test result output determined to be normal. 2. The semiconductor memory according to claim 1, wherein the expected value information is test information or its inverted information.