JPH06204903A - Ari signal detecting circuit - Google Patents

Abstract

PURPOSE:To provide an ARI signal detecting circuit which can be constructed in a simple structure and at low cost by deleting the capacity that is unfavorable as an internal circuit of an IC. CONSTITUTION:An ARI signal detecting circuit consists of an SK signal detecting circuit 1 and a DK signal detecting circuit 5. The circuit 1 detects an SK signal out of an input signal by an SK signal detection means 2 and then extracts the DC component of the SK signal out of the detection output A of the means 2 through a 1st LPF 3. Then an SK signal deciding means 4 decides the SK signal input based on the output voltage B of the LPF 3. Meanwhile the circuit 5 detects a DK signal out of the output A of the means 2 by a DK signal detecting means 6. Then a DK signal deciding means 8 decides the DK signal input via a 2nd LPF 7. The bias voltage of the circuit 5 is set equal to the output voltage of the LPF 3.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an ARI (Autofahrer Ru
ndfunk Informations) signal detection circuit, and more particularly to a detection circuit for SK signal and DK signal included in ARI signal.

[0002]

2. Description of the Related Art ARI broadcasting is known as a part of a traffic information system for alleviating traffic congestion. AR
I broadcasting is mainly conducted in Germany and its neighboring countries, and the FM broadcasting station superimposes an identification signal modulated at a specific frequency on the radio wave for general broadcasting to determine the presence or absence of traffic information and the start / end of information provision. , Information on the target area, etc. can be provided. The ARI signal used for ARI broadcasting is SK signal and B as a subcarrier of 57 kHz.
It has identification signals of K signal and DK signal.

The SK signal is an identification signal of the ARI broadcasting station and is frequency-modulated and transmitted to the main carrier signal of each broadcasting station. It means that the broadcasting station transmitting the SK signal is broadcasting the traffic information. DK signal is 125Hz
Is an information identification signal of the subcarrier and is AM-modulated with a modulation degree of 30% to the SK signal as the subcarrier and transmitted. The DK signal is sporadically inserted between general program broadcasts such as music, news, etc., and enables discrimination between traffic information and general broadcasts. The user can recognize the start of traffic information broadcasting by detecting the DK signal. The BK signal is an area identification signal, and in order to accurately provide traffic information of a necessary area, a BK signal of a different frequency is assigned to each area divided into a plurality of areas. The frequencies of these BK signals are defined within the range of about 20 Hz to 50 Hz. Each BK signal is AM-modulated to a SK signal as a subcarrier with a modulation factor of 60% and transmitted.

FIG. 11 shows a block diagram of a conventional ARI signal detection circuit included in an ARI broadcast receiver. In the figure, S
Only the K signal detection circuit 50 and the DK signal detection circuit 55 are shown.

In the SK signal detection circuit 50, the SK detection PLL 51, which is the detection means, detects BK + from the input signal.
A 57 KHz SK signal including a DK signal is detected. From the detected output A, the low pass filter (LPF1) 52 extracts the DC component of the SK signal. In the SK signal determination circuit 53, the output B of the low pass filter 52 is changed to SK.
The presence or absence of signal input is determined and the result is output. Also,
The detection output A is input to the DK signal detection circuit 55 via the bypass capacitor 54. Similarly, in the DK signal detection circuit 55, the DK detection PLL 56 detects a 125 Hz DK signal, the low-pass filter (LPF2) 57 extracts the DC component of the DK signal from the detected output, and the DK signal determination circuit 58 detects the DK signal. Presence or absence of superimposition is determined and the result is output.

As shown in FIG. 12, the SK detecting PLL 5
The DC component is included in the envelope signal of the SK signal obtained in the synchronous detection of 1. In the DC component, the output of the low-pass filter 52 settles down near the reference voltage when the SK detection PLL 51 is not locked, but when locked, the voltage of the reference voltage + α is output. Further, when the circuit is configured so that the SK detection PLL 51 is locked on the opposite side, the voltage of the reference voltage −α is output. Therefore, DC
In order to input the detection output A having a varying component to the DK signal detection circuit 55, the DC component is deleted via the bypass capacitor 54 so as to reduce the problem of offset.

[0007]

However, in the above-mentioned conventional ARI signal detecting circuit, the SK signal detecting circuit and the DK signal detecting circuit are different from each other.
When the signal detection circuit is formed on an IC (semiconductor integrated circuit), not only the circuit scale becomes large due to the configuration of the bypass capacitor, but also the number of external pins is required to be two, and the output pin is restricted. There was a problem of high cost.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an ARI signal detection circuit which is simple and low-cost, in which a disadvantageous capacitor is eliminated as an internal circuit of an IC. .

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. In order to solve the above problems, the present invention, as shown in FIG. 1, is a circuit for detecting an ARI signal in which a traffic information and a DK signal for identifying a general broadcast are superimposed on a SK signal for identifying a broadcasting station that broadcasts the traffic information. That is, the SK signal detection means 2 for detecting the SK signal from the input signal, the first low-pass filter 3 for extracting the DC component of the SK signal from the output A of the SK signal detection means 2, and the first S for judging the SK signal from the output B of the low-pass filter 3
SK signal detection circuit 1 including K signal determination means 4, and SK
D for detecting the DK signal from the output A of the signal detecting means 2
K signal detection means 6, a second low-pass filter 7 for extracting the DC component of the DK signal from the output signal of the DK signal detection means 6, and a DK for determining the DK signal from the output of the second low-pass filter 7. In the ARI signal detection circuit including the DK signal detection circuit 5 including the signal determination means 8, the bias voltage of the DK signal detection circuit 5 is configured to be the output voltage of the first low pass filter 3.

In this case, the DK signal detection circuit 5 corresponds to the output C of the SK signal determination means 4 and the DK signal determination means 8
In addition, it is preferable that the reset means 9 for supplying the output B of the first low-pass filter 3 is provided.

[0011]

The output B of the first low pass filter 3 in the SK signal detection circuit 1 is an average of the output A of the SK signal detection means 2. The SK signal determination means 4 determines the reception of the SK signal when the voltage of the output B of the first low pass filter 3 exceeds the threshold level. The output voltage B of the first low pass filter 3 is set to the DK signal detection circuit 5
If the bias voltage is, the output A of the SK signal detection means 2
Even if a DC component is generated at, the bias voltage also moves in the same direction. Therefore, even if the output of the SK signal detection means 2 is directly input to the DK signal detection means 6 without passing through the bypass capacitor, offset does not relatively occur.
This simplifies the configuration and realizes a circuit configuration with a small offset voltage.

[0012]

The preferred embodiments of the present invention will be described below. First Embodiment FIG. 2 shows a block diagram of an ARI signal detection circuit according to a first embodiment of the present invention which is included in an ARI broadcast receiver.

As shown in FIG. 2, the input signal is an SK signal detecting means of the SK signal detecting circuit 11, and a SK detecting PL.
It is input to L12. The SK detection PLL 12 includes multipliers 12a and 12b, a loop filter 12c and a VCO.
The input signal is synchronously detected and quadrature detected by the multipliers 12a and 12b with a reference signal of 57 KHz. The synchronous detection output A is input to the low pass filter 13 to extract the DC component,
The SK signal determination circuit 14 determines whether or not a predetermined threshold level is exceeded. When the threshold level is exceeded, an "H" level signal is output as the SK detection signal.

The synchronous detection output A including the DK signal and the BK signal is input to the DK signal detection circuit 16 via the input resistor 15. In the DK signal detection circuit 16, the bandpass filter 17 separates the DK signal, and the separated signal is input to the DK detection PLL 18. In the DK detection PLL 18, the synchronous detection and the quadrature detection are performed by the 125 Hz reference signal, the synchronous detection output is input to the low-pass filter 19, the DC component is extracted, and the DK signal determination circuit 20 determines. As shown in the figure,
The bias voltage of the K signal detection circuit 16 is supplied with the voltage of the SK signal detection signal B output from the low-pass filter 13 of the SK signal detection circuit 11.

In this embodiment, with this configuration, it is not necessary to form a bypass capacitor in the input stage of the DK signal detection circuit, and when it is formed in an IC, its scale is reduced and one output pin is provided. And the circuit scale and cost are reduced. Furthermore, the input offset voltage is also greatly reduced. Second Embodiment FIG. 3 shows a block diagram of an ARI signal detection circuit according to a second embodiment of the present invention.

In the figure, the same parts as those in the first embodiment shown in FIG. 2 are designated by the same reference numerals, and their detailed description will be omitted. This embodiment is different from the first embodiment in that the SK signal detection means is configured to be shared with the RDS (Radio Data System) signal detection means, and the DK signal detection circuit 31 has a differential input stage. This is the point where the circuit 32 is configured.

The RDS signal is 57K same as the ARI signal.
Hz subcarrier enables digital
Data is transmitted by being multiplexed with the radio waves for general broadcasting of the broadcasting station. In broadcasting where compatibility with ARI signals is required, R
The DS signal and the ARI signal are always set in a quadrature relationship with each other and are transmitted simultaneously. Therefore, by demodulating the RDS signal, the ARI signal is also demodulated. Since the RDS signal is modulated so that the phase is inverted at the zero crossing point of the envelope of the subcarrier, it is not demodulated by a simple PLL. Therefore, demodulation is performed using a PLL such as an inverse modulation system, a frequency multiplication system, a remodulation comparison system, a differential detection system, or a Costas loop system.

In this embodiment, a Costas loop type PLL 33 is arranged in the input stage for detecting the ARI signal and the RDS signal. In the Costas loop type PLL33, VC
The input signal is in-phase and quadrature-coherently detected in the multipliers 33a and 33b by the 57 KHz reference signal output from the O33g. The two detected outputs are input to the exclusive OR circuit 33e, which is a phase comparator, via the low-pass filters 33c and 33d, respectively, and a phase comparison signal to the sequential loop filter 33f is generated by multiplication, and the control signal of the PLL is generated. I am trying. The ARI signal synchronously detected by the Costas loop type PLL 33 is DC
There are two stable points, and there is a 50% chance that both will be locked. In addition, this Costas loop type PLL33 is
When only the DS signal is used, the RDS signal is locked, and when the RDS + ARI signal is used, the ARI signal having consecutive subcarriers is locked. Therefore, when the ARI signal is input, the detection output of the ARI signal is always taken out from the in-phase synchronous detection output side which is the output of the multiplier 33a.

FIG. 4 shows the DK signal detection circuit 31 of this embodiment.
3 is a configuration diagram of the differential circuit 32 configured in the input stage of FIG. As shown in the figure, one of the inputs of the differential circuit 32 is connected to the in-phase synchronous detection output (BK + DK) of the Costas loop PLL 33.
+ Α) is input via the input resistor 15, and the output (BK + DK ′ + α) of the low-pass filter 13 is input to the other. Then, the output on the transistor side to which the output of the low-pass filter 13 is input is output to the DK detection PLL 18. The differential circuit 32 also serves as a bandpass filter for the DK signal. That is, although the BK and DK signal components are deleted by the low-pass filter 13, these signal components are not completely eliminated, and the DK signal component is mostly attenuated because its frequency is higher (DK '<DK). Therefore, the in-phase synchronous detection output (BK + DK + α) and the low-pass filter 1
The differential output from the output (BK + DK '+ α) of 3 is (BK + DK + α)-(BK + DK' + α) = DK-DK ', and as a result, the BK signal component is deleted. Therefore, the BK signal can be attenuated by making the input a differential input as in the present embodiment, and it is not necessary to configure a bandpass filter. In the Costas loop type PLL 33, there are two stable points for locking the SK signal. Therefore, the DC voltage for detecting the SK signal becomes ± α, but as shown in the above equation, the differential circuit 32 operates similarly even when the lock direction is reversed, and the PLL having the Costas loop configuration can be configured without any problem. It Third Embodiment FIG. 5 shows a block diagram of an ARI signal detection circuit according to a third embodiment of the present invention.

In the figure, the same parts as those in the second embodiment shown in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment differs from the first and second embodiments in that the DK signal detection circuit 41 includes an ON / OFF detection circuit 42 and a switch 43 as reset means. The ON / OFF detection circuit 42 outputs a reset signal to the switch 43 in response to the SK detection signal output from the SK signal determination circuit 14.
The reset signal is output at the rising and falling timings of the SK detection signal, as shown in FIG. In the switch 43, the switch is turned on by the reset signal,
The output of the low pass filter 13 for SK detection is supplied to the output of the low pass filter 19 for DK detection. As a result, the capacitor of the low-pass filter 19 is temporarily charged and erroneous detection of the DK signal is prevented.

The effects of this embodiment will be described with reference to FIGS. As shown in FIG. 7, the Costas loop type PLL3
The signal obtained by synchronously detecting the ARI signal by 3 is ±
It has either DC potential stable point of α, and settles to either when locked. However, once the lock is released due to noise or the like, it is not decided which side to lock next. Therefore, if the lock is frequently released due to multipath noise or the like, the synchronous detection output wanders between two DC potential stable points. Such a state is not preferable when the output voltage of the SK detection low-pass filter 13 is used as the bias voltage of the DK signal detection circuit 41. Therefore, if the circuit is configured to synchronously detect the DK signal at the DC potential on the −α side, for example, D
When the K signal is input, as shown in FIG.
The DK detection voltage output by the low-pass filter 19 for DK detection has a potential lower than the threshold level and D
The K signal determination circuit 20 determines this state and detects the DK signal.

However, when the DK signal is not input, the ARI signal detection circuit first detects from the SK signal, so the SK detection voltage output from the low-pass filter 13 rises when the SK signal is detected. Since the SK detection voltage is used as the bias voltage of the DK signal detection circuit 41, the bias voltage and the threshold level for detecting the DK signal also rise in the same manner as shown in FIG. At this time, the DK output from the low-pass filter 19
The detection voltage rises with a time constant of the low-pass filter 19 so as to slightly delay the movement of the threshold level. Therefore, although the DK signal is not input, there is a section in which the potential of the DK detection voltage falls below the threshold level, resulting in erroneous detection of the DK signal. Also, when the circuit is configured so that the DK signal is synchronously detected with the DC potential on the + α side, a section in which erroneous detection occurs similarly occurs.

Therefore, in this embodiment, the reset means is configured to detect the rising and falling edges of the SK detection signal output from the SK signal determination circuit 14, generate a reset signal at that timing, and set the DK detection voltage to the bias voltage. Reset to. As a result, as shown in FIG. 10, there is no delay in the rise of the DK detection voltage, and erroneous detection of the DK signal input is avoided.

[0024]

As described above, according to the ARI signal detection circuit of the present invention, the output voltage of the first low-pass filter is set to the bias voltage of the DK signal detection circuit, so that the output of the SK signal detection means is obtained. Even if a DC component is generated,
Since the bias voltage of the DK signal detection circuit also moves in the same direction, even if the output of the SK signal detection means is directly input to the DK signal detection means without passing through a bypass capacitor, offset does not occur relatively. Therefore, the circuit size can be reduced, the number of output pins of the IC can be reduced, and the cost can be reduced, and a circuit configuration with a small offset voltage can be realized.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an ARI signal detection circuit according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of an ARI signal detection circuit according to a second embodiment of the present invention.

FIG. 4 is a detailed diagram of a differential circuit configured in the second embodiment.

FIG. 5 is a configuration diagram of an ARI signal detection circuit according to a third embodiment of the present invention.

FIG. 6 is a timing chart of an SK detection signal and a reset signal in the third embodiment.

FIG. 7 is a signal waveform diagram illustrating a third embodiment.

FIG. 8 is a signal potential diagram for explaining the third embodiment.

FIG. 9 is a signal potential diagram for explaining erroneous detection of a DK signal.

FIG. 10 is a signal potential diagram for explaining the effect of the third embodiment.

FIG. 11 is a schematic block diagram of a conventional ARI signal detection circuit.

FIG. 12 is a signal waveform diagram illustrating detection output of an ARI signal.

[Explanation of symbols]

 1, 11 ... SK signal detection circuit 2 ... SK signal detection means 3 ... First low-pass filter (LPF) 4 ... SK signal determination means 5, 16, 31, 41 ... DK signal detection circuit 6 ... DK signal detection means 7 ... Second low-pass filter (LPF) 8 ... DK signal determination means 9 ... Reset means 12 ... SK detection PLL 13 ... Low-pass filter 14 ... SK signal determination circuit 15 ... Input resistance 17 ... Bandpass filter (BPF) 18 ... DK detection PLL 19 ... Low-pass filter 20 ... DK signal determination circuit 32 ... Differential circuit 33 ... Costas loop type PLL 42 ... ON / OFF detection circuit 43 ... Switch circuit

Claims (2)

[Claims] 1. An SK for identifying a broadcasting station that broadcasts traffic information.
A circuit for detecting an ARI signal in which a traffic information and a DK signal for general broadcast identification are superimposed on a signal, the SK signal detecting means detecting the SK signal from an input signal, and the SK signal from the output of the SK signal detecting means. Of D
A first low-pass filter for extracting a C component; and an SK signal detection circuit including an SK signal determination means for determining the SK signal from the output of the first low-pass filter; and an output of the SK signal detection means for the DK signal. Signal detecting means for detecting the DK signal, a second low-pass filter for extracting the DC component of the DK signal from the output signal of the DK signal detecting means, and a DK signal for determining the DK signal from the output of the second low-pass filter. D consisting of judgment means
An ARI signal detection circuit including a K signal detection circuit, wherein a bias voltage of the DK signal detection circuit is an output voltage of the first low-pass filter.
RI signal detection circuit. 2. The ARI signal detection circuit according to claim 1, wherein the DK signal detection circuit outputs the output of the first low-pass filter to the DK signal determination means in response to the output of the SK signal determination means. An ARI signal detection circuit comprising a resetting means for supplying.