DE4344789A1 - Signal detection circuit for broadcast road traffic information - Google Patents

Abstract

The circuit amplitude-modulates a 125 Hz data identification signal (DK) on a 57 kHz station identification signal (SK) and detects by a separate circuit (5), fed from the station identification signal detector (2) via a low-pass filter (3). The LP filter extracts the DC component and also provides an output for testing (4) the station identification.Another low-pass filter (7) extracts the DC component from the data identification signal for testing (8), subject to the output from a reset device (9) controlled by the station identification test result (C).

Description

1. Field of the Invention

The invention relates to an ARI (driver broadcasting informa tion) signal detection circuit, and relates in particular a detection circuit of an SK signal and a DK-Si signals contained in the ARI signal.

2. Description of the prior art

ARI broadcasting is one of the traffic information systems systems to accelerate the relief of traffic traffic jam known. The ARI broadcast is mainly in German country and its neighboring countries. An FM broadcasting company station overlaps a mod by a specific frequency lated identification signal on a radio wave of the general my radio, so that information such as the occurrence ner traffic information, the start and end of the informa tion supply and the object area are provided can. The ARI signal used for ARI broadcasting holds the SK signal as a 57 as identification signals kHz subcarrier, the BK signal and the DK signal.

The SK signal is the identification signal of the ARI radio station that is on the main signal carrier of each broadcasting station frequency modulated and transmitted. This means that the Broadcasting station that has broadcast the SK signal, the Ver transmits traffic information.

The DK signal is a 125 Hz information identification si gnal. The DK signal is set to 30% of the modulation rate SK signal AM-modulated and transmitted as an intermediate carrier. The DK signal is sporadic in the intervals of the general  Program broadcasts, such as music or news, inserted, so that it becomes possible to get traffic information and others distinguish between general transmissions. A user can the beginning of the transmission of traffic information, etc. detect the detection of the DK signal.

The BK signal is an area identification signal. To the Precise traffic information of a required area Deliver the BK signal frequency for each area is different, a variety of separate areas assigned. The frequencies of these BK signals are in one Range set from approximately 20 Hz to 50 Hz. Every BK Signal is on the SK signal as an intermediate carrier with 60% of the Modulation rate AM modulated and transmitted.

Fig. 11 shows a block diagram of a conventional ARI signal detection circuit built in the ARI broadcast receiver. Fig. 11 shows only a SK-signal detection circuit 50 and a DK signal detection circuit 55.

The SK signal detection circuit 50 detects the SK signal of 57 kHz including the BK + DK signal from the input signal by a SK-detecting PLL 51 , which is a wave detection device. The DC component of the SK signal is extracted by a low-pass filter 52 (LPFI) from a wave detection output A. A SK signal test circuit 53 checks the presence of the input of the SK signal at an output B of the low-pass filter 52 , and outputs the result. Furthermore, the wave detection output A is given to a DK signal detection circuit 55 by a shunt capacitance (capacitor) 54 .

By means of a DK-detecting PLL 56, the DK signal detection circuit 55 detects a 125 Hz DK signal in a similar manner. The DC component of a DK signal is extracted by a low-pass filter 57 (LPF2) from the wave detection output. The presence of a superimposition of the DK signal is checked by a DK signal test circuit 58 , and the result is output. A bias circuit 59 biases the DK signal detection circuit 55 .

As shown in Fig. 12, the DC component is included in the envelope signal of the SK signal, which he will keep by the synchronous wave detection of the SK-detecting PLL 51 . In the state in which the SK-detecting PLL 51 does not engage, this DC component is in the vicinity of the standard voltage of the output of the low-pass filter 52 . In the state in which the SK-detecting PLL 51 engages, this DC voltage component is output as the voltage of the standard voltage + α. On the other hand, if the circuit is designed so that the SK-detecting PLL 51 snaps in on the opposite side, this DC component is output as the voltage formed from the standard voltage - α. In order to enter the wave detection output A, whose DC voltage component changes in this way, into the DK signal detection circuit 55 , the ARI signal detection circuit is therefore designed to reduce the problems of the offset by deleting the DC component through the shunt capacitance 54 becomes.

The above-mentioned conventional ARI signal detection circuit however, has the following problems. In the event that the SK Signal detection circuit and the DK signal detection scarf device on an IC (e.g. an integrated semiconductor switch circle) are formed, namely the circuit scope because of the formation of the shunt capacity large, and two Pins are numbered on the outside Pins necessary with the result of this limitation of Starting pens and high cost.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to ARI signal detection circuit to create the previous imagined disadvantageous shunt capacitance as an internal Circuit of the IC's does not have and the low Ko can be easily manufactured.

A basic block diagram of the present invention is shown in FIG. 1.

The above object of the present invention can be achieved by an ARI signal detection circuit shown in FIG. 1 for detecting an ARI signal, in which a DK signal for distinguishing between first information such as traffic information and second information such as one Information from other general transmissions is superimposed on a SK signal for identification of a radio station which transmits the traffic information. The ARI signal detection circuit has a SK signal detection circuit 1 and a DK signal detection circuit 5 .

The SK signal detection circuit 1 comprises: a SK signal detection device 2 for detecting the SK signal from an input signal: a first low-pass filter (LPF) 3 for extracting the DC component of the SK signal from an output A of the SK signal detection device 2 : and an SK signal test device 4 for testing the SK signal in an output B of the first low-pass filter 3 .

The DK signal detection circuit 5 comprises: a DK signal detection device 6 for detecting the DK signal from the output A of the SK signal detection device 2 : a second low-pass filter (LPF) 7 for extracting the DC component of the DK signal from the output signal of the DK Signal detection device 6 : and a DK signal test device 8 for testing the DK signal in an output of the second low-pass filter 7 .

The voltage of the output B of the first low-pass filter 3 is used as a bias for the DK signal detection circuit 5 ver.

In this case, the DK signal detection circuit 5 is preferably provided with a reset device 9 in order to supply the output B of the first low-pass filter 3 to the DK signal test device 8 in accordance with an output C of the SK signal test device 4 .

The output B of the first low-pass filter 3 in the SK signal detection circuit 1 is the mean value of the output A of the SK signal detection device 2 . If the voltage of the output B of the first low-pass filter 3 exceeds a predetermined threshold level, the SK signal checking device 4 checks the reception of the SK signal. By using the voltage of the output B of the first low-pass filter 3 as bias voltage of the DK signal detection circuit 5 , the voltage moves in the same direction as the generated DC component, even if the DC component is generated in output A of the SK signal detection device 2 . Therefore, the offset is not generated relatively even if the output of the SK signal detection device 2 is directly input to the DK signal wave detection device 6 without the intermediate shunt capacitance. Since the arrangement of the circuit is simplified, the circuit arrangement being realized with a small offset voltage.

The nature, usability and other idiosyncrasies of this Er will be found from the following detailed description the preferred embodiment of the invention,  if these together with the briefly described below, accompanying drawings is read.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram of the present invention;

Fig. 2 is a block diagram of an ARI signal detecting TIC of a first embodiment according to the present invention;

Fig. 3 is a block diagram of an ARI signal detecting TIC a second embodiment according to the present invention;

Fig. 4 is a detailed block diagram of a differential circuit formed in the second embodiment;

Fig. 5 is a block diagram of an ARI signal detecting TIC of a third embodiment according to the present invention.

Fig. 6 is a timing chart of an SK detection signal and a reset signal of the third embodiment;

Fig. 7 is a diagram of the signal waveform which explains the third embodiment:

Fig. 8 is a signal voltage diagram explaining the third embodiment:

Fig. 9 is a signal voltage diagram illustrating the erroneous detection of a DK signal:

Fig. 10 is a signal voltage diagram explaining the effect of the third embodiment;

Fig. 11 is a block diagram of the scope of an ARI signal detection circuit: and

Fig. 12 is a signal waveform diagram explaining a wave detection output of an ARI signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

With reference to the accompanying drawings explains an embodiment of the present invention.

First embodiment

Fig. 2 shows a block diagram of an ARI signal detection circuit of the first embodiment according to the present invention, which is arranged in an ARI broadcast receiver.

In FIG. 2, an ARI signal detecting circuit includes an SK signal detection circuit 11 and a DK signal detection circuit 16.

The SK signal detection circuit 11 is provided with a SK-detec ting PLL 12 , a low-pass filter 13 , a SK signal test circuit 14 and an input resistor 15 . The SK-detecting PLL 12 includes Muliplizierer 12 a and 12 b, a loop filter 12 c, and a VCO (voltage control oscillator ligand) 12 d.

The DK signal detection circuit 16 is provided with a bandpass filter (BPF) 17 , a DK-detecting PLL 18 , a low-pass filter (LPF2) 19 and a DK signal test circuit 20 . The DK-detecting PLL 18 comprises multipliers 18 a and 18 b, a loop filter 18 c and a VCO 18 d.

As shown in FIG. 2, an input signal is input to the SK-detecting PLL 12 . The input signal is synchronously and orthogonally detected by the multipliers 12 a and 12 b of the SK-detecting PLL 12 on the basis of a 57 kHz standard signal. The synchronous detection output A is given in the low-pass filter 13 and its DC voltage component is extracted. The SK signal test circuit 14 checks whether this output A exceeds a predetermined threshold level or not. If it exceeds the threshold level, an "H" level signal is output as the SK detection signal.

On the other hand, the synchronous detection output A having the DK signal and the BK signal is input to the DK signal detection circuit 16 through the input resistor 15 . The DK signal is separated by the bandpass filter 17 in the DK signal detection circuit 16 , and this separated signal is entered into the DK-detecting PLL 18 . Then it is detected synchronously and orthogonally on the basis of a 125 Hz standard signal in the DK-detecting PLL 18 . The synchronous detection output is input to the low-pass filter 19 , and the DC component is extracted, which is checked by the DK signal checking circuit 20 . As shown in FIG. 2, the voltage of the signal B for detection of the SK signal, which is output by the low-pass filter 13 of the SK signal detection circuit 11 , is used as a bias of the DK signal detection circuit 16 .

In the present embodiment, by the training in this way, it is not necessary to provide a shunt capacitance in the input stage of the DK signal detection circuit 16 . Therefore, in the case of their manufacture on an IC, the size range can be reduced and the number of pins can be exactly one. The reduction in the circuit size and circuit cost can be promoted, while the input offset voltage can also be reduced to a large extent.

Second embodiment

Fig. 3 shows a block diagram of an ARI signal detection circuit of the second embodiment according to the present invention.

In Fig. 3, the same constitutional elements as those in the first embodiment of Fig. 2 carry the same reference numerals and the detailed explanations thereof are omitted. The point of the second embodiment that differs from that of the first is as follows. The SK signal detection device is namely generally used as a detection device for detecting an RDS (radio data system), and a differential circuit 32 is arranged at the input stage of a DK signal detection circuit 31 .

The RDS signal is multiplexed by digital data Channel selection etc. on the general broadcast radio wave of the Broadcast station by using a 57 kHz intermediate carrier formed in the same way as the ARI signal and then transferred. In the broadcast, in which a knockout existence with the ARI signal is required, the RDS-Si signal and the ARI signal always in an orthogonal phase drawing to each other and transmitted at the same time. Therefore becomes the ARI signal with the demodulation of the RDS signal also demodulated. The RDS signal cannot be transmitted through a simple PLL can be demodulated because the RDS signal is so mod is that the phase at the zero point crossing of the envelope curve of the intermediate carrier is inverted. For this reason be for PLL's demodulation, like a reverse modulation procedure, a frequency multiplication procedure, a re modulation comparative method, a delay wave  Detection method and a Costas loop method ver turns.

In the second embodiment, the input stage is provided with a Costas loop type PLL 33 to detect the ARI signal and the RDS signal. Based on the 57 kHz standard signal output by the VCO 33 g, the PLL 33 of the Costas loop type carries out the synchronous and orthogonal detections with respect to the input signals by the multipliers 33 a and 33 b. The two wave detection outputs are entered through low-pass filters (LPF1) 33 c and (LPF2) 33 d accordingly in an exclusive "OR" circuit 33 e, which acts as a phase comparator. A phase comparison signal for the sequential loop filter 33 f is generated by the multiplier calculation and used as a control signal of the PLL. The ARI signal, which is detected synchronously by the PLL 33 of the Costas loop type, has two DC stabilized points, each of which latches with a probability of 50%. In the case of only one RDS signal, the PLL 33 of the Costas loop type latches with respect to the RDS signal. In the case of the RDS + ARI signal, the PLL 33 of the Costas loop type latches with respect to the ARI signal, which has a continuous subcarrier. Therefore, when the ARI signal is input, the wave detection output of the ARI signal is always taken out from the side of the in-phase and synchronized wave detection output, which is the output of the multiplier 33 a.

FIG. 4 shows a block diagram of the differential circuit 32 provided at the input stage of the DK signal detection circuit 31 of the present embodiment. As shown in FIG. 4, the in-phase and synchronized wave detection output (BK + DK + α) of the PLL 33 of the Costas loop type is given by the input resistor 15 on one side of the input of the differential circuit 32 . The output (BK + DK '+ α) of the low-pass filter 13 is given on the other side of the input of the differential circuit 32 . And the output of the transistor, to which the output of the low-pass filter 13 is given, is given to the DK-detect the PLL 18 . This differential circuit 32 also serves as a bandpass filter of the DK signal. Although the component of the BK and DK signals is deleted by the low-pass filter 13 , the component of these signals is not completely deleted. Since the frequency of the DK signal component is higher, it is almost suppressed (DK ′ <DK). Therefore, the differential output of the in-phase and synchronized wave detection output (BK + DK + α) and the output (BK + DK '+ α) of the low-pass filter 13 is as follows.

(BK + DK + α) - (BK + DK ′ + α) = DK - DK ′.

As a result, the BK signal component is deleted. Therefore, by using the differential input as the input of the present embodiment, it is possible to suppress the BK signal, and it is not necessary to construct a bandpass filter. In addition, there are two stabilized points for locking the SK signal in the PLL 33 of the Costas loop type. Although the DC voltage becomes SK α signal detection ± α, even if the direction of engagement is reversed, the differential circuit 32 behaves similarly as explained above, so that the PLL of the Costas loop type can be used with no difficulty.

Third embodiment

Fig. 5 is a block diagram of an ARI detection circuit showing the third embodiment according to the present invention.

In Fig. 5, the same constitutional elements as those in the second embodiment of Fig. 3 have the same reference numerals and their detailed explanation is omitted. The point of the third embodiment different from the first and second embodiments is as follows. Namely, an ON / OFF detection circuit 42 and a switch 43 are designed as a reset device in the DK signal detection circuit 41 . The ON / OFF detection circuit 42 is designed so that a reset signal is output to the switch 43 in accordance with the SK-detected signal output from the SK signal test circuit 14 . The reset signal is output by clocking the rise and fall of the SK-detected signal, shown in FIG. 6. The switch 43 is switched on by the reset signal in order to supply the output of the low-pass filter 19 for the DK detection with the output of the low-pass filter 13 for the SK detection. Therefore, the capacitor of the low-pass filter 19 is temporarily charged, so that an erroneous detection of the DK signal is prevented.

The effect of the present embodiment will be explained below with reference to Figs. 7 to Fig. 10.

As shown in Fig. 7, the signal obtained by the synchronous detection of the ARI signal by the PLL 33 of the Costas loop type has the DC stabilizing point at + or - α, and when it is locked, is placed on one of them . However, if the snapping is lost due to noise, etc., it is not certain which side the signal snaps into afterwards. Therefore, if it happens that latching is often lost due to multi-pass noise, etc., the synchronous detection output travels back and forth between the two DC stabilized points. This water state is not desirable in the event that the output voltage of the low-pass filter 13 is used for the SK detection as a bias of the DK-Si signal detection circuit 41 . For this reason, a circuit is formed to synchronously detect the DK signal by the DC voltage on the, for example, α side, so that the DK detection voltage output by the low-pass filter 19 for the DK detection drops to a value less than the threshold level, when the signal is input as in Fig. 8 and the DK signal checking circuit 20 checks this state to detect the DK signal.

If the DK signal is not input, however, the ARI signal detection circuit first detects the SK signal so that the SK detection voltage, which is the output of the low-pass filter 13 , rises at the time of detection of the SK signal. Since the SK detection voltage is used as the bias of the DK signal detection circuit 41 shown in Fig. 9, the bias and the threshold level for detection of the DK signal are coupled to each other to rise in the same manner. At this time, the DK detection voltage, which is the output of the low-pass filter 19 , rises a little later than the movement of the threshold level due to the time constants of the low-pass filter 19 . Therefore, although the DK signal is not input, an interval is generated in which the DK detection voltage drops to a lower value than the threshold level, so that an erroneous detection of the DK signal can occur. Furthermore, even if the circuit is designed to synchronously detect the DK signal by the DC voltage on the + α side, such an interval is also generated in which an erroneous detection of the DK signal can occur.

Therefore, in the present embodiment, the reset device is prepared so that the rise and fall of the SK detection signal output from the SK signal test circuit 14 are detected so that the reset signal is generated by the detected timing, and that the DK detection voltage is set to the bias. Therefore, as shown in FIG. 10, the delay in rising the DK detection voltage is avoided, and the erroneous detection of the DK signal input can be avoided.

As described in detail above, moves according to the ARI signal detection circuit of the present invention Biasing of the DK signal detection circuit by the Ver the output voltage of the first low-pass filter as Bias the DK signal detection circuits in the same Direction even if the DC component for the Output of the SK signal detection device is generated. Even if the output of the SK signal detection device directly to the DK signal wave detection device without the intermediate shunt capacitance is given the offset is not generated relatively. This makes it possible the circuit size, the number of output pins of the IC and reduce the cost of a circuit design tion can be realized with a small offset voltage.

The invention can be implemented in other specific embodiments be embodied without losing its content or essential Characteristics. The present execution All parts of the form are therefore only illustrative and not to be considered as limiting, the scope of the inven by the appended claims instead of the foregoing Genes description is given and all changes made in Are within the meaning and equivalency of the claims, will therefore be considered as encompassed here.

Claims (10)

1. ARI signal detection circuit for detecting an ARI signal, in which a DK signal for differentiating first information and second information is superimposed on an SK signal for identifying a radio station which transmits the first information, the ARI signal detecti has a SK signal detection circuit ( 1 , 11 ) and a DK signal detection circuit ( 5 , 16 , 31 , 41 ), characterized in that
the SK signal detection circuit is provided with: a SK signal detection device ( 2 , 12 , 33 ) for detecting the SK signal from an input signal: a first low-pass filter ( 3 , 13 ) for extracting the DC voltage component of the SK signal from an output ( A) the SK signal detection device; and a SK signal test device ( 4 , 14 ) for testing the SK signal of an output (B) of the first low-pass filter,
that the DK signal detection circuit is provided with: a DK signal detection device ( 6 , 18 ) for detecting the DK signal from the output (A) of the SK signal detection device; a second low-pass filter ( 7 , 19 ) for extracting the DC component of the DK signal from an output signal of the DK signal detection device; and a DK signal test device ( 8 , 20 ) for testing the DK signal in an output of the second low-pass filter, and
wherein the voltage of the output (B) of the first low-pass filter is used as a bias of the DK signal detection circuit. 2. ARI signal detection circuit according to claim 1, characterized characterized in that the first information is a traffic information  mation, and that the second information is an informa tion of other general broadcast transmissions. 3. ARI signal detection circuit according to claim 1 or 2, characterized in that the SK signal test device ( 4 , 14 ) checks receipt of the SK signal when the voltage of the output (B) of the first low-pass filter ( 3 , 13 ) a vorbe agreed threshold level exceeds. 4. ARI signal detection circuit according to one of claims 1 to 3, characterized in that the SK signal detection device ( 12 , 33 ) has a PLL for performing synchronous and orthogonal detections of the input signal on the basis of a standard signal with a predetermined frequency. 5. ARI signal detection circuit according to one of claims 1 to 4, characterized in that the DK signal detection device ( 18 ) has a PLL for performing synchronous and orthogonal detections of the output (A) of the SK signal detection device ( 2 , 12 , 33 ) on the basis of a standard signal with a predetermined frequency. 6. ARI signal detection circuit according to one of claims 1 to 5, characterized in that a BK signal for identi fication of an area is superimposed on the SK signal, and that the DK signal detection circuit ( 16 ) further with a bandpass filter ( 17 ) for Separation of the DK signal from the BK signal is provided. 7. ARI signal detection circuit according to one of claims 1 to 6, characterized in that the ARI signal detection circuit further comprises a differential circuit ( 32 ) at the input stage of the DK signal detection circuits ( 31 ). 8. ARI signal detection circuit according to one of claims 1 to 7, characterized in that the SK signal detection device ( 33 ) is designed to detect both an RDS signal and the SK signal, the RDS signal and the ARI Signal have an orthogonal phase relationship to one another and are transmitted simultaneously. 9. ARI signal detection circuit according to claim 8, characterized in that the SK signal detection device ( 33 ) either a PLL of the Costas loop type, or a PLL of the reverse modulation type or a PLL of a frequency multiplication type, or a PLL comparing the remodulations or a delay wave detection PLL for detection of the SK signal and the RDS signal. 10. ARI signal detection circuit according to one of claims 1 to 9, characterized in that the DK signal detection circuit ( 5 , 41 ) further with a reset device ( 9 , 42 , 43 ) for supplying the output (B) of the first low-pass file ters ( 3 , 13 ) to the DK signal test device ( 8 , 20 ) accordingly an output (C) of the SK signal test device ( 4 , 14 ) is provided.