JPH06204763A - High input impedance circuit and time constant circuit using the same - Google Patents

High input impedance circuit and time constant circuit using the same

Info

Publication number
JPH06204763A
JPH06204763A JP4360800A JP36080092A JPH06204763A JP H06204763 A JPH06204763 A JP H06204763A JP 4360800 A JP4360800 A JP 4360800A JP 36080092 A JP36080092 A JP 36080092A JP H06204763 A JPH06204763 A JP H06204763A
Authority
JP
Japan
Prior art keywords
circuit
time constant
signal processing
input impedance
high input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4360800A
Other languages
Japanese (ja)
Inventor
Satoru Ishii
哲 石井
Hiroshi Kondo
浩史 近藤
Akira Ishizuka
公 石塚
Yasushi Kaneda
泰 金田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP4360800A priority Critical patent/JPH06204763A/en
Publication of JPH06204763A publication Critical patent/JPH06204763A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain inexpensively a high input impedance circuit and the time constant circuit using it with simple configuration and small circuitry. CONSTITUTION:The high impedance circuit is provided with 1st and 2nd passive elements R1, R2 connected in series between a signal source 1 and a reference DC voltage source E, a signal processing circuit 4 whose input terminal connects to the signal source, and a 3rd passive element R3 connected between an output terminal 3 of the signal processing circuit 4 and a connecting part between the 1st and 2nd passive elements R1, R2. The high impedance circuit is formed by the simple and small sized configuration.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高入力インピーダンス回
路とこれを用いた時定数回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high input impedance circuit and a time constant circuit using the same.

【0002】[0002]

【従来の技術】通常の非反転増幅回路では、入力抵抗値
はバイアス抵抗の値で決まることが多い。その一例を図
12に示す。図12において、1は入力端子、2は非反
転入力端子を入力端子1に接続した演算増幅器、3は出
力端子、R11は入力端子1と基準直流電圧源であるア
ースE間に接続したバイアス抵抗器、R12は演算増幅
器2の反転入力端子とアースE間に接続した抵抗、R1
3は演算増幅器2の反転入力端子と出力端子間に接続し
た抵抗である。
2. Description of the Related Art In a typical non-inverting amplifier circuit, the input resistance value is often determined by the bias resistance value. An example thereof is shown in FIG. In FIG. 12, 1 is an input terminal, 2 is an operational amplifier in which a non-inverting input terminal is connected to the input terminal 1, 3 is an output terminal, and R11 is a bias resistor connected between the input terminal 1 and the ground E which is a reference DC voltage source. , R12 is a resistor connected between the inverting input terminal of the operational amplifier 2 and the ground E, R1
Reference numeral 3 is a resistor connected between the inverting input terminal and the output terminal of the operational amplifier 2.

【0003】上記の構成により、演算増幅器2の入力抵
抗が非常に大きい(FET入力であれば、ほぼ無限大と
みなすことができる)と、この非反転増幅回路の入力抵
抗値はバイアス抵抗R11の抵抗値に等しい。
With the above configuration, if the input resistance of the operational amplifier 2 is very large (if it is a FET input, it can be regarded as almost infinite), the input resistance value of this non-inverting amplifier circuit is that of the bias resistor R11. Equal to resistance.

【0004】上記非反転増幅回路では、図13に示すよ
うに、キャパシタC1を入力端子1とバイアス抵抗R1
1の一端との間に接続して、時定数C1・R11で決ま
るカットオフ周波数を有するハイパスフィルタを構成す
ることができる。
In the above non-inverting amplifier circuit, as shown in FIG. 13, the capacitor C1 is connected to the input terminal 1 and the bias resistor R1.
A high-pass filter having a cutoff frequency determined by the time constants C1 and R11 can be configured by connecting it to one end.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、図13
に示すハイパスフィルタの低域カットオフ周波数fは、 f=1/(2πC1R11) ・・・(1) の式により与えられるため、低域カットオフ周波数fを
10kHzに設定しようとすると、時定数C1・R11
はおよそ16μsとなる。仮に、R11=1MΩの場合
はC1≒16pF、R11=100kΩの場合はC1≒
160pFという値が必要となる。
However, as shown in FIG.
Since the low-pass cutoff frequency f of the high-pass filter shown in is given by the formula of f = 1 / (2πC1R11) (1), when the low-pass cutoff frequency f is set to 10 kHz, the time constant C1・ R11
Is about 16 μs. If R11 = 1 MΩ, then C1≈16 pF, and if R11 = 100 kΩ, C1≈16 pF.
A value of 160 pF is needed.

【0006】したがって、非反転増幅回路をディスクリ
ート部品で構成する場合には特に支障はないが、集積回
路上でこの時定数を実現するには、抵抗、キャパシタの
両方またはいずれかが非反転増幅回路全体の何倍もの広
大な面積を占有し、チップサイズがきわめて大きくなっ
てしまう。
Therefore, there is no particular problem when the non-inverting amplifier circuit is composed of discrete components, but in order to realize this time constant on the integrated circuit, either or both of the resistor and the capacitor are non-inverting amplifier circuits. It occupies a vast area that is many times larger than the whole, and the chip size becomes extremely large.

【0007】そこで、このような場合、従来はキャパシ
タを外付けとすることが一般的であったが、これでは集
積回路化の利点がかなり損なわれてしまうという問題点
があった。
Therefore, in such a case, conventionally, it was general that the capacitor is externally attached, but this has a problem that the advantage of the integrated circuit is considerably impaired.

【0008】本発明は上記のような問題点を解消した高
入力インピーダンス回路とこれを用いた時定数回路を簡
単な構成で小形かつ安価に得ることを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to obtain a high input impedance circuit and a time constant circuit using the high input impedance circuit, which solves the above problems, with a simple structure, in a small size and at a low cost.

【0009】[0009]

【課題を解決するための手段】本発明は下記の構成から
なることを特徴とする高入力インピーダンス回路とこれ
を用いた時定数回路である。
The present invention is a high input impedance circuit having the following configuration and a time constant circuit using the same.

【0010】(1)信号源と基準直流電圧源との間に直
列に接続された第1および第2の受動素子と、前記信号
源を入力端子に接続した信号処理回路と、信号処理回路
の出力端子と前記第1および第2の受動素子の接続部と
の間に接続された第3の受動素子とを備えたことによ
り、大きな値のインピーダンス素子を使用することな
く、高入力インピーダンス回路を実現したものである。
(1) First and second passive elements connected in series between a signal source and a reference DC voltage source, a signal processing circuit in which the signal source is connected to an input terminal, and a signal processing circuit By providing the third passive element connected between the output terminal and the connection portion of the first and second passive elements, a high input impedance circuit can be realized without using an impedance element having a large value. It was realized.

【0011】(2)信号源と基準直流電圧源との間に直
列に接続された第1および第2の受動素子と、前記信号
源を入力端子に接続した信号処理回路と、この信号処理
回路の出力端子と前記第1および第2の受動素子の接続
部との間に接続された第3の受動素子とを備え、前記第
1、第2、第3の受動素子が抵抗である上記高入力イン
ピーダンス回路の等価抵抗値とで時定数を得るキャパシ
タとを備えたことにより、大きな時定数をもつ時定数回
路を実現したものである。
(2) First and second passive elements connected in series between a signal source and a reference DC voltage source, a signal processing circuit in which the signal source is connected to an input terminal, and this signal processing circuit And a third passive element connected between the output terminal of the first passive element and the connection portion of the first and second passive elements, wherein the first, second and third passive elements are resistors. A time constant circuit having a large time constant is realized by providing a capacitor that obtains a time constant with the equivalent resistance value of the input impedance circuit.

【0012】[0012]

【実施例】実施例1 以下、本発明の実施例を図面について説明する。図1は
本発明の実施例を示す。本実施例が前記図12に示す従
来例と異なる点は、演算増幅器2の非反転入力端子と基
準直流電圧源としてのアースE間にバイアス抵抗器R1
1を設ける代りに信号処理回路としてのバイアス回路5
を設けたものである。このバイアス回路5は図2に示す
ように、信号源である入力端子1とアースE間に直列に
接続された抵抗R1およびR2と、上記入力端子1に入
力端子を接続した増幅回路4と、この増幅回路4の出力
端子と前記直列抵抗R1、R2の接続点に接続した抵抗
R3とで構成されている。
Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The present embodiment differs from the conventional example shown in FIG. 12 in that a bias resistor R1 is provided between the non-inverting input terminal of the operational amplifier 2 and the earth E as a reference DC voltage source.
Bias circuit 5 as a signal processing circuit instead of providing 1
Is provided. As shown in FIG. 2, the bias circuit 5 includes resistors R1 and R2 connected in series between an input terminal 1 which is a signal source and an earth E, an amplifier circuit 4 in which the input terminal is connected to the input terminal 1. It is composed of an output terminal of the amplifier circuit 4 and a resistor R3 connected to the connection point of the series resistors R1 and R2.

【0013】次に上記実施例1の作用について説明す
る。入力端子1の入力電圧をV1、増幅回路4の増幅度
をA、抵抗R1を流れる電流をi1、抵抗R3を流れる
電流をi3とすると、 V1=R1i1+R2(i1+i3) ・・・(2) AV1=R3i3+R2(i1+i3)・・・(3) となる。なお、増幅回路4の入力抵抗は無限大と仮定し
ている(FET入力であればほぼ無限大とみなすことが
できる)。
Next, the operation of the first embodiment will be described. Assuming that the input voltage of the input terminal 1 is V1, the amplification degree of the amplifier circuit 4 is A, the current flowing through the resistor R1 is i1, and the current flowing through the resistor R3 is i3, V1 = R1i1 + R2 (i1 + i3) (2) AV1 = R3i3 + R2 (i1 + i3) ... (3). The input resistance of the amplifier circuit 4 is assumed to be infinite (although it can be considered to be infinite if it is an FET input).

【0014】これにより、入力抵抗Rin=V1/i1
は、
As a result, the input resistance Rin = V1 / i1
Is

【0015】[0015]

【数1】 と計算される。[Equation 1] Is calculated.

【0016】例えば、A=1のときを想定すると、 Rin=R1+R2+R1R2/R3 ・・・(5) となり、抵抗R3の値を選定することによって、入力抵
抗Rinは、論理上、最小で(R1+R2)、最大で無
限大までの所望の値に設定することができるので、高入
力抵抗回路を実現することができる。
For example, assuming that A = 1, Rin = R1 + R2 + R1R2 / R3 (5), and the input resistance Rin is theoretically the minimum (R1 + R2) by selecting the value of the resistance R3. Since it can be set to a desired value up to infinity, a high input resistance circuit can be realized.

【0017】また、(4)式より、Aを1より大きく設
定した場合には、分母の(1−A)R2が負になるた
め、通常は抵抗R3を大きく設定する必要がある。
Further, from the equation (4), when A is set to be larger than 1, the denominator (1-A) R2 becomes negative, so that it is usually necessary to set the resistance R3 large.

【0018】実施例2 図3は上記の高入力抵抗回路を用いて低域阻止フィルタ
を構成した例を示すもので、基本的には前記図13に示
す従来回路のバイアス抵抗R11を上記バイアス回路5
に置き換えたものである。本実施例ではバッファ回路と
して演算増幅器6によるボルテージフォロワ(利得A=
1)を用いている。ここで、たとえば、抵抗R1,R
2,R3を、 R1=R2=2kΩ、R3=1Ω に設定すれば、前記(5)式よりRin=4.004M
Ωとなる。この結果、カットオフ周波数fを10kHz
にするためのキャパシタC1は、約4pFですむことに
なり、抵抗、キャパシタとも大きな値が不必要となるた
め、集積回路内でこれらの素子が大きな面積を占めるよ
うなことはなくなる。バッファ回路はゲイン1で十分な
ので、図4のような簡単で基本的な回路構成の集積化演
算増幅器でよく、チップ内の占有面積は大きくならな
い。換言すれば、集積回路に適した構成であるというこ
とができる。
Embodiment 2 FIG. 3 shows an example in which a low-pass filter is constructed by using the above high input resistance circuit. Basically, the bias resistor R11 of the conventional circuit shown in FIG. 13 is basically the above bias circuit. 5
Is replaced with. In this embodiment, a voltage follower (gain A =
1) is used. Here, for example, the resistors R1 and R
If R2 and R3 are set to R1 = R2 = 2 kΩ and R3 = 1Ω, then Rin = 4.004 M from the equation (5).
It becomes Ω. As a result, the cutoff frequency f is set to 10 kHz.
The capacitor C1 for achieving the above need only be about 4 pF, and since a large value is unnecessary for both the resistor and the capacitor, these elements do not occupy a large area in the integrated circuit. Since a gain of 1 is sufficient for the buffer circuit, an integrated operational amplifier having a simple and basic circuit configuration as shown in FIG. 4 may be used, and the occupied area in the chip does not increase. In other words, it can be said that the configuration is suitable for an integrated circuit.

【0019】なお、R3=0の場合、回路構成がより簡
単なので、利用価値が高い。 実施例3 上記の各実施例においては、各受動素子を抵抗とした場
合を示したが、一般的には図5のようにそれぞれインピ
ーダンスZ1,Z2,Z3を有する受動素子と増幅器4
とでバイアス回路5を構成しても、その入力インピーダ
ンスは前記(4)式と同様に、
When R3 = 0, the circuit configuration is simpler and the utility value is high. Embodiment 3 In each of the above embodiments, the case where each passive element is a resistance is shown, but generally, as shown in FIG. 5, the passive element and the amplifier 4 having impedances Z1, Z2 and Z3, respectively.
Even if the bias circuit 5 is configured by and, the input impedance thereof is the same as in the equation (4),

【0020】[0020]

【数2】 となり、高入力インピーダンス回路を実現することがで
きる。たとえば各受動素子にインダクタを使用すれば、
高入力インダクタンス回路となる。
[Equation 2] Therefore, a high input impedance circuit can be realized. For example, if you use an inductor for each passive element,
It becomes a high input inductance circuit.

【0021】このような高入力インピーダンス回路が有
効な装置の一つとして、レーザードップラ速度センサが
挙げられる。このレーザードップラ速度センサでは、受
光信号は図6のように、直流成分Dの上に所望の信号成
分Sが重畳された形になる。通常、被測定物は散乱光が
多いため、直流成分Dが大きく信号成分Sは相対的に小
さい。このため、次段でこのまま増幅すると、直流成分
で増幅回路が飽和してしまうことになり、段間には低域
阻止フィルタを設けることが必要となる。
A laser Doppler velocity sensor is one of the devices in which such a high input impedance circuit is effective. In this laser Doppler velocity sensor, the received light signal has a form in which the desired signal component S is superimposed on the DC component D, as shown in FIG. Usually, since the DUT has a large amount of scattered light, the DC component D is large and the signal component S is relatively small. For this reason, if amplification is performed in the next stage as it is, the amplification circuit will be saturated with the DC component, and it is necessary to provide a low-frequency blocking filter between the stages.

【0022】図7は本発明の高入力インピーダンス回路
をレーザードップラ速度センサに適用した回路例を示す
もので、フォトダイオードD1で受光された信号は、差
動増幅回路11および抵抗R4で電圧に変換され、その
出力端子aには図8に示すような信号が得られる。な
お、抵抗R4と並列に接続されたコンデンサC2は高周
波での安定性を確保するために付加されている。
FIG. 7 shows an example of a circuit in which the high input impedance circuit of the present invention is applied to a laser Doppler velocity sensor. The signal received by the photodiode D1 is converted into a voltage by the differential amplifier circuit 11 and the resistor R4. Then, a signal as shown in FIG. 8 is obtained at the output terminal a. The capacitor C2 connected in parallel with the resistor R4 is added to ensure stability at high frequencies.

【0023】上記差動増幅回路11の出力端子に前記図
2に示す低域阻止フィルタ回路をそのまま接続すること
によって、出力端子3には図9のように低域成分を除い
た信号を得ることができる。
By connecting the low-frequency blocking filter circuit shown in FIG. 2 to the output terminal of the differential amplifier circuit 11 as it is, a signal excluding low-frequency components can be obtained at the output terminal 3 as shown in FIG. You can

【0024】このような回路構成とすれば、上記で述べ
られた理由により、集積回路化(ワンチップ化)するこ
とが容易であり、かつ、低域阻止用のキャパシタを外部
に設ける必要がないため、従来にない非常に小型のレー
ザドップラ速度センサを実現することができる。
With such a circuit configuration, it is easy to form an integrated circuit (one chip) for the reasons described above, and there is no need to provide a low-frequency blocking capacitor outside. Therefore, it is possible to realize a very small laser Doppler velocity sensor that has never been available.

【0025】次に、2段の低域阻止フィルタに応用した
例を図10に示す。この回路では利得1のバッファ回路
6と、数個の抵抗R1〜R3と、コンデンサC1とから
なる2個の低減阻止フィルタ7,8を使用している。前
記(5)式にしたがって計算し等価回路図を描くと図1
1のようになる。このように、大きな抵抗値、特にMΩ
単位の値になる場合や、大きな時定数が必要な場合に本
発明高入力インピーダンス回路を適用すると効果が顕著
となる。
Next, FIG. 10 shows an example applied to a two-stage low-pass blocking filter. This circuit uses a buffer circuit 6 having a gain of 1, two resistors R1 and R3, and two reduction blocking filters 7 and 8 including a capacitor C1. Figure 1 shows the equivalent circuit diagram calculated according to equation (5).
It becomes like 1. Thus, a large resistance value, especially MΩ
The effect becomes remarkable when the high input impedance circuit of the present invention is applied when the value becomes unit or when a large time constant is required.

【0026】なお、以上の各実施例では、基準直流電圧
源が回路グラウンドになっているが、交流的に低インピ
ーダンスであればよく、回路グラウンドに限定されるも
のではないことは言うまでもない。
In each of the above embodiments, the reference DC voltage source is the circuit ground, but it is needless to say that it is not limited to the circuit ground as long as it has a low impedance in terms of AC.

【0027】[0027]

【発明の効果】以上説明したように、請求項1の発明に
よれば、任意に高入力インピーダンス回路を簡単な構成
で実現することができる。また、請求項2の発明によれ
ば、きわめて高い入力抵抗値を容易に実現できるので、
大きな時定数を有する時定数回路をごく小さな値のキャ
パシタを用いて簡単に実現することができる。
As described above, according to the invention of claim 1, a high input impedance circuit can be arbitrarily realized with a simple structure. Further, according to the invention of claim 2, since an extremely high input resistance value can be easily realized,
A time constant circuit having a large time constant can be easily realized by using a capacitor having a very small value.

【0028】したがって、大きな値の抵抗やキャパシタ
を使用しなくてもよいので、集積回路化が容易であり、
装置を小型化することができるなどの効果がある。
Therefore, since it is not necessary to use a large value resistor or capacitor, it is easy to form an integrated circuit.
There is an effect that the device can be downsized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の高入力インピーダンス回路を適用した
非反転増幅回路図。
FIG. 1 is a non-inverting amplifier circuit diagram to which a high input impedance circuit of the present invention is applied.

【図2】本発明の高入力インピーダンス回路図。FIG. 2 is a high input impedance circuit diagram of the present invention.

【図3】本発明の時定数回路を適用した非反転増幅回路
図。
FIG. 3 is a non-inverting amplifier circuit diagram to which the time constant circuit of the invention is applied.

【図4】本発明の高入力インピーダンス回路を構成した
集積回路図。
FIG. 4 is an integrated circuit diagram which constitutes a high input impedance circuit of the present invention.

【図5】本発明の高入力インピーダンス回路の他の実施
例を示す回路図。
FIG. 5 is a circuit diagram showing another embodiment of the high input impedance circuit of the present invention.

【図6】レーザードップラ速度センサの受光部に入射さ
れる光強度図。
FIG. 6 is a diagram of a light intensity incident on a light receiving portion of a laser Doppler velocity sensor.

【図7】本発明の時定数回路をレーザードップラ速度セ
ンサに適用した回路図。
FIG. 7 is a circuit diagram in which the time constant circuit of the present invention is applied to a laser Doppler velocity sensor.

【図8】図7における回路のa点の信号波形図。8 is a signal waveform diagram at point a of the circuit in FIG.

【図9】図7における回路の出力端子3の信号波形図。9 is a signal waveform diagram of the output terminal 3 of the circuit in FIG.

【図10】本発明の時定数回路を2段用いた低域阻止フ
ィルタの回路図。
FIG. 10 is a circuit diagram of a low-frequency blocking filter using two stages of the time constant circuit of the present invention.

【図11】図10の等価回路図。11 is an equivalent circuit diagram of FIG.

【図12】従来のバイアス抵抗を含む非反転増幅回路
図。
FIG. 12 is a non-inverting amplifier circuit diagram including a conventional bias resistor.

【図13】図12の非反転増幅回路に低域阻止フィルタ
用キャパシタを追加した回路図。
FIG. 13 is a circuit diagram in which a capacitor for low-frequency blocking filter is added to the non-inverting amplifier circuit of FIG.

【符号の説明】[Explanation of symbols]

1 入力端子(信号源) 4 バッファ回路または増幅回路(信号処理回路) R1,R2,R3 抵抗(受動素子) Z1,Z2,Z3 インピーダンス(受動素子) C1,C2 キャパシタ(受動素子) E アース(基準直流電圧源) 1 input terminal (signal source) 4 buffer circuit or amplifier circuit (signal processing circuit) R1, R2, R3 resistance (passive element) Z1, Z2, Z3 impedance (passive element) C1, C2 capacitor (passive element) E ground (reference) DC voltage source)

───────────────────────────────────────────────────── フロントページの続き (72)発明者 金田 泰 東京都大田区下丸子3丁目30番2号 キヤ ノン株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasushi Kaneda 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 信号源と基準直流電圧源との間に直列に
接続された第1および第2の受動素子と、前記信号源を
入力端子に接続した信号処理回路と、この信号処理回路
の出力端子と前記第1および第2の受動素子の接続部と
の間に接続された第3の受動素子とを備えたことを特徴
とする高入力インピーダンス回路。
1. A first and second passive element connected in series between a signal source and a reference DC voltage source, a signal processing circuit in which the signal source is connected to an input terminal, and a signal processing circuit of the signal processing circuit. A high input impedance circuit comprising: a third passive element connected between an output terminal and a connection portion of the first and second passive elements.
【請求項2】 前記信号処理回路はバッファ回路または
増幅回路を用いることを特徴とする請求項1の高入力イ
ンピーダンス回路。
2. The high input impedance circuit according to claim 1, wherein the signal processing circuit uses a buffer circuit or an amplifier circuit.
【請求項3】 信号源と基準直流電圧源との間に直列に
接続された第1および第2の受動素子と、前記信号源を
入力端子に接続した信号処理回路と、この信号処理回路
の出力端子と前記第1および第2の受動素子の接続部と
の間に接続された第3の受動素子とを備え、前記第1、
第2、第3の受動素子が抵抗である上記高入力インピー
ダンス回路の等価抵抗値とで時定数を得るキャパシタと
を備えたことを特徴とする時定数回路。
3. A first and a second passive element connected in series between a signal source and a reference DC voltage source, a signal processing circuit connecting the signal source to an input terminal, and a signal processing circuit of the signal processing circuit. A third passive element connected between an output terminal and a connection portion of the first and second passive elements, the first,
A time constant circuit, comprising: a capacitor for obtaining a time constant with the equivalent resistance value of the high input impedance circuit in which the second and third passive elements are resistors.
【請求項4】 前記信号処理回路はバッファ回路または
増幅回路を用いることを特徴とする請求項3の時定数回
路。
4. The time constant circuit according to claim 3, wherein the signal processing circuit uses a buffer circuit or an amplifier circuit.
JP4360800A 1992-12-28 1992-12-28 High input impedance circuit and time constant circuit using the same Pending JPH06204763A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4360800A JPH06204763A (en) 1992-12-28 1992-12-28 High input impedance circuit and time constant circuit using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4360800A JPH06204763A (en) 1992-12-28 1992-12-28 High input impedance circuit and time constant circuit using the same

Publications (1)

Publication Number Publication Date
JPH06204763A true JPH06204763A (en) 1994-07-22

Family

ID=18470975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4360800A Pending JPH06204763A (en) 1992-12-28 1992-12-28 High input impedance circuit and time constant circuit using the same

Country Status (1)

Country Link
JP (1) JPH06204763A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006349391A (en) * 2005-06-14 2006-12-28 Hioki Ee Corp Ac amplifier and impedance measuring apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006349391A (en) * 2005-06-14 2006-12-28 Hioki Ee Corp Ac amplifier and impedance measuring apparatus
JP4657017B2 (en) * 2005-06-14 2011-03-23 日置電機株式会社 AC amplifier and impedance measuring device

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