JPH06204243A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the formation of a MOS transistor by a method wherein a protective film on a sidewall formed during the gate electrode etching step is made a part of an ion implanting mask for the formation of a MOS transistor impurity region. CONSTITUTION:A field insulating film 13 is formed on an Si substrate 11 whereon an N, P well is formed and then a gate oxide film 14 is formed in an active region to adjust the threshold voltage by channel implantation. Later, a gate electrode pattern is formed of a photoresist 23 on a polySi doped with phosphorus to perform selective dryetching using the gate pattern as a mask. Simultaneously, a protective film 24 is formed on the sidewall of the gate electrode 15. At this time, oxygen addition, is adjusted up to 10% to enable the size of the protective film 24 to be controlled. Next, after releasing the photoresist 23, Nch and Pch of the high concentration impurity region 19 as a source and a drain are respectively ion implanted with arsenic and BF2. At this time, the protective film 24 on the sidewall can fulfill the role of a spacer to form an offset region of a MOS transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a MOS transistor.

[0002]

2. Description of the Related Art MOS-LSIs and the like are required to be miniaturized in order to achieve integration, high speed, and multi-functionalization. Conventionally, the manufacturing method of these semiconductor devices is, for example, Si in which a well region 12 is formed as shown in FIG. A field insulating film 13 is formed on the substrate 11 by selective oxidation, a gate oxide film 14 is formed in the active region thereof, PolySi is vapor-deposited, and a gate electrode 15 is dry-etched using a photoresist as a mask. At this time, anisotropic etching is performed by using He for chlorine or SF6 gas at a pressure of several mtorr. Next, after removing the photoresist, low-concentration impurity regions (offset regions) of the source and drain
4 after implanting impurities such as phosphorus and boron into 16
A silicon oxide film 17 of up to 5000 Å is vapor-phase grown (FIG. 2A). Next, using a parallel plate RIE type dry etching apparatus, anisotropic full surface etch back is performed using a gas such as CHF3 or C2F6, and a spacer 18 is formed on the side wall of the gate electrode 15 and then about 100 to 200Å Of the silicon oxide film 20 is vapor-deposited, and arsenic, BF2, etc. are ion-implanted into the high-concentration impurity regions 19 of the source and drain through the spacer 18 to LDD (lightly d).
and an oxidization gas such as O2 or N2O is vapor-phase-reacted with SiH4 and a BPSG film 22 containing phosphorus or boron are laminated and annealed to form an interlayer insulating film (Fig. 2). (B)) Subsequently, after opening contact holes, PolySi, Al alloy, etc. are grown to provide resistance elements and upper layer wiring, and finally a passivation film is laminated and a bonding pad portion for extracting an external electrode is opened. There is.

[0003]

However, in the prior art, in order to surely form the spacer 18 on the side wall, it is necessary to increase the film thickness of the silicon oxide film 17 including the variation of the film thickness and the etch back, and to perform overetching. It is necessary to increase If the thickness is increased, the dimensions and variations of the spacer 18 are increased, and the transistor characteristics and reliability are unstable. By the way, when the space rule is 0.5 μm or less, the spacer size on both sides becomes larger, and when the wiring is taken out from between the gate electrodes 15, the process and the structure are complicated and miniaturization is not possible. It was difficult. Further, when the gate electrode 15 is also thinned from being flattened,
The vapor-phase growth silicon oxide film 17 reacted with SiH4 is likely to cause cusping when the space becomes narrow, and it is difficult to stably form a spacer having a size of 0.2 μm or less in mass production.

Further, the process itself of forming the spacer 18 by etching back becomes a factor of particles, and even in the case of over-etching, an egre of the field oxide film and defects of the Si surface of the source and drain occur, resulting in flatness, yield and electrical characteristics. I was having trouble.

On the other hand, from the viewpoint of mass production cost, there is a problem that the number of processes is increased due to the miniaturization and integration, and therefore there is a strong demand for process shortening and process stabilization.

However, the present invention solves such a problem, and particularly facilitates formation of a MOS transistor, and aims to improve the quality of the fine semiconductor device due to its stable electrical characteristics and reliability, and shorten the manufacturing process. It is intended.

[0007]

According to the method of manufacturing a semiconductor device of the present invention, the sidewall protection film formed at the time of selective etching of the gate electrode is used as a part of the ion implantation mask for forming the MOS transistor impurity region. Is characterized by.

The method of manufacturing a semiconductor device according to the present invention is an MO method.
In forming the S-transistor, at least a step of selectively etching the gate electrode while adding a reaction gas that promotes the growth of the sidewall protective film to the main etching gas, an step of ion-implanting a high-concentration impurity region such as a source and a drain, the sidewall The method is characterized by including a step of removing the protective film, a step of implanting ions into low-concentration impurity regions such as a source and a drain, and a step of forming an interlayer insulating film and opening a contact hole from the element to provide wiring.

[0009]

Embodiments of the present invention will be described in detail below with reference to FIG.

When applied to the manufacture of a half-micron CMOS gate array, the field insulating film 13 is formed by selective oxidation on the Si substrate 11 on which the N and P wells 12 are formed, and the gate oxide film 14 is formed on the active region thereof. After adjusting the threshold voltage by forming a channel and injecting a channel, the minimum dimension 0.4 on the phosphorus-doped PolySi2500Å
A 5 μm gate electrode 15 pattern is formed from a photoresist 23, and selective dry etching is performed using this as a mask (FIG. 1A). The etching at this time is RI of a parallel plate.
Using an E apparatus, 100 cc / min of chlorine was added with about 5% of oxygen to a pressure of 25 mtorr, the etching rate was about 2000∂, and the selection ratio was about 75 at 500 w. A protective film 24 having a width of 12 μm was formed. At this time, by adjusting the addition amount of oxygen to about 10%, the protective film 24 formed is 0.02 to 0.
Dimension control is possible up to about 2 μm. Next, after removing the photoresist 23, the high-concentration impurity regions 19 of the source and drain are formed.
Arsenic on Nch and BF2 on Pch at about 50 kev.
Ions were implanted at about 1 to 1 × 10 ¹⁶ cm ⁻² (FIG. 1B). Here, the protective film 24 on the side wall serves as a spacer forming the offset region of the MOS transistor. Then, an ammonium hydroxide aqueous solution:
Hydrogen peroxide water = 1: 1 and add about 2 to 10 times water to 40
The protective film 24 on the side wall is removed by immersing the solution in a solution heated to -80 ° C. for about 5 minutes. Next, in order to prevent the generation of crystal defects, a silicon oxide film 20 of about 150 Å is vapor-deposited and the source,
Phosphorus on Nch and BF2 on Pch in the low concentration impurity region (offset region) 16 of the drain is about 60 kev and 0.5.
To about 5 × 10 ¹³ cm ^−2, respectively. Next, 2000 liters of non-doped silicon oxide film 21 obtained by vapor-phase reaction of SiH4 with N2O and BPSG film 2 are used as an interlayer insulating film.
2 was deposited by vapor phase growth, and then annealed at 850 to 900 ° C. for both reflow for planarization and activation (FIG. 1).
(C)). A semiconductor device in which a contact hole is continuously opened, an Al alloy or the like is grown, and an interlayer film growth and a wiring process are repeated to form a multilayer wiring structure, and finally a passivation film is applied to open a bonding pad portion for extracting an external electrode. Was manufactured.

According to the semiconductor device and the manufacturing method of the present invention described above, the steps of growing a silicon oxide film and forming a full-scale etch back for forming sidewall spacers are not required, so that particles are reduced and the steps are shortened. The effect was also found to prevent the occurrence of defects on the surface of the field insulating film 13 and the surface of the source and drain, and the flattening and the reduction of junction leakage were achieved. In addition, it is easy to control the size of the side wall protective film that functions as an ion implantation spacer, stabilize the characteristics of the MOS transistor against punch-through and hot carriers, and stabilize the MOS transistor with a fine structure of 0.5 μm rule or less. Formation is now possible.

In another embodiment, the silicon oxide film 20 is thickened to about 1000Å and the ion implantation acceleration voltage is increased to form the low-concentration impurity regions 16 of the source and drain, thereby forming a barrier of the BPSG film 22. MOS-LS having a structure in which the silicon oxide film 21 is removed, or a gate having an overlapped LDD structure by oblique ion implantation
I was also manufactured, but in each case, problems such as shortening of the process were improved compared to the conventional method, and the electrical characteristics and reliability were improved.

Further, when etching the gate electrode, CH
F3 or CH2 F2 with chlorine 100 cc / min and oxygen gas 10
By adding about 1 to 15% to cc / min,
The side wall protective film 24 with less peeling and thickness variation was formed, and its effectiveness was confirmed especially when the thickness of the gate electrode 15 is reduced to 2500 Å or less. Depending on the amount of CHF3 or the like added, the shape of the protective film 24 and the range of 0.01-0.25.
Dimension control of about μm was possible. In order that the side wall protective film 24 remaining after the photoresist 23 is peeled off is stably left in a shape required as an ion implantation spacer, it is preferable that the protective film adhered to the side wall of the photoresist 23 is small, and the side wall protective film 24 contains oxygen. The ratio is increased to about 5 to 20% and the side surface of the photoresist is tapered, and the degree of vacuum is set to 20 mt.
It is effective to keep it below orr.

On the other hand, since the high-concentration region of the MOS transistor is formed first, the degree of freedom of heat treatment that can be applied before the offset region forming step is increased, and the silicon oxide film 21 is changed to vapor phase growth by thermal oxidation at about 900.degree. A device with a lower diffusion layer and lower contact resistance than the conventional one could be manufactured by introducing the activation process in the high concentration region using a lamp aniler or a diffusion furnace. This makes it possible to reduce the heat treatment in the subsequent process when obtaining the diffusion resistance value determined from the device specifications, which is advantageous in improving the punch-through margin of the transistor.

In the embodiment of the present invention, the manufacture of a multilayer wiring LSI having a PolySi gate structure has been described. However, it is a polycide structure in which a silicide of a refractory metal such as Mo or W is laminated on the gate electrode. Good, Poly
It can also be applied to Si or silicide wiring, a memory having high resistance or TFT. Also, single channel MO
In the case of the S structure, it is not necessary to perform selective ion implantation of Pch and Nch. Therefore, the photoresist peeling of the pattern of the gate electrode 15 may be performed after the high concentration ion implantation.

[0016]

As described above, according to the present invention, by using the protective film on the side wall formed at the time of etching the gate electrode as a spacer for forming the offset region of the MOS transistor, the process is shortened and the cost is reduced. Further, the reliability and yield related to the electrical characteristics and quality are improved, which can contribute to stable mass production of finer and more multifunctional semiconductor devices.

[Brief description of drawings]

1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.

2A to 2B are schematic cross-sectional views related to a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 11 Si substrate 12 well 13 field insulating film 14 gate oxide film 15 gate electrode 16 low concentration impurity region 17, 20, 21 silicon oxide film 18 spacer 19 high concentration impurity region 22 BPSG film 23 photoresist 24 sidewall protection film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 21/28 L 7376-4M

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a side wall protective film formed during selective etching of a gate electrode is used as a part of an ion implantation mask for forming a MOS transistor impurity region. 2. A step of selectively etching a gate electrode while adding a reaction gas that promotes growth of a sidewall protective film to at least a main etching gas when forming a MOS transistor, and ion implantation into a high concentration impurity region such as a source and a drain. A step of removing the side wall protective film,
A method of manufacturing a semiconductor device, comprising: a step of implanting ions into low-concentration impurity regions such as a source and a drain; and a step of forming an interlayer insulating film, opening contact holes from elements and providing wiring. 3. The method for manufacturing a semiconductor device according to claim 2, wherein chlorine, fluorine and bromine or at least one of these compounds coexist as a main etching gas. 4. A method of manufacturing a semiconductor device, wherein the reaction gas for promoting the growth of the side wall protective film according to claim 2 is oxygen. 5. A method of manufacturing a semiconductor device, wherein at least one compound containing hydrogen or carbon is contained as a reaction gas for promoting the growth of the sidewall protective film according to claim 2. 6. The method of manufacturing a semiconductor device according to claim 2, wherein the step of removing the side wall protective film is performed by using a mixed aqueous solution of ammonium hydroxide and hydrogen peroxide.