JPH06203091A - Logical simulator and control method therefor - Google Patents

Abstract

PURPOSE:To start debugging by a software simulator immediately after detecting an expected value non-coincidence error for the simulated result of a hardware simulator. CONSTITUTION:Logical model data in a tabular format including the values of respective signals in a logical model are stored in respective storage devices 104 and 203 inside a host 100 provided with the software simulator 103 and the hardware simulator 200. When an error is not detected in expected value comparison for the simulated result obtained by the hardware simulator 200 and a simulation time and a value list data transfer time specified beforehand coincide, the data of a value list on the side of the hardware simulator 200 are transferred to the host 100 along with time data and the logical model data inside the storage device 104 on the side of the host 100 are updated. Also, when the error is detected in the expected value comparison, the simulation of the hardware simulator 200 is interrupted, the software simulator 103 is started instead and target debugging is started with the value list data and time data inside the storage device 104 as initial values.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an ASIC (Applicatio)
The present invention relates to a logic simulator used in the development of (n Specific IC) and its control method.

[0002]

2. Description of the Related Art In recent years, a hardware simulator, which is a dedicated device for verifying the operation of a logic circuit, has been actively developed. This hardware simulator expresses a logical model in a hardware description language or a schematic, and executes a simulation by giving test data to this logical model. This hardware simulator is much faster than the simulation method using software,
It also has many advantages such as economical and labor loss reduction. Therefore, it can be said that it is extremely suitable for simulation of a large-scale logic circuit.

This hardware simulator executes an event driven simulation. This event-driven method captures a change in the value of a signal between functional elements or functional blocks that make up a logic circuit as an event, and propagates this changed signal to the functional element or functional block to which it is connected to simulate. It is a method to proceed.

By the way, since this hardware simulator is developed aiming at a high-speed simulation-dedicated device, it is usual that a subordinate function such as a debug function is not incorporated. On the other hand, many software simulators have a debugging function and can debug from the middle of the simulation in an interactive form with the user.

Therefore, a system has been considered in which a software simulator and a hardware simulator are combined, a normal simulation is executed by the hardware simulator, and the software simulator is activated only when debugging is performed.

Data representing a logical model in a table format is stored in a storage device of such a system, and a hardware simulator and a software simulator execute a simulation based on the logical model data. In the logic model data, there is a value table that stores the value of each signal in the logic model during the simulation. The data in this value table is updated to the state of the current simulation time as the simulation is performed.

Further, the simulation result obtained by the hardware simulator is sequentially compared with the expected value stored in advance in order to check its validity. When an error is determined by this expected value comparison, the user interrupts the operation of the hardware simulator, activates the software simulator, and starts debugging. However, in this case, there are the following problems. That is, by the time the simulation result of the hardware simulator is compared with its expected value, the data in the value table in the storage device has already been updated by this simulation. Therefore, even if an error is determined by the expected value comparison, at this time, the data of the value table in the storage device is already in a state after the error occurrence that is meaningless for debugging. In order to perform debugging with the software simulator, the data before the time when the error occurs is necessary, and therefore, conventionally, the simulation had to be redone until a time slightly before the time when the error occurred. Therefore, it was not possible to debug on the software simulator immediately after the error judgment.

[0008]

SUMMARY OF THE INVENTION The present invention is intended to solve such a problem, in which debugging by a first simulator such as a software simulator in the host computer is performed by a second simulator such as hardware outside the host computer. It is an object of the present invention to provide a logic simulator that can start immediately after detecting an error in the simulation result of the simulator and a control method thereof.

[0009]

In order to achieve the above object, a logic simulator of the present invention is a logic simulator in which a second simulator is connected to a host computer having a first simulator for simulating and debugging a logic model. In the second simulator, the second simulator includes first storage means for storing logic model data including a value of each signal in the logic model necessary for execution of simulation, and time data input from the host computer. A simulation is performed on the logic model based on the test data and the logic model data stored in the first storage means, and the value of each signal in the logic model data stored in the first storage means is simulated. Simulation execution to update the state after execution And a transfer means for transferring the simulation result obtained by the simulation execution means to the host computer, and the host computer simulates on the second simulator within a plurality of predesignated times. The logical model data at the specified time immediately before the end of the
Second storage means for storing data required to start simulation and debugging with the simulator, third storage means for storing an expected value for the simulation result, simulation result transferred by the transfer means, and the third storage means. 3 comparing means for comparing the expected value stored in the storing means, and when the comparing means determines that the simulation result and the expected value do not match, the second simulator is instructed to suspend the simulation. And a means for activating the first simulator.

[0010]

According to the present invention, first, the simulation executing means of the second simulator uses the logic model based on the test data including the time data input from the host computer and the logic model data stored in the first storing means. Is executed, and the value of each signal stored in the first storage means is updated in the state at the current time. Then, when the simulation for one input of the test data (simulation for one time) is completed, the transfer means transfers the simulation result to the host computer. When the host computer receives the simulation result, the comparison means compares the simulation result with the expected value stored in the third storage means. As a result of this comparison, when it is determined that the simulation result does not match the expected value, the host computer instructs the second simulator to suspend the simulation and activates the first simulator. Where the second
The value of each signal in the logical model data stored in the storage means is a designated time immediately before the time when the expected value error is detected in the simulation result of the second simulator among a plurality of times designated in advance. Of the first storage means. Therefore, the second simulator can start the intended simulation and debugging immediately after starting up, which can greatly improve the debugging efficiency.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a logic simulator according to an embodiment of the present invention.

In the figure, 100 is a host computer, 200 is the host computer 100 and an external bus 30.
It is a hardware simulator as a second simulator that is a dedicated simulation device connected through 0.

The host computer 100 has a CPU 10
1, a simulator control device 102, a software simulator 103 as a first simulator having a debug function, a storage device 104, an expected value file storage unit 1
05, keyboard and CRT input / output terminal 10
6 and so on.

The CPU 101 is a host computer 10.
Input / output and control of data between each component within 0. The simulator control device 102 is a host computer 10
Input / output of various data between 0 and the hardware simulator 200, switching control between the software simulator 103 and the hardware simulator 200, and error control by comparing the simulation result with an expected value. To do. The software simulator 103 executes a simulation and a debug for the logical model in an interactive mode with a user according to a predetermined program. The storage device 104 stores logical model data in which a logical model is expressed in a table format, test data input to the hardware simulator 200, and further the hardware simulator 200.
The time data and the like transferred from are stored. Logical model data includes facility table, connection table, operation table, terminal table,
It is composed of a value table. Here, the value table stores the value of each signal in the logic model, and the content thereof may be updated every time the simulation is performed at each time. The time data represents the latest time when the data in the value table was updated. The software simulator 103 performs simulation and debugging with the value table data and time data stored in the storage device 104 as initial values. The expected value file storage unit 105 stores expected values for simulation results.

On the other hand, the hardware simulator 200
Is a processor 201, an input buffer memory 202, a logical model data memory 203, an event / stack memory 204, and an output buffer memory 205.

The input buffer memory 202 temporarily stores test data and the like transferred from the host computer 100 via the bus 300. Similar to the storage device 104 of the host computer 100, the logical model data memory 203 stores logical model data such as a facility table, a connection table, a calculation table, a terminal table, and a value table that represent a logical model in a tabular format. Here, the facility table is formed by registering pointers to the value table and pointers to the connection table corresponding to signals between the functional elements or between the functional blocks that form the logic model. The value table registers signal values between the functional elements or between the functional blocks. The values in this value table are updated each time an event occurs. The connection table is formed by registering a pointer to the calculation table. The operation table is formed by registering operation instructions corresponding to the functions of each functional element or each functional block forming the logic model. Further, the logical model data memory 203 stores the trace condition, the simulation end condition, and time information for transferring the data of the value table to the host computer 100, which are arbitrarily set by the user. The event / stack memory 204 stores an event data area 204a in which a pointer to a facility table for a signal in which an event has occurred is stored as event data, a calculation instruction necessary for calculation processing, and the value of the signal that is the calculation target. Calculation data area 204b. Output buffer memory 205
The simulation result, that is, various information to be transferred to the host computer 100, such as the value of the trace-designated signal, error data, and simulation end data, is temporarily stored.

The processor 201 incorporates an interface processing unit 211, a condition processing unit 212, a logical operation processing unit 213, an event processing unit 214 and a connection processing unit 215. The interface processing unit 211 is connected to the bus 300 of the host computer 100 and controls input / output of various data with the host computer 100. The condition processing unit 212 controls the execution of the simulation according to the trace condition, the simulation end condition, the value data transfer time, etc. set by the user on the host computer 100. The logical operation processing unit 213 executes arithmetic processing corresponding to the function of the functional element or the functional block based on the logical model data stored in the logical model data memory 203. The event processing unit 214 evaluates the occurrence of the event with respect to the value of the signal obtained by the logical operation processing unit 213, and when the event occurrence is determined, the event data area 204a of the event / stack memory 204 is provided with a facility corresponding to the event occurrence signal. Register the pointer to the table as event data. At the same time, the event processing unit 214 updates the value of the corresponding signal registered in the value table of the logical model data memory 203 with the value of the event occurrence signal. When an event occurs, the connection processing unit 215 uses the pointer to the facility table stored in the event data area 204a of the event / stack memory 204, based on the facility table, connection table, calculation table, and value table in the logical model data memory 203. Are sequentially searched to determine the operation instruction corresponding to the function of the functional element or functional block through which the event occurrence signal propagates and the value of the signal input to this functional element or functional block.

Next, the operation of the logic simulator of this embodiment will be described with reference to the flow charts of FIGS. 2. FIG. 2 is a flowchart showing the control flow of the logic simulator as a whole. FIG. 3 is a flowchart showing the procedure of simulation on the hardware simulator 200.

First, the simulator control device 102 in the host computer 100 is started up and the processing before the simulation is executed. As pre-processing, the simulator control device 102 uses the storage device 10 in the host computer 100.
4 and the value table in the logical model data memory 203 in the hardware simulator 200 are set to initial values (step 201).

Subsequently, the simulator control device 102 controls the trace condition, the simulation end condition, and the hardware simulator 2 which are designated in advance by the user.
The hardware simulator 200 provides information such as the time when the data of the value table of 00 is transferred to the host computer 100.
(Step 202).

In addition, the user performs necessary preprocessing such as storing the test data for a plurality of times to be given to the hardware simulator 200 in the storage device 104 in the host computer 100 during the simulation (step 203).

Next, the user inputs a simulation start command (step 204). Then, the simulator control device 102 reads the test data at the first time from the storage device 104, adds the time data to the test data, and transfers the test data to the hardware simulator 200.

The test data including the time data is input buffer memory 202 in the hardware simulator 200.
Then, the logical operation processing unit 213 reads these data, and the hardware simulator 2
The simulation for one time on 00 is started (step 205).

In step 301 of FIG. 3, the logical operation processing unit 213 sets the functional element or functional block to which the test data is input, that is, the functional element or functional block connected to the input terminal of the verification logic circuit, to the logical model data memory 203. Judging from the contents of (step 301). Next, the logical operation processing unit 213 executes the operation processing when each signal of the test data is input to the determined functional element or functional block (step 302).

The operation result of the logical operation processing unit 213 is input to the event processing unit 214. The event processing unit 214 compares the value of the output signal of the functional element or the functional block, which is the calculation result, with the value of the corresponding signal registered in the value table of the logical model data memory 203 to evaluate the occurrence of the event. That is, it is determined whether or not the signal value as the calculation result matches the signal value in the value table (step 303).
As a result, if the occurrence of an event is not detected, the condition processing unit 214 reads the value of the trace-designated signal from the value table of the logical model data memory 203, and uses this as a simulation result in the host computer 100 through the interface processing unit 211. Transfer (Step 3)
04). This completes the simulation for the input of one test data.

If it is determined that an event has occurred as a result of the event evaluation, the event processing unit 214 causes the event /
Event data area 204a of the stack memory 204
Then, a pointer to the facility table corresponding to the event occurrence signal is registered as event data (step 305). Then, the value of the corresponding signal registered in the value table of the logical model data memory 203 is updated with the value of the signal which is the new calculation result (step 306).

Next, the connection processing unit 215 reads out a pointer to the facility table stored in the event data area 204a of the event / stack memory 204, and based on this pointer, the facility table of the logical model data memory 203, the connection table, The operation table and the value table are sequentially searched to determine the operation instruction corresponding to the function of the functional element or functional block through which the signal in which the event has been propagated and the signal value input to this functional element or functional block (step 307). Then, these operation data are stored in the operation data area 204b of the event / stack memory 204.

After that, the logical operation processing unit 213 executes the operation processing corresponding to the function of the functional element or the functional block from the operation command and the signal value stored in the operation data area 204b of the event / stack memory 204 ( Step 308).

After that, the occurrence of the event is evaluated again with respect to the calculation result (step 303), and thereafter, the processes from step 303 to step 308 are repeated until the event is not propagated or the simulation ending condition is satisfied. Finally, in step 304, the simulation result is transferred to the host computer 100, and the simulation for one test data input is completed.

The simulation result thus obtained by the hardware simulator 200 is transferred to the host computer 100. And simulator control device 1
02, the expected value stored in the storage device 104 is compared with the simulation result (step 20).
6).

In this expected value comparison, if all the simulation results match the expected value (step 207),
The simulator control device 102 sends a signal indicating this to the hardware simulator 200. The hardware simulator 200 inputs this signal to the condition processing unit 212 through the interface processing unit 211. Then, the condition processing unit 212 refers to the value data transfer time stored in the logical model data memory 203, and determines whether the current simulation time corresponding to the time data added to the test data is the value data transfer time. The determination is made (step 208). As a result, when the condition processing unit 212 determines that the current time is not the value data transfer time, the process returns to step 205 and the simulation for the next test data is started.

If it is determined in step 208 that the current time is the value data transfer time, the condition processing unit 2
Reference numeral 12 reads out all the value table data in the logical model data memory 203 and transfers these value table data to the host computer 100 together with the current time data. The value table data and the time data transferred to the host computer 100 are overwritten in the storage device 104 by the simulator control device 102, whereby the value table data and the time data in the storage device 104 are updated (step 209). After this, the hardware simulator 200
Returns to step 205 to start the simulation for the test data at the next time.

When the simulator control unit 102 determines that they do not match in the expected value comparison in steps 206 and 207, the simulator control unit 102 instructs the hardware simulator 200 to suspend the simulation and activates the software simulator 103. (Step 210).

The software simulator 103 starts simulation and debugging with the data of the value table in the storage device 104 and the time data as initial values. The simulation and debugging by the software simulator 103 are advanced in an interactive form with the user until the user determines that the simulation time has reached the next value data transfer time (step 211).

When the simulation time reaches the next value data transfer time, the user chooses whether to end the simulation or start the hardware simulator 200 again and continue the simulation (step 212). . For example, the result of debugging
If it is found that the logical model needs to be modified, the termination of the simulation is selected. When the user selects to continue the simulation, the simulator control device 102 instructs the hardware simulator 200 to restart the simulation, and at the same time, the data of the value table in the current storage device 104 and the time data are set to the hardware simulator. Transfer to 200. The hardware simulator 200 updates the value table data and the time data in the logical model data memory 203 with these transfer data (step 213), returns to step 205, and sets the value table data and the time data as initial values. Restart the simulation.

As described above, in the logic simulator of this embodiment, the storage device 104 of the host computer 100 is always available.
In addition, the data of the value table and the time data of the time slightly before the simulation time on the hardware simulator 200 are stored. Therefore, when the simulation result does not match the expected value and an error is detected, the host computer 10 uses the data of the value table and the time data stored in the storage device 104 as initial values.
Simulation and debug can be started immediately with zero software simulator 103. As a result, the debugging efficiency can be significantly improved.

In this embodiment, the value table data and the time data in the logical model data memory 203 are transferred to the host computer 1 only at the value data transfer time set by the user.
However, the value table data in the logical model data memory 203 may be transferred to the host computer 100 at all simulation times. In this case, the time data may or may not be transferred.

[0039]

As described above, according to the logic simulator and the control method of the present invention, the debugging by the first simulator in the host computer, for example, the software simulator, is performed by the second simulator outside the host computer.
It is possible to start immediately after detecting an error in the simulation result of the simulator, for example, the hardware simulator, and it is possible to greatly improve the debugging efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a logic simulator according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the overall control flow of the logic simulator shown in FIG.

FIG. 3 is a flowchart showing a procedure of simulation on a hardware simulator in the logic simulator shown in FIG.

[Explanation of Codes] 100 ... Host computer, 101 ... CPU, 102
... Simulator control device, 103 ... Software simulator, 104 ... Storage device, 105 ... Expected value file storage unit, 106 ... Input / output terminal, 200 ... Hardware simulator, 201 ... Processor, 202 ... Input buffer memory, 203 ... Logical model data Memory, 204 ... Event / stack memory, 205 ... Output buffer memory, 211 ... Interface processing unit, 212 ... Condition processing unit, 213 ... Logical operation processing unit, 214 ... Event processing unit, 215 ... Connection processing unit.

Claims (4)

[Claims] 1. A logic simulator in which a second simulator is connected to a host computer having a first simulator for simulating and debugging a logic model, wherein the second simulator is the one in the logic model necessary for executing the simulation. First storage means for storing logic model data including values of respective signals of, and test data including time data input from the host computer,
And a state after the simulation is performed on the logic model based on the logic model data stored in the first storage means, and the value of each signal in the logic model data stored in the first storage means is executed. And a transfer means for transferring the simulation result obtained by the simulation execution means to the host computer, and the host computer is configured to perform the simulation in a plurality of predesignated times. Second storage means for storing the logical model data at a specified time immediately before the time when the simulation is finished on the second simulator as data necessary for starting simulation and debugging on the first simulator; Remember the expected value for the result Third storage means, comparison means for comparing the simulation result transferred from the transfer means with the expected value stored in the third storage means, and the comparison result between the simulation result and the expected value If it is determined that the first simulator is instructed to suspend the simulation,
And a means for activating the simulator described in 1. above. 2. The logic simulator according to claim 1, wherein the second simulator transfers the value of each signal stored in the first storage means to the host computer in accordance with a transfer request from the host computer. And a means for making a transfer request to the second simulator when the comparison means determines that the simulation result matches the expected value. A logic simulator, which updates the logic model data of the second storage means with the value of each signal transferred from the second transfer means of the second simulator in accordance with the transfer request. . 3. The logic simulator according to claim 1, wherein the second simulator preliminarily transfers the value of each signal in the logic model stored in the first storage means to the host computer. Fourth storage means for storing data at a designated time, time data added to the test data input from the host computer, and the fourth storage means.
The second transfer means receives the transfer request from the host computer, and the time data added to the test data is further included in the time data check means for checking the time data stored in the storage means. When the corresponding current simulation time coincides with any time stored in the fourth storage means as a result of the comparison by the time data comparison means, the value of each signal stored in the first storage means is changed. A logic simulator which transfers the time data to the host computer. 4. A second computer is connected to a host computer having a first simulator for simulating and debugging a logical model, and the second simulator is one of the logical models in the logical model necessary for executing the simulation. The host computer has a first memory for storing logic model data including the value of each signal, and the host computer specifies immediately before the time when the simulation is finished on the second simulator among a plurality of times specified in advance. A logic simulator having a second memory that stores the logic model data at time as data necessary for starting simulation and debugging with the first simulator, and a third memory that stores an expected value for a simulation result. In the control method, the host computer A value of each signal stored in the first memory, the simulation is executed on the second simulator based on the input test data including the time data and the logic model data stored in the first memory. In the state of the current time, a step of transferring the simulation result obtained on the second simulator to the host computer, a simulation result transferred to the host computer and stored in the third memory. Comparing the expected value with the expected value on the host computer to determine whether each match / mismatch, and as a result of the comparison, if the mismatch between the simulation result and the expected value is determined, the second Interrupting the simulation of the simulator and starting the first simulator. A method for controlling a logic simulator characterized by the above.