WO2001084316A1

WO2001084316A1 - Rapid debugging method on rapid prototyping apparatus for complex embedded system

Info

Publication number: WO2001084316A1
Application number: PCT/KR2001/000722
Authority: WO
Inventors: Sei-Yang Yang
Original assignee: Yang Sei Yang
Priority date: 2000-05-02
Filing date: 2001-05-02
Publication date: 2001-11-08
Also published as: KR20010100961A

Abstract

The present invention relates to effective debugging method by using rapid prototyping apparatus for enabling effective debugging of embedded system. The present invention produces a binary execution code with regard to processor in embedded system of a verification subject, and programming pattern for realizing digital hardware portion of the embedded system into programmable device of an arbitrary prototyping board when necessary, downloads from the personal computer said produced binary execution code and programming pattern as debugger of personal computer via connecting device for communication to the memory of the arbitrary prototyping board and the programmable device, respectively, and after realizing embedded system of the verification subject on the arbitrary prototyping board and with complete control of the execution of the embedded system realized on the arbitrary prototyping board by using debugger, verify freely changing status of the embedded system realized on the arbitrary prototyping board for rapid debugging.

Description

RAPID DEBUGGING METHOD ON RAPID PROTOTYPING APPARATUS FOR COMPLEX EMBEDDED SYSTEM

BACKGROUND OF THE INVENTION

Field of the Invention The present invention relates to a debugging technique for design verification based on a rapid prototyping which promptly inspects a designed embedded system. Particularly, by making an effective debugging of the designed embedded system possible, the present invention relates to a debugging method necessary to the prototyping device for the embedded system inspecting with speed.

Description of the Related Art

The constitution of the past embedded system is generally comprised only of a processor, a memory and an input/output port (for example, a micro-controller). In such circumstance, in order to constitute a system suitable for a particular applied field, a software for a processor was developed and converted into an executable binary code through compiling or assembling process. Thus, loading said software to a memory such as ROM or RAM was the core of the developing the embedded system.

In order to develop code for the processor of such embedded system, the existing Microprocessor Development System (MDS) equipment was used. However, recently it is possible to have a further optimum in aspect of a price to performance ratio in the applied field, and in order to obtain a high security, there is a trend to even include an Application Specific Integrated Circuits (ASIC) in the embedded system.

If the Application Specific Integrated Circuits (ASIC) is to be included in the embedded system as the above, the entire task executed by the embedded system can be divided into a part performed by the processor of the embedded system and a part performed by the application specific integrated circuits of the embedded system, respectively. Thus, by furnishing interface therebetween, the entire task can be executed. In this regard, the part of task performed by the embedded system's processor is processed by a software code of the processor and therefore, is called 'software execution', and the part of task performed by the embedded system's application specific integrated circuits is processed by the application specific integrated circuit and therefore, is called 'hardware execution'. Such method as described above has its own respective characteristic advantages and disadvantages since the conduct of task is processed by hardware and software. In other words, the advantage of processing task with hardware execution is in obtaining a very fast processing speed and a high security, whereas the disadvantage is a low flexibility. The advantage of processing task with software execution is the extremely high flexibility enabling a fast upgrading, etc. Nevertheless, the disadvantage is relatively slow processing speed and low security.

Accordingly, the embedded system using both processor and application specific integrated circuit may acquire the optimum design possibly taking only the advantages of both {execution methods}. For example, the part of task requiring a fast processing speed among the tasks for a particular application may be conducted by the embedded system's application specific integrated circuits, and the part requiring a change when upgrading in the future or the control portion of the entire system may be conducted by the embedded system's processor so that the development of the embedded system in accomplishment of the optimum in aspect of the price to performance ratio of the particular application may become possible. Fig. 1 illustrates the gist of the constitution of such embedded^" system, and such system is generally comprised of a processor (2), a memory (4), I/O port (8), and when necessary, comprised of an application specific integrated circuit ( 6 ) .

Nevertheless, the development of the embedded system consisting of both application specific integrated circuits and processor (hereinafter, refer to as "complex embedded system") is more difficult than that of the embedded system consisting of only a processor (hereinafter, refer to as "simple embedded system"). That is to say, the debugging process of the simple embedded system is easy since only the processor solely performs a role of a master to process the task. Contrarily, the processor and the application specific integrated circuit of the complex embedded system should not perform an independent master role, respectively but should interchange the master role in mutual dependence and concurrently process the task. Accordingly, an integrated simultaneous debugging in consideration of the above should be supported during its development stage.

For instance, for debugging of the complex embedded system, at the arbitrary point desired by the complex embedded system designer during the execution of the embedded system, the execution of the complex embedded system is temporarily stopped and at this arbitrary point of time, in order to inspect all the status information of the complex embedded system, first, not only the execution of the software processed by processor and memory should be stopped, but also the execution of the hardware processed by the application specific integrated circuits should be stopped likewise. Also, not only all the status information with regard to the processor and the memory required by the designer, but also all the necessary status information (for example, when the instruction code o.f a particular processor is executed, the logical values of the flip-flop of a circuit realized in the application specific integrated circuits) should be knowledgeable. Recently, due to development of the semiconductor integration technique, a technique constituting such embedded system by a single chip so called System On a Chip (hereinafter, refer to as "SOC") is also used. Yet, observability and controllability of a constitution having such complex embedded system by a single chip are much declined compared to the constitution of such complex embedded system composed on a board so that it is more difficult to debug at developing stage. Lately, programmable devices in the improved form of integrating a processor core together with field programmable gate array logic in a single chip are introduced in the market, and they are Virtex-II Platform FPGA of XILINX and Excalibur SOPC (System On a Programmable Chip) of ALTERA. As these devices employ field programmable technique, particularly, a complex embedded system can be promptly realized which is deemed to form a very promising market in the embedded system field.

Nevertheless, a prototyping device for a complex embedded system with a simultaneous hardware/software debugging function promptly and effectively correcting the bugs produced during the course of developing such complex embedded system did not exist until now. Moreover, the recent processor or controller employs a pipelining method in order to improve its efficiency. Such pipelining method divides the instruction execution process into several stages and undergoes an hourly temporally parallelization whereby it makes the debugging more difficult.

In order to perform a correction and a new verification of the bugs discovered during such debugging process, the prototyping device must every time be re-executed from the start which also raises a serious problem of a very prolonged debugging time.

Separately from the above, at present, a co-verification method using virtual prototype is widely used for designing and verifying a complex embedded system having a simultaneous existence of hardware and software. Such virtual prototype does not use an actual hardware, but uses virtual software models for all the hardware platforms and the software platforms . In other words, as a software platform executing a software developed by a developer and when necessary, a system software such as a real time operating system, an Instruction Set Processor (hereinafter, refer to as "ISS") which is a software model of the target processor is used. Furthermore, as a hardware platform executing the hardware, a Hardware Description Language (HDL) simulator or a Cycle-Based Simulator (hereinafter, refer to as "CBS") is used. The representative systems of such co-verification system are Seamless-CVE of MENTOR GRPAHICS CORP. or Eagle of SYNOPSYS INC., etc. The advantages of using co-verification system which uses such virtual prototype in developing the complex embedded system are testing an efficiency of the complex embedded system and optimizing thereof prior to manufacturing a real prototype, and detecting design errors. However, the processing speed of such virtual prototype is so slow that in reality, developing software of the embedded system is not possible

SUMMARY OF THE INVENTION

Accordingly, the object of the present invention is to provide a rapid debugging method in a rapid prototyping device for an embedded system so that a high speed debugging is possible by provision of 100% visibility and controllability to both software and hardware during real time execution of the designed embedded system or execution process nearing almost to the real time while executing not only the arbitrary prototyping board or when necessary, the arbitrary prototyping board which is the real prototyping system, but also to the extent of the virtual prototyping system by alternately executing them one or more times via exchange of status information between them. BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a drawing schematically illustrating the typical embedded system.

Fig. 2 is a drawing schematically illustrating the constitution of the rapid prototyping device for an embedded system wherein a rapid debugging method of the present invention is applicable. Fig. 3 is a drawing schematically illustrating the structure of the arbitrary prototyping board of the rapid prototyping device for the embedded system wherein the rapid debugging system method of Fig. 2 is applicable.

Fig. 4 is a drawing schematically illustrating the other structure of the arbitrary prototyping board of the rapid prototyping device for the embedded system wherein the rapid debugging method of Fig. 2 is applicable.

Fig. 5 is a drawing schematically illustrating the other different structure of the arbitrary prototyping board of the rapid prototyping device for the embedded system wherein the rapid debugging method of Fig. 2 is applicable.

Fig. 6 is a drawing schematically illustrating the other structure of the arbitrary prototyping board of the rapid prototyping device for the embedded system wherein the rapid debugging method of Fig. 2 is applicable. Fig. 7 is a drawing schematically illustrating the constituent elements of a portion of debugger module of the rapid prototyping device for the embedded system wherein the rapid debugging method of Fig. 2 is applicable. Fig. 8 is a drawing schematically illustrating the remaining constituent elements of the debugger module of the rapid prototyping device for the embedded system wherein the rapid debugging method of Fig. 2 is applicable.

Fig. 9 is a drawing schematically illustrating the internal structure of the system logic .

Fig. 10 is a drawing schematically illustrating the embedded logic analyzer realized together with the user hardware in the programmable device.

Fig. 11 (a) is a drawing schematically illustrating the structure of the trigger circuit existing in the embedded logic analyzer of Fig. 10.

Fig. 11 (b) is a drawing explaining the truth table with regard to the comparator of Fig. 11 (a).

Fig. 12 is a flow chart explaining the rapid prototyping method in accordance with the first embodiment of the present invention .

Fig. 13 is a drawing schematically illustrating the structure of the other different rapid prototyping device for the embedded system wherein the rapid debugging method of the present invention can be applied.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

In order to achieve the above object, the debugging method of the rapid prototyping device for the embedded system according to the present invention uses a rapid prototyping device for the embedded system comprising as illustrated in Fig. 2, an arbitrary prototyping board (10), a debugger slave module (15) operated in said prototyping board (10), a personal computer (12), a debugger master module (14) operated in said personal computer, and a communication connecting device (16) connecting said personal computer and said arbitrary prototyping board (10). The constitution of the prototyping board (10), as illustrated in Fig. 3 not only realizes a system logic controlling one or more processors (2) and one or more memories (4) and a debugging process, but also comprises one or more programmable devices (24) which can prototype hardware portions realizable in the application specific integrated circuits of the embedded system and when necessary, one or more connectors (26) for connection to the external and a communication interface region (26) for communication between the personal computer and the prototyping board. In the SOC technique, the function of the processor (2) is minimized and called 'processor 0722

core'. Accordingly, the present specification, will use processor and processor core as an identical term.

Fig. 4 shows a different constitution of the prototyping board when further comprising an additional programmable device (24-1) in comparison to Fig. 3.

Fig. 5 shows other different constitution of the prototyping board. The different constitution of the prototyping board (10) realizes as shown in Fig. 5, system logic controlling at least one micro-controller (32) of the embedded system, one or more memories (4), and a debugging process. Furthermore, it comprises one or more programmable devices (24, 24-1) prototyping to the extent of a portion of digital hardware of the embedded system when necessary, one or more connectors (26) for connection to the external, and a communication interface region (28) for communication between the personal computer and the prototyping board (10). The micro-controller (32) is different from the processor (2) because a memory with mass-capacity and multiple of I/O Port are embedded therein.

Fig. 6 shows other constitution of the prototyping board (10). If the aforementioned SOPC or platform FPGA are used in the realization of the complex embedded system, the processor on the prototyping board of Figs . 3 to 6 or the micro-controller are included in the programmable device (24), and if the capacity of the memory is not massive, memory can also be included in the programmable device ..

In the present invention, the role of a debugger which integrates a user software designed for realization of the embedded system and to the extent of a user hardware when necessary is important in order to concurrently debug. Such constitution as illustrated in Fig. 2 comprises a debugging master module (14) executed in the personal computer (12) performing the role of a server, and a debugging slave module (15) executed in the prototyping board (10). An example for the gist of the constitution of the debugging master module (17) in the above constitution is the same as Fig. 7. The user through a debugger Graphic User Interface (40) (GUI) can input data relevant to debugging instruction and debugging, and the inputted debugging instruction is interpreted by an instruction interpreter (42). The user may further see the result of the execution rendered on the arbitrary prototyping board from his personal computer by using debugger GUI (40).

With regard to data relevant to debugging, a digital hardware netlist and a software code are analyzed respectively by a hardware netlist importer (44) and by a software code importer (44), and stored in the internal debugger database and the internal debugger database of the instruction router (62) within the debugger (Nevertheless, when the user hardware in the embedded system does not exist, the hardware netlist . importer is omitted.) The imported software code is compiled/assembled and linked into a software compiler/assembler and a linker (48), and to be generated into a assembler code and an executable binary code. The imported digital hardware netlist is placed and routed to a hardware placement/routing and programming pattern generator (50), and to the form of the programming pattern, it is stored in the internal debugger database and in the internal debugger database of the instruction router (62) within the debugger .

The downloading of the binary file and the hardware bit file generated by the above process by down loader (56) at the execution of the downloading debugging instruction via communication driver (60) between debugger and board are executed at the particular memory region of the arbitrary prototyping board and the programmable device. The user using a design navigator (52) may see the hierarchical circuit constitution of the digital circuit realized in the programmable device and netlist in graphics. Concurrently, the user may see a user program code executed by a processor in various combination of three program types of an executable binary source program type, an assembly program type and an object program type easily readable to the program developer together with the hierarchical structure of the digital circuit and the netlist .

Moreover, through integrated board state controller (54), all the status information - for example, logic values of all memory devices (flip-flop or latch) of the circuit realized in the programmable device, values of all registers in the processor, values of the particular memory region, and values of the user variable used in the user program code- relevant to the execution of the hardware and software in the arbitrary prototyping board can be integratively examined and known, and can be changed when necessary (Specific method for this process will follow afterward) .

Also, the provision of a code coverage and a profiling function, etc. is possible by using data collected during execution. The integrated debugging instruction execution core shell (58) executes an internal process for various debugging instruction so that when necessary, the debugging instruction sequence is transferred to the arbitrary prototyping board via a communication driver (60) between debugger-board which should be executed in the arbitrary prototyping board, and is executed on the prototyping board. When necessary, after the data relevant to debugging are collected in the prototyping board, the data relevant to debugging are transmitted and received from said arbitrary prototyping board through communication driver (60) between debugger-board, and via debugger GUI (40), the data. re 0722

shown on the personal computer. The internal debugger database and the instruction router (62) within the internal debugger control building and maintenance of a database, and constituent elements, and the performance of the constitutional elements though a role of transferring instruction of each constitutional element in the internal debugger.

An example for the gist of the constitution of the debugging slave module is the same as Fig. 8. The debugging slave module is comprised of a system logic connecting all the buses connected to processor on the arbitrary prototyping board or micro-controller, all the buses connected to a memory, and all the buses connected to the programmable device realized with the user hardware.

In order to execute the debugging applied with the rapid debugging method suggested by the present invention, first let the debugger of the personal computer download with downloading debugging instruction, the execution code regarding the processor of the examined subject embedded system and when necessary, the " programming pattern for prototyping hardware portion realizable in the ASIC of the embedded system in the programmable device of the arbitrary prototyping board via a communication connecting device from the personal computer through communication connecting [coupling] device to the particular memory region in the prototyping board and the programmable device, respectively. Thus, the examining subject embedded system may be respectively divided and realized in the programmable device and the memory as hardware and software in the prototyping board. The software is realized via downloading in the particular memory region of the arbitrary prototyping board of the embedded system. When necessary, even after the hardware is realized via downloading in the programmable device of the prototyping board of the embedded system, it is possible to debug the embedded system realized on the prototyping board when using debugger operated in the personal computer. In other words, a various debugging instructions (for example, compile, downloading, step interval setup, break point/watch point setup, reading, writing, execution, continuation, interruption, trigger, etc . ) are inputted in the debugger which are interpreted and executed in the personal computer.

When necessary, via communication connecting device, a debugging instruction sequence regarding the programmable device, the processor and the memory is transmitted from the personal computer to prototyping board, and then interpreted in the prototyping board, and executed. When necessary, data related to debugging in the prototyping board are collected and afterwards, these data via communication connecting device are transmitted to be shown in the personal computer. Such debugger can furnish a debugging function with regard to a user software realized in the prototyping board when necessary, and further inclusive of a user hardware when necessary. The user software for execution via processor is realized in the form of an executable binary code of the processor in the particular memory region, and when necessary, the user hardware is realized in the form of a digital circuit in the programmable device. Accordingly, the debugger presents a various combination of three program types of an executable binary source program type, an assembly program type and an object program type easily readable to the program developer. Concurrently, when necessary, the hierarchical structure of the digital circuit realized in the programmable device and to the extent of the netlist in graphics together with the user program code are shown.

Under such circumstances, a user sets the setting of a debugging step interval as a step interval setting debugging instruction and the setting of a break point as a break point/watch point setting debugging instruction at a specific program instruction position on a program with said three forms of program, or sets a watch point in case that one or more user variables existing in a user program have a specific value, or sets a watch point in case that one or more registers existing inside of a processor have a specific value, or sets a watch 0722

point in case that the content of a specific address .of a memory has a specific value, or sets a break point as the number of a clock added on a user circuit which is realized in a programmable device, or one or more signal lines existing inside of a user circuit which is realized in a programmable device have a specific value, or sets a watch point in case that one specific signal value is changed to another specific signal value thereby a break point in the middle of debugging can be set at either a software part or a hardware part. Circumstances described above, for a designed embedded system for an verification object, lead to a stand-by status that both user hardware and user software which perform on an arbitrary prototyping board temporarily stop the performance thereof or that the execution of a user hardware and a user software no longer proceeds at a break point occurred while a user program or both a user program and user hardware performs. A user reads the entire status information on an arbitrary prototyping board at this break point in a personal computer by means of a reading debugging instruction, which results in inspecting as to whether a user hardware and a user software are appropriately proceeded.

Status information as described above consists of the content of a register group of a processor or of a microcontroller, the content of a memory, the content of a flip-flop group of a user circuit realized in- a programmable device. In Particular, a minimum status information required to reproceed the performance of an embedded system later is called a complete status information (it could be considered similar to the context of a context switching status in a multiprocessor) . Hereinbelow if not specially mentioned, a status information vindicates a complete status information. Further, it can be easily changed by creating a specific status information on an arbitrary prototyping board at this break point in a personal computer by means of a writing debugging instruction.

In order to make a read/write possible regarding a register group of a processor, a specific address region of a memory, a flip-flop group/latch group/memory of a digital circuit realized on a programmable device and user variables used in a user program code as a read/write debugging instruction of a debugger following a temporary stop or a standby status of motion at a break point in the middle of the motion of an arbitrary prototyping board in the above debugger, an input/output probe addition circuit must be realized by being attached to a digital circuit which is realized in a programmable device to make a read/write possible freely regarding the above flip-flop group/latch group/memory of a digital circuit realized in a programmable device. Such methods are explained in a multiple patent applications (Patent Application Numbers: 771 in 1998, 38-834 in 1998, 46750 in 1999, 11646 in 2000, 19740 in 2000) in detail and thus left out herein. In the present invention, status information of a processor (referred to as soft status information) and status information (referred to as hard status information) of a digital circuit realized in a programmable device are differently handled thereby an effective management of status information can be possible. That is, status information of a processor does not need to include all the status information existing in hardware comprising a processor but only shows status information necessary at the standpoint of performance of software in a processor. Such soft status information is mentioned in a manual for programmer of the corresponding processor. For example, there is no need to include flip-flop contents existing for assisting a pipeline in a processor construction in the soft status information as a transparency at the standpoint of a software performance. Meanwhile, status information of a digital circuit realized in a programmable device includes all the contents of flip-flop group/latch group/memory existing in a circuit. By this, status information regarding a processor is minimized thereby a quite effective processing is possible -in debugging.

The above debugger inputs a specific debugging instruction by means of an instruction inputter embedded in a debugger, which is interpreted in a- personal computer and then executed, and, when necessary, transmits a debugging instruction sequence which must be executed for a debugging instruction in an arbitrary prototyping board from a personal computer to an arbitrary prototyping board through a connecting apparatus for communication. As a result of interpretation of the transmitted debugging instruction sequence on an arbitrary prototyping board and execution thereof and execution relating to the debugging, when necessary, a data collection and transmission of the above data to a personal computer is taken charge of by one or more programmable devices of a prototyping board, or by one or more programmable devices of a prototyping board and one or more processors on an arbitrary prototyping board.

For this, as a result of interpretation of the transmitted debugging instruction sequence on an arbitrary prototyping board and execution thereof and execution relating to the debugging when necessary, a data collection and a programmable device in charge of transmission of the above data to a personal computer have a system logic (it would be called a monitor logic) therefor, and have a system program (it would be called a monitor program) in a specific region of a memory in case of charging this along with a processor or micro-controller. In particular, system logic is already realized in a step of a system set-up. When a user program and, when necessary, even a user hardware on a prototyping board are realized and a debugging is executed in response, the core matter provided by a debugger makes the execution of a user program and user hardware in a temporary stand-by status or stop at a specific point, i.e. break point. A user reads all the status information on an arbitrary prototyping board at this break point to a personal computer by a reading debugging instruction and inspects whether a user program and user hardware are correctly proceeded and, when necessary, changes a specific status information on an arbitrary prototyping board at this break point by a write debugging instruction. Status information as described above is comprised of the content of register group of a processor or micro-controller, content of a memory, and content of flip-flop group of user circuit realized in a programmable device.

As such, a temporary stop or stand-by status of the motion of the embedded system realized on an arbitrary prototyping board at a break point is possible by controlling solely a programmable device or a programmable device together with a processor. Such is possible by temporarily stopping supplying a clock signal in the embedded user hardware through the above control at the above break point in case that a user hardware of the embedded system realized in a prototyping apparatus is a realized programmable device. Supply of a clock T KR01/00722

signal which is recognized in a processor like when a user hardware can be temporarily stopped in case the execution of a user software of the embedded system which is executed by a specific processor on an arbitrary prototyping board is temporarily stopped at a break point or is in a stand-by status . Further, as an alternative way, such is possible while keeping supplying a clock signal with a processor by no longer proceeding a user program just before the corresponding processor or micro-controller through the above control executes a program code wherein the above break point is established, or at the time a data bus inside the processor or a specific register gets to have a specific numerical value.

As such, a user program is no longer proceeded at a specific time can be performed by a system logic or a system logic together with a system program whose structure of the system logic is the same as illustrated in Figure 9. A detailed execution method using the above is in detail explained in a patent application (Patent Application No. 17774 in 2000) and thus left out herein. After that a user program stops executing or is in a stand-by status, various debugging courses can be executed if necessary that includes a read/write regarding a register inside of a processor or micro-controller and a read/write regarding a memory, etc. Such can be executed by a system logic or system program. In case a system logic realized in a programmable device executes this, a system logic generates instruction pattern sequences which perform a read/write regarding a register inside the processor or micro-controller and supplies them with a data bus of processor or micro-controller in order, thereby it can have a processor or micro-controller executed in the same manner as instructions necessary for a register read/write are read in a memory and then executed. Further, in case a system program realized inside the memory or micro- controller executes this, it can be implemented by changing the content of a program counter of a processor or micro-controller to an address numerical value wherein the above system program is stored and by executing an instruction sequence, i.e. a register read/write execution code, which is stored in a system program region.

Similarly, in case a system logic realized in a programmable device executes a read/write regarding a memory, a system logic directly generates a data and timing signal, which can execute a read/write regarding a memory, instead of a processor or micro-controller and supplies them for address buses and control signals connected to a memory, and in case of a memory write, for data buses. In case a system program realized inside the memory or micro-controller executes this, it can be implemented by changing the content of program counter of a processor or micro-controller to an address numerical value wherein a system program is stored and by executing instructions, i.e. a memory read/write execution code, which is stored in a system program region. At this time, it is possible to apply necessary data bus signal value or address bus value, and control signal value in order using a boundary scan technique on a basis of JTAG.

Also in case the execution of a user software or a user software and a user hardware which are executed by a specific processor or micro-controller on an arbitrary prototyping board at a watch point is temporarily stopped or in a stand-by status at a break point, in order to detect such situation occurrence and prohibit a further execution at this point, it can be executed by a system logic or both a system logic and system program using the same method as used at a break point.

That is, a system logic realized in a programmable device executes a watch regarding a watch point and detects a situation occurrence, after such detection, a read or write of status information regarding a user program on an arbitrary prototyping board or a user program and user hardware is executed using the same method as explained above. However, in case a watch point exists regarding the content of register inside the processor or micro-controller or regarding the content of a specific address of a memory, in order to execute a watch regarding a watch point 01 00722

as above and detect a situation occurrence, an indirect watch method to watch the data bus after that a system logic realized in a programmable device makes the content of a watch point display on a data bus is used. Also, at this time in order to make the content of a watch point display on a data bus it can be implemented by that a system logic directly generates a data and timing signal, which can execute a read regarding a specific address of a register or memory inside the processor or microcontroller that is an object of a watch point, instead of a processor or micro-controller and supplies them for address buses and control signals on an arbitrary prototyping board. The intervention of system logic as above is executed after the execution of per instruction of a user program. Also, in case a watch point exists regarding a logic signal line inside a user hardware when a user software and user hardware together are performed, in order to execute a watch regarding such watch point and detect a situation occurrence, a user hardware is realized in a programmable device like an embedded logic analyzer. During execution of a user software and user hardware, when a situation occurrence is detected and is informed of a system logic by a trigger function that the logic analyzer holds, after a system logic temporarily stops the execution of a user software and user hardware or in a stand-by status, an output probe is executed regarding specific signal lines of a user hardware realized in a programmable device by using an output probe function that the logic analyzer holds.

The embedded logic analyzer is comprised of a trigger circuit and an input/output probe addition circuit as mentioned above. The trigger circuit is comprised of one or more pattern register arrays (33) which can store watch values, a mask register (34) which enables each comparison regarding the above pattern register arrays, one or more comparators (35) which compare the value of a watch point and of registers, and a situation occurrence detector (36).

A situation occurrence detector is simply comprised of an

AND gate, in case of considering the relation of before and after at the time of a situation occurrence or the frequency of a situation occurrence, an order circuit wherein a counter circuit and register are embedded.

Figure 10 is a brief structure view of a logic analyzer which is embedded in a programmable device together with a user hardware, Figure 11 (a) is a structure view regarding a trigger circuit of the embedded logic analyzer, and Figure 11 (b) illustrates a truth table regarding an example of a very simple and mixing comparator which can be used in a comparator used in a trigger circuit.

Upon executing the embedded system realized on an arbitrary prototyping board, an input data for execution of a digital circuit realized in a programmable device .for a user hardware, if necessary, is edited in a shape of wave in a waveshape inputter and is stored in a memory of a personal computer or a specific memory region on an arbitrary prototyping board. An input data for a user software executed in a processor is edited in a binary data, progressing by hexadecimal data, denary data, ASCII code, or text file, thereafter is stored in a memory of a personal computer or a specific memory region on an arbitrary prototyping board. The stored input data is supplied for the embedded system as an input data necessary for executing the embedded system realized on an arbitrary prototyping board during execution of the embedded system in a fixed order. Separately from this, an input date supplied in the embedded system is directly input outside through a connector employed on an arbitrary prototyping board, and can be output outside. Such method enables a prototyping apparatus to be operated together with the outside hardware surrounding (for example, A/D converter, D/A converter, LCD panel, or step motor), which makes ICE (In Circuit Emulation) possible. If a user executes the embedded system realized by downloading on an arbitrary prototyping board through an execution debugging instruction or continuation debugging instruction, a debugger converts an arbitrary prototyping board from a system mode to a user mode automatically or manually, recognizes directly the above input datum in the corresponding component • on an arbitrary prototyping board through one or more connecting devices for communication, or while recognizing indirectly them using a memory on an arbitrary prototyping board, reconverts an arbitrary prototyping board to a system mode automatically or manually after executing an arbitrary prototyping board to a specific break point while receiving input data provided outside through a connector on an arbitrary prototyping board.

At this time a prototyping apparatus of the present invention collects an intermediate or final result executed up to now in a programmable device and processor as a read debugging instruction through a connector for communication on an arbitrary prototyping board and shows a user circuit motion result executed in a programmable device as a wave outputter embedded in a debugger in a shape of a wave or a letter. A user software execution result executed in a processor is synchronized with a user circuit result executed in a programmable device and shows in a manner of a binary data, progressing by hexadecimal data, denary data, ASCII code, or text file. What is more, at this time a prototyping apparatus of the present invention can change the value of arbitrary flip- flops of a user circuit realized in a programmable device, value of arbitrary registers in a processor, values of an arbitrary memory or values of user variables used in a user program code as a write debugging instruction.

A debugging flow for a rapid debugging method for a rapid prototyping apparatus for the embedded system of the present invention comprises the following steps of: realizing the embedded system on an arbitrary prototyping board by downloading a programming file in each of a memory and a programmable device through a connecting apparatus for communication for a memory and a programmable device on an arbitrary prototyping board using a debugger in a personal computer; displaying a user hardware of the embedded system as various combinations of a form of hardware dictation language code dictated as a form of functional technology, a form of layered construction of a user circuit, and signal lines by a debugger in a personal computer, and displaying a user software of the embedded system as various combinations of three program forms of an executable binary primitive program, an assembly program, and an object program; transmitting a debugging instruction sequence to an arbitrary prototyping board through a connecting apparatus for communication when necessary after executing by inputting and translating a debugging instruction using a debugger in a personal computer; executing by translating a debugging instruction sequence by both a programmable device and a processor, or by a processor, or by a programmable device on an arbitrary prototyping board and, when necessary, collecting by creating data relating to a debugging; adversely transmitting data relating to a debugging from an arbitrary prototyping board to a debugger in a personal computer through a connecting apparatus for communication; displaying that a debugger collects data relating to a debugging adversely transmitted in a personal computer to a user; and standing by an input of a new debugging instruction by a debugger.

In summary, use of a rapid debugging method of the present invention enables a status information regarding the embedded system realized in a prototyping apparatus to be freely changed using a read/write debugging instruction and to be read in a personal computer, thereby the execution of unnecessary part during execution of the embedded system can be omitted at any time and the recurring execution of a specific part is possible, which enables a rapid debugging regarding the embedded system realized on an arbitrary prototyping board.

The purpose in addition to the above purpose and advantages of the present invention are clearly described in the detailed description as to embodiments referring to the drawings as attached hereto.

Hereinbelow, it is explained in detail referring to Figure 12 which includes embodiment of the present invention. Figure 12, which is a flow view which by steps explains a rapid prototyping method for the embedded system according to embodiment of the present invention,- is executed by. a personal computer (12) illustrated in Figure 2.

In the step of S10, a designer inputs a design data or a debugging instruction in the personal computer (12). In the step of S20, after determining whether an input of the personal computer (12) is a design data or a debugging instruction of a netlist of a user digital hardware in the embedded system designed by a designer and a user software code, in case of a design data it is proceeded to the step of S30 and in case of a debugging instruction it is proceeded to the step of S50. A user software code and a user hardware netlist input in each step of S30 and S40 are translated and stored inside of the database and proceeded to the step of S200.

In the step of S50, the input debugging instruction is interpreted and then the step of S60 is proceeded in the case of a compile, the step of S62 in the case of a downloading, the step of S64 in the case of establishment of a step interval or a break point/watch point, the step of S66 in the case of reading/writing, the step of S68 in the case of establishment of an watch point, and the step of S80 in the case of the other cases such as execution, continuation or stop.

In the steps of S60 and S70, the full processing work to be realized on the arbitrary prototyping board is executed where in the case of each software, en executable binary file is generated while in the case of a hardware netlist, a programming beat file is generated. In such full processing work, a software code includes the compile, assemble and connecting processes while the hardware netlist includes the placement, routing and programming pattern generation processes.

The intermediary data generated in the above full processing process, and the executable binary file and the programming beat file as the final data of the full processing are stored in the internal database and then the step S200 is proceeded. In the step S62, the executable binary file and programming beat file are downloaded, respectively, to a specific region and a programmable device on the prototyping board of the personal computer via the connecting device for communication, and then, the step S200 is proceeded. In the step S64, the embedded system executed on the arbitrary prototyping board is stopped at the constant step interval or an irregularly stopping break point is established and then the step S80 is proceeded. In the step S66, a specific status information of the embedded system on the arbitrary prototyping board is read at the present time, or the status information to write is established or the data is input in the case of writing and then the step S80 is proceeded.

In the step S68, if the status of the embedded system realized on the arbitrary prototyping board satisfies a specific status condition, the execution of the embedded- system is stopped or a watch point of the embedded system is input so as to enter into a waiting status. Then, the step S80 is proceeded. In the step 80, for the corresponding debugging instruction , the debugger executes certain processes necessary for the internal execution on the personal computer and then the step S90 is proceeded. In the step S90, for the corresponding debugging instruction, it is examined whether . there are any additionally necessary processes on the arbitrary prototyping board besides the executions in the step S80. If there are found any additionally necessary processes, the step S100 is proceeded, however, if not, the step S200 is proceeded.

In the step S100, for the corresponding debugging instruction, the instruction sequence needed for the additional execution on the arbitrary prototyping board is generated and transmitted to the arbitrary prototyping board via the connecting device for communication, and then, the step SI10 is proceeded. In the step S110, the transmitted instruction sequence is interpreted and executed on the arbitrary prototyping board. For example, in the case of the executive debugging instruction, if the break point is preliminary established, the execution of the embedded system realized on the arbitrary prototyping board is executed to the first break point of the execution process. However, if the watch point is established by the execution of the trigger. debugging instruction, such execution of the embedded system is executed only to the point when such watch point is satisfied during the execution. If the break point and the watch point are not preliminarily established at the same time, the execution of the embedded system is executed to the point when the break debugging instruction is input. In the case of the continuous debugging instruction, only one step is proceeded and then stopped. In the case of the break debugging instruction, the execution of the embedded system under execution on the present arbitrary prototyping board is input by the continuous debugging instruction and stopped at the point of execution. Likewise, for each case of the step interval establishing debugging instruction, a break point/watch point establishing debugging instruction, a reading/writing debugging instruction, a trigger debugging instruction, the programmable device on the arbitrary prototyping board, or the processor micro-controller and the programmable device in conjunction interpret and execute the instruction sequence to be executed on the arbitrary prototyping board. In particular, in the present invention, the reading/writing debugging instruction interprets said reading/writing debugging instruction sequence with system logic individually realized in the programmable device or with the system logic and system program in conjunction to execute the arbitrary prototyping board. Thus., in the case .of writing debugging instruction sequence, the status information on the arbitrary prototyping board is replaced with the status information transmitted from the personal computer. In the case of the reading debugging instruction sequence, the present status information on the arbitrary prototyping board is read to conversely transmit its results to the debugger module in the personal computer via the connecting device for communication.

In the step S120, the corresponding debugging instruction executed on the arbitrary prototyping board is transmitted to the personal computer as the results of execution to examine whether there exist any data needed for an user's view. If such data exist, the step SI30 is proceeded, but if not, the step S200 is proceeded. In the step S130, the data needed for the user's view, which are the execution results of the corresponding debugging instruction executed on the arbitrary prototyping board, are transmitted to the personal computer from the arbitrary prototyping board via the connecting device for communication and then displayed. Next, the step S200 is proceeded. In the step S200, it is examined whether the additional operation of the prototyping device is needed. If needed, the step S10 is proceeded, but if not, the whole processes are ended.

As Fig. 3 displays a rapid prototyping device for another embedded system according to the present invention, it uses the rapid prototyping device for the embedded system comprising the arbitrary prototyping board (10), the personal computer (12), the debugger master module (14) to be operated in the personal computer, and the debugger slave module (15) to be operated on the arbitrary prototyping board, and the connecting device (16) for communication for connecting the personal computer with the arbitrary prototyping board. The personal computer includes the virtual prototyping system (68) comprising the debugger module, the instruction set simulator (64), and HDL simulator or CBS (66) so that it is possible to instantaneously execute the exchange of the status information between the simulation and the emulation and to execute integrated verification based on the simulation and emulation one or more times.

INDUSTRIAL APPLICABILITY

As mentioned above, the rapid debugging process in the rapid prototyping device for the embedded system according to the present invention mounts the processor, memory, connector, and programmable device when necessary on the arbitrary prototyping board so as to rapidly realize the embedded system. During execution of debugging for the realized embedded system, the user program of the break point or watch point and the present complete status information of the embedded system realized on the rapid prototyping device at the execution stop or waiting state of the user hardware are read and stored in the personal computer. From this, it is possible to reproduce such state on the rapid prototyping device at any time by using writing debugging instruction. Further, by transmitting said complete status information to the virtual prototype executed on the personal computer when necessary, it makes possible to progress the embedded system in the virtual prototype succeeding the execution on the real prototype board. It is possible to execute the embedded system on the real prototype board succeeding the execution in the virtual prototype wherein the complete status information at a specific point during the debugging process of the embedded system is newly generated by the co-verification process based on the simulation, which uses the virtual prototype, or by other process in the personal computer. Then, the newly generated status information is also established as the status information of the embedded system realized in the rapid prototyping device by using the writing debugging instruction so as to be executed in the virtual prototype. As such, by freely establishing the state of the embedded system realized on the rapid prototyping device, it is possible to omit the execution parts of the embedded system that are unnecessarily repeated at debugging as well as to repeatedly execute a specific part only, thus enabling the rapid debugging. At the same time, it is possible, to accomplish .the strong debugging capacity that enables the high-speed executive capacity of a real prototype, the flexibility of the virtual prototype, and the 100% perfect visibility. Based on the aforementioned description, a person skilled in the pertinent art could see that the present invention could be variously changed and modified within the scope of the technical idea of the present invention. Accordingly, the technical scope of the present invention should be defined by the claims, not by the contents described in the embodiments.

Claims

What is claimed:

1. A method for debugging embedded system implemented by using rapid prototyping device including an arbitrary prototyping board consisting of one or more programmable devices, one or more memories, one or more processors or micro-controllers or digital signal processors, and one or more connectors; the personal computer; debugger module operated on said personal computer and said arbitrary prototyping board and one or more connecting devices for communication for connecting said personal computer and said arbitrary prototyping board, and executed under the control of debugger, comprising: reading status information of an embedded system into a personal computer at a specific point or under a specific condition; or omitting unnecessary execution step of the embedded system, if necessary, by using a new status information generated in a personal computer; or enabling the debugging while continuously repeating a specific execution step only one or more times; or enabling the execution of the embedded system in software style in the personal computer.

2. A method for debugging embedded system implemented by using rapid prototyping device including an arbitrary prototyping board consisting of one or more memories, one or more processors or micro-controllers or digital signal processors, and one or more connectors; the personal computer; debugger module operated on said personal computer and said arbitrary prototyping board; and one or more connecting devices for communication for connecting said personal computer and said arbitrary prototyping board, and executed under the control of debugger, comprising: reading status information of an embedded system into a personal computer at a specific point or under a specific condition; or omitting unnecessary execution step of the embedded system, if necessary, by using a new status information generated in a personal computer; or enabling the debugging while continuously repeating a specific execution step only one or more times; or enabling the execution of the embedded system with software model in the personal computer.

3. The method of claim 1 or 2 further comprising: using the status information obtained by simulating the embedded system which is modeled by software using a simulator on the personal computer, as an initial status of said arbitrary rapid prototyping board executed at said specific point; or utilizing the status information of the embedded system executed on arbitrary rapid prototyping board, read into the personal computer under a specific point or a specific condition, as the initial status information for simulation when simulating the embedded system modeled by software by using a simulator on the personal computer; and executing mixed emulation/simulation-based system-leve debugging by switching instantaneously one or more times between simulation and emulation by executing said instruction set simulator/HDL simulator(or cycle based-simulator) and said arbitrary prototyping board.

4. The method of any one of claims 1 to 3 further comprising: using the status information obtained by simulating the embedded system which is modeled by software using an instruction set processor and HDL simulator or a cycle based- simulator on the personal computer, as an initial status of said arbitrary rapid prototyping board executed at said specific point; or utilizing the status information of the embedded system executed on the arbitrary rapid prototyping board, read into the personal computer under a specific point or a specific condition, as initial status information for simulation when simulating the embedded system modeled in software by using an instruction set processor and HDL simulator or a cycle based-simulator on the personal computer; and executing mixed emulation/simulation-based system-level debugging by switching instantaneously one or more times between simulation and emulation by executing said instruction set simulator/HDL simulator (or cycle based-simulator) and said arbitrary prototyping board.

5. The method of any one of claims 1 to 4 further comprising: using the status information obtained by simulating the embedded system which is modeled by software using an instruction set processor and HDL simulator or a cycle based- simulator on the personal computer, as an initial status of said arbitrary rapid prototyping board executed at said specific point; or utilizing complete status information wherein as the status information of the embedded system executed on the arbitrary rapid prototyping board, soft status information for the status information of the processor and hardware status information for the status information of the hardware are used, read into the personal computer under a specific point or a specific condition, as initial status information for simulation when simulating the embedded system modeled by software by using an instruction set processor and HDL simulator or a cycle based- simulator on the personal computer; and executing debugging by switching instantaneously one or more times simulation and emulation by executing said prototyping board.

6. A method for debugging, comprising: realizing an embedded system on an arbitrary prototyping board by downloading each of the programming files to a memory and a programmable device, via a connecting device for communication, for a processor and a programmable device on the arbitrary prototyping board by using a downloading debugging instruction by debugger module in the personal computer; showing a hardware description language code type described in a functional descriptive type, a hierarchical circuit structure type, and a various combination of signal lines for a user hardware of the embedded system simultaneously while showing various combinations of three program types, i.e., an executable binary primitive program type, an assembly program type, and an object program type for a user software of the embedded system by the debugger module in the personal computer; transmitting a relevant reading/writing debugging instruction sequence to the arbitrary prototyping board when necessary, via the connecting device for communication, after inputting, interpreting, and executing the reading/writing debugging instruction by a user directly or a scrip program by using the debugger module on the personal computer at a specific point or under a specific condition during the execution of the embedded system realized on the arbitrary prototyping board; and one or more inversely transmitting the reading/writing debugging instruction sequence to the debugger module in the personal computer, via the connecting device for communication, the reading/writing debugging instruction sequence being interpreted and being executed by a system logic solely realized on the programmable device, or the system logic and the system program in conjunction, and then, the writing debugging instruction sequence replacing the status information on the arbitrary prototyping board with the status information transmitted from the personal computer while the reading debugging instruction sequence reading the preset status information on the arbitrary prototyping board.

7. A method for debugging, comprising: realizing an embedded system on an arbitrary prototyping board by downloading the programming file to a memory, via a connecting device for communication, for a processor on the arbitrary prototyping board by using a downloading debugging instruction by debugger module in the personal computer; showing various combinations of three program types, i.e., an executable binary primitive program type, an assembly program type, and an object program type for a user software of the embedded system by the debugger module in the personal computer; transmitting a relevant reading/writing debugging instruction sequence to the arbitrary prototyping board when necessary, via the connecting device for communication, after inputting, interpreting, and executing the reading/writing debugging instruction by a user directly or a script program by using the debugger module on the personal computer at a specific point or under a specific condition during the execution of the embedded system realized on the arbitrary prototyping board; and one or more inversely transmitting the reading/writing debugging instruction sequence to the debugger module in the personal computer, via the connecting device for communication, the reading/writing debugging instruction sequence being interpreted and being executed by a system logic solely realized on the programmable device, or the system logic and the system program in conjunction, and then, the writing debugging instruction sequence replacing the status information on the arbitrary prototyping board with the status information transmitted from the personal computer while , the reading debugging instruction sequence reading the preset status information on the arbitrary prototyping board.