JPH06202960A - Information processor - Google Patents

Abstract

PURPOSE:To relax restriction on software for backing up part of information by judging whether or not an address specified by an address indicating means is between a 1st and a 2nd address. CONSTITUTION:An address comparing circuit 204 judges whether or not an address on an address bus 203 is within the range between addresses stored in registers 201 and 202. When a positive judgment is made, a write pulse 207 is supplied to a volatile RAM 215 and a nonvolatile RAM 206 and data on a data bus 208 are stored in the volatile RAM 215 and nonvolatile RAM 206. Consequently, the same contents are written in locations of the volatile RAM 215 and nonvolatile RAM 206 which are specified with the address on the address bus. When a negative judgment is made, on the other hand, only the volatile RAM 215 is activated and the contents of the data on the data bus are stored only in the volatile RAM 215 and not stored in the nonvolatile RAM 206.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus capable of backing up a part of stored information.

[0002]

2. Description of the Related Art Conventionally, an information processing apparatus for backing up a part or all of the stored contents has been known.

[0003]

However, since a storage device having a storage capacity capable of backing up all storage contents is expensive, there is a problem that the cost of the device is increased.

Further, in the method of backing up a part of the stored contents, there is a problem in that the storage area is set in a fixed area of the address on the main storage device, so that the software is restricted.

An object of the present invention is to provide an information processing apparatus which solves the above-mentioned problems and can relax restrictions on software for partial backup of information.

[0006]

In order to achieve such an object, the present invention provides a readable and writable volatile storage device,
In an information processing device having a readable and writable non-volatile memory device, an addressing means for addressing the volatile memory device and an address addressed by the addressing means are a first and a second address. And a determination unit that determines whether or not there is a space, and if the determination unit determines that the result is affirmative, the same content as the content that is written to the volatile storage device is written to the nonvolatile storage device, and a negative determination is made. If the determination is made, a writing means for writing only to the volatile storage device is provided.

[0007]

In the present invention, the volatile storage device is addressed by the addressing means, and the determining means determines whether or not the address addressed by the addressing means is between the first and second addresses. If the result of the determination made by the determination means is affirmative, the same content as that written in the volatile storage device is written in the nonvolatile storage device by the writing means, and if the determination is negative, the volatile The writing means writes only in the storage device.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

In FIG. 1, a CPU 101 controls the present system. A ROM 102 stores a control program for controlling this system. 1
Reference numeral 03 is an input / output device (I / O) for exchanging data between this system and the outside. Reference numeral 104 denotes a RAM that stores data and the like of this system, and the stored contents are lost when the power is turned off. 105 is an RA for backup
With M, save the memory even when the power is turned off. Reference numeral 106 is a system bus.

FIG. 2 shows the RAM 104 and RAM 1 shown in FIG.
05 and the system bus 106 are shown in detail.

In FIG. 2, 201 is a register, which is a first register.
It stores the address of. 202 is a register for storing the second address. An address bus 203 indicates an address of the storage device output by the CPU 101. A non-volatile RAM 206 is a constituent element of the RAM 105. 204 is an address comparison circuit,
The address shown on the address bus is compared with whether it is within the range between the first address and the second address, and the address on the address bus 203 is within the range between the first address and the second address. If it is inside, it activates the RAM 206. Reference numeral 205 is a signal indicating the comparison result of the address comparison circuit 204.

Reference numeral 207 denotes a write pulse, which is the RAM 2
15 is a control signal for writing data to the RAM 206 and the RAM 206. 208 is a bidirectional data bus, RAM
215 and write data to be written in the RAM 206 or read data from the volatile RAM 215 and the nonvolatile RAM 206. 211 is a system power supply.
Reference numeral 212 denotes a backup battery that backs up the contents stored in the nonvolatile RAM 206. Reference numeral 210 is a power supply control circuit, which includes a system power supply 211 and a backup battery 2.
Select the one with the higher voltage from among 12 and select the power supply line 209
The power source to be supplied to the nonvolatile RAM 206 via is selected. 213 is an address decoding circuit,
In the case of a predetermined address range, the signal 214 for activating the volatile RAM 215 is output.

FIG. 3 is a flow chart showing a data write control procedure by the CPU 101 shown in FIG.

In step S1, the address is output onto the address bus 203, the address decoding circuit 213 decodes the address on the address bus 203, and the RAM 2
Activate 15. At this time, the write pulse 207 is changed to R
The data is supplied to the AM 215 and the content of the data on the data bus 208 is stored in the RAM 215.

Further, the address on the address bus 203 is supplied to the address comparing circuit 204, and in parallel with the decoding by the address decoding circuit 213, the address comparing circuit 204 causes the address comparing circuit 204 to register 20 in steps S 2 and S 3.
1 and register 202, respectively, and the address on the address bus are compared, and the address on address bus 203 is determined to be register 201 and register 202.
It is determined whether or not it is within the range of the addresses respectively stored in.

When the result of the determination is affirmative, the process proceeds to step S4, in which the address comparison circuit 204 activates the activation signal 205 and the nonvolatile RA
Activate M206. If the result of determination in step S5 is that there is writing, in step S6 the write pulse 207 is supplied to the volatile RAM 215 and the non-volatile RAM 206, and the data on the data bus 208 is supplied to the volatile RAM 215 and the non-volatile RAM 206. Remember. As a result, the volatile RAM 215 and the non-volatile R
The same content is written in the position addressed by the address on the address bus of the AM 206. On the other hand, if it is not a write, the process proceeds to step S7, and in step S7, the nonvolatile RAM 206 is placed on the data bus 208.
Output the contents of.

On the other hand, if a negative decision is made, the address comparison circuit 204 deactivates the activation signal 205 and deactivates the nonvolatile RAM 206. Therefore, volatile RAM
Only 215 will be activated, and the content of the data on the data bus will be stored only in the volatile RAM 215 and not in the non-volatile RAM 206.

By thus designating the two addresses, it is possible to back up a part of the stored contents.

[0020]

As described above, according to the present invention,
Determining whether the address addressed to the volatile storage device is between the first and second addresses,
If the result of the determination is positive, the same content as that written to the volatile storage device is written to the non-volatile storage device, and if negative determination is made, only the volatile storage device is written. The effect is that the restrictions on the software related to partial backup can be relaxed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

2 is a block diagram showing configurations of RAMs 104 and 105 and a system bus 106 shown in FIG.

3 is a flowchart showing an example of a control procedure by a CPU 101 shown in FIG.

[Explanation of symbols]

 101 CPU 102 ROM 103 Input / Output Device (I / O) 104, 105 RAM 106 System Bus 201, 202 Register 203 Address Bus 204 Address Comparison Circuit 205 Activation Signal 206 Nonvolatile RAM 207 Write Pulse 208 Data Bus 209 Power Supply Line 210 power supply control circuit 211 system power supply 212 backup battery 213 address decoding circuit 214 activation signal 215 volatile RAM

Claims (1)

[Claims] 1. An information processing apparatus having a readable / writable volatile storage device and a readable / writable non-volatile storage device, comprising: addressing means for addressing the volatile storage device; and the addressing means. Determination means for determining whether or not the addressed address is between the first and second addresses, and if the determination means makes a positive determination,
An information processing apparatus comprising: a writing unit that writes the same content as the content written in the volatile storage device into the nonvolatile storage device, and writes only the volatile storage device when a negative determination is made. .