JPH06202587A - Liquid crystal driving device - Google Patents

Abstract

PURPOSE:To present the deterioration in display dignity due to the delay in a gate signal related to a liquid crystal driving device. CONSTITUTION:In a liquid crystal driving device 1 provided with a scanning driver 3 successively outputting a scanning signal line selection signal to a scanning signal line 5 in a liquid crystal display pannel 2 and selecting the optional scanning signal line 5 and a data driver 4 applying a prescribed voltage to respective cells on the scanning signal line 5 selected by the scanning driver 3 through a data signal line 6, the scanning signal line selection signal is reset to a nonselection state at optional timing by the scanning driver 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of flat panel displays, and more specifically, to an active matrix type liquid crystal display device (hereinafter, LCD: li: thin film transistor).
quid crystal display).

[0002]

2. Description of the Related Art Recently, for example, in an information processing device represented by a word processor, a personal computer, etc., the display device has been improved in size and weight as the performance and function have been improved. Especially, lightweight and thin ones are desired.

Therefore, an ordinary cathode ray tube (CRT: cath) is used.
Compared with a display device using an ode ray tube, it is extremely thin and consumes less power, so many LCDs have been developed to become the mainstream of future display devices.

LCDs currently provided in many markets
Are roughly classified into TN (Twisted Nemat-ic) and STN (Su
simple matrix LCD by per Twisted Nematic
And TFT (Thin Film Transistor) and MIM (Metal
Insulator Metal) active matrix LC
Generally, two types of LCDs, D and D, are used. The active matrix type LCD can control fine halftones, can secure a high contrast ratio, and has a high response speed as compared with the simple matrix type LCD. Therefore, it is widely used in the field where high-quality and multi-gradation color display is required. In particular, an active matrix type LCD using a TFT which is a three-terminal element has been particularly noted because it can obtain a high image quality comparable to that of a CRT.

FIG. 5 is a schematic block diagram showing a liquid crystal driving device including a TFT active matrix type liquid crystal display panel.

The liquid crystal driving device 1 comprises a liquid crystal display panel 2, a scanning driver (gate driver) 3, and a data driver (source driver) 4. 5 is a scanning (gate) signal line, 6 is a data (source) signal line, and 9 is an input signal.

The liquid crystal display panel 2 is formed by forming a plurality of TFTs 7 which are switching elements and a liquid crystal 8 between two electrode layers, and is provided with a TFT and a pixel capacitance for each pixel. It is driven line by line based on the signal 9 during the scanning period of one frame.

The scan driver 3 includes a shift register (not shown) and a plurality of buffer amplifiers (not shown),
While scanning the scanning signal line 5 of the liquid crystal display panel 2,
A gate drive signal is output from the scanning signal line 5 selected by scanning to the gate of the TFT 7 in the liquid crystal display panel 2, and T
It controls the on / off operation of the FT7.

The data driver 6 applies a display voltage to the liquid crystal 8 via an arbitrary TFT 7 selected by the scanning driver 3 in order to write data in each pixel of the liquid crystal display panel 2.

Display data and control signals necessary for driving the TFT 7 are supplied from the bus line 9.

FIG. 6 is a timing chart showing drive waveforms of the conventional scan driver 3. In FIG. 6, Din
Is a shift data signal, CK is a shift clock signal, X1
-Xm are gate signals, and Yj (j = 1 to n) are data signals.

An example of the operation of the above configuration will be described.

First, when the shift data signal Din and the shift clock signal CK are input to the scan driver 3 from the bus line 9, in the scan driver 3, the gate signals X1 and X2 are generated by the shift register on the basis of the rising edge of the shift clock signal CK. , ..., Xm are output to the scanning signal line 5.

As a result, each scanning signal line 5 is sequentially selected, the data signal Yj is applied to the data signal line 6 in synchronization with the selection timing of the scanning signal line 5, and the above sequential writing operation is performed for all pixels. Then, the image is displayed on the liquid crystal display panel 2.

[0015]

However, in such a conventional liquid crystal driving device, the scanning signal lines 5 are supplied with the gate signals X1, X2, ..., Xm, and the data signal lines 6 are supplied with data. Since the configuration is such that the signal Yj is output, there are problems as described below.

That is, in the actual liquid crystal display panel 2, since the scanning signal lines 5 and the data signal lines 6 have a distributed resistance and a distributed capacitance, the gate signals X1, X2, ...
, Xm and the data signal Yj are respectively supplied to the scanning signal line 5
It reaches the TFT 7 while charging the data signal line 6 and the data signal line 6, and a certain amount of time, that is, a delay time, occurs before reaching the TFT 7.

Specifically, in the scanning signal line 5, the gate signal X1 reaching the TFT 7 closest to the scanning driver 3 (the TFT located at the left end in FIG. 5) and the scanning signal line 5 farthest from the scanning driver 3 are provided. TFT7 (Fig. 5
Gate signal X reaching the TFT located at the right end in the middle
As shown in FIG. 6, there is a delay in the signal propagation time between 1'and 1 '.

The same phenomenon occurs on the data signal line 6 side, but since the length of the data signal line 6 is sufficiently shorter than the length of the scanning signal line 5, there is not much problem.

Therefore, the data signal Yj (j = 1 in this case) actually written in the TFT 7 on the terminal side (right end in FIG. 5) of the liquid crystal display panel 2 due to the delay time td.
Means that a part of the data signal Yj (j = 2 in this case) when the next line is selected by the gate signal X2 is written.

Therefore, there is a problem that the display of the liquid crystal display panel 2 is blurred and the display quality is deteriorated.

An object of the present invention is to prevent the display quality from deteriorating due to the delay of the gate signal.

[0022]

The means of the present invention are as follows.

According to the present invention, a scanning driver for sequentially outputting a scanning signal line selection signal to a scanning signal line in a liquid crystal display panel to select an arbitrary scanning signal line, and each scanning signal line on the scanning signal line selected by the scanning driver. In a liquid crystal drive device including a data driver for applying a predetermined voltage to a cell via a data signal line, the scan driver resets the scan signal line selection signal to a non-selected state at an arbitrary timing. I am trying.

[0024]

The operation of the means of the present invention is as follows.

According to the present invention, a scan driver that sequentially outputs a scan signal line selection signal to a scan signal line in a liquid crystal display panel to select an arbitrary scan signal line, and a scan signal line selected by the scan driver. In the liquid crystal drive device including a data driver for applying a predetermined voltage to each cell via the data signal line, the scan driver resets the scan signal line selection signal to the non-selected state at an arbitrary timing.

That is, since the scanning signal line can be set to the non-selected state at an arbitrary timing, the pulse width of each signal output in parallel from the scanning driver can be arbitrarily adjusted, whereby the delay of the gate signal is delayed. It is possible to set the margin in time.

[0027]

EXAMPLES Examples will be described below with reference to FIGS.

1 and 2 are views showing an embodiment of a liquid crystal drive device according to the present invention.

First, the structure will be described. The schematic block diagram showing the liquid crystal drive device 1 including the liquid crystal display panel 2 in the present embodiment is the same as FIG. FIG. 1 is a circuit diagram showing a schematic configuration of the scan driver 3 of this embodiment. In FIG.
The scan driver 3 includes a flip-flop 10, an OR gate 11, a booster circuit (level shifter) 12, and a high breakdown voltage inverter 13. In addition, in FIG. 1, Din1
Din4 is a 4-bit width shift data signal, CK1 to C
Ki is a capture clock signal, RST is a reset clock signal, X1 to X4, ..., X (m−3) to Xm are gate signals.

The flip-flop 10 is a 4-bit flip-flop and shift data signal Di based on a timing signal input from the clock input terminal CLK.
n1 to Din4 are taken in parallel and output in parallel.

The OR gate 11 receives the fetched clock signals CK1 to CKi at one input terminal and the reset clock signal RST at the other input terminal, and outputs the logical sum of the signals to the clock input terminal C of the flip-flop 10.
It is output to LK.

The booster circuit 12 boosts the output signal from the flip-flop 10 to the drive voltage of the liquid crystal display panel 2, and the high breakdown voltage inverter 13 includes the booster circuit 1.
The output from 2 is output as a desired drive capability.

Next, the operation of this embodiment will be described.

First, the operation of the scan driver 3 shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a timing chart showing drive waveforms of the scan driver of the embodiment. First, as a signal for displaying an image, a horizontal synchronizing signal, a vertical synchronizing signal, an image signal, a clock signal, etc. are transmitted from an image signal output device (not shown) through an interface circuit (not shown) to a control circuit (not shown). Input) to the horizontal sync signal, vertical sync signal,
The image signal and the clock signal are converted into input signals for driving the liquid crystal display panel 2.

Next, an input signal for displaying an image is input to the scan driver 3 and the data driver 4, and the shift data signals Din1 to Din1 to the scan driver 3 are input by the input signal.
The Din4, the fetch clock signals CK1 to CKi, and the reset clock signal RST are input.

Then, in the scan driver 3, the shift register 10 shifts the shift data signals Din1 to Di based on the rising edges of the clock signals CK1 to CKi.
The output of all the flip-flops 10 is reset to "L" by the reset clock signal RST input during the capturing of n4.

That is, the fetch clock signals CK1 to CK1
The gate signals X1 to X that become “H” only between the rising of CKi and the rising of the reset clock signal RST.
, ..., X (m-3) to Xm are output to the scanning signal line 5, and gate signals X1 to X4, ..., X (m-3) to be output from the scanning driver 3 are output. A margin tm of Xm is set between adjacent signals by the reset clock signal RST. That is, the data signal Yj
Change in synchronization with the rising edges of the fetched clock signals CK1 to CKi, the gate signals X1 to X4, ...
., X (m−3) to Xm change to “L” and then change after a while.

Therefore, as described above, the gate signal X
Even when a propagation delay occurs in 1 to X4, ..., X (m−3) to Xm, they do not overlap with the data signal Yj of the adjacent pixel, and display blurring and the like are prevented.

Further, in this case, in the case of a so-called driver circuit integrated type liquid crystal display panel in which the scanning driver 3 is formed on the substrate of the liquid crystal display panel 2 in which the TFT is formed, the flip-flop 10 in the scanning driver 3 is formed. Is defective, the shift data signals Din1 to Din4
Are taken in parallel, and gate signals X1 to X4, ...
Since it is a method in which X (m-3) to Xm are output in parallel, only line defects occur. In the conventional method, the shift data Din is fetched into the shift register and the gate signals X1 to
Since Xm is output serially, it causes a surface defect.
In comparison with this, this embodiment also has an advantage that it is easy to take relief measures.

FIGS. 3 and 4 are views showing another embodiment of the liquid crystal drive device according to the present invention, FIG. 3 is a circuit diagram showing a schematic configuration of the scan driver 3 in this embodiment, and FIG. 9 is a timing chart showing drive waveforms of a scan driver of another embodiment.

In this embodiment, the flip-flop 10 and the OR gate 11 in the scan driver 3 shown in FIG. 1 are replaced with a flip-flop 10 'having a reset terminal R.

That is, in the flip-flop 10 of FIG. 1, due to the signal delay due to the OR gate 11, the output timing of the shift data signals Din1 to Din4 is set to the time ts ( It is necessary to output earlier by (corresponding to the delay time of the OR gate 11), but in the present embodiment, since there is no delay time due to the OR gate 11, the shift data signal is synchronized with the fall of the fetched clock signals CK1 to CKi. It is only necessary to output Din1 to Din4.

The other structure and operation are the same as those of the embodiment shown in FIG.

As described above, in the scan driver 3 of the TFT active matrix liquid crystal display panel 2,
Since the shift data signals Din1 to Din4 are input in parallel to the flip-flop 10 (10 ′) and the output can be set to “L” at an arbitrary timing according to the generation timing of the reset clock signal RST, the delay of the scanning signal line 5 is delayed. It is possible to prevent display deterioration due to.

In the above embodiment, the flip-flop 10 is used.
The case where a 4-bit flip-flop is used has been described as an example, but the present invention is not limited to this, and the number of bits of the flip-flop may be arbitrary.

[0046]

According to the present invention, the scanning driver can reset the scanning signal line selection signal to the non-selected state at any timing, so that the scanning signal line can be set to the non-selected state at any timing. , The pulse width of each signal output in parallel from the scan driver can be arbitrarily adjusted, which allows the margin setting in consideration of the delay time of the gate signal.

Therefore, the display deterioration due to the delay of the gate signal can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a schematic configuration of a scan driver according to an embodiment.

FIG. 2 is a timing chart showing drive waveforms of the scan driver according to the embodiment.

FIG. 3 is a circuit diagram showing a schematic configuration of a scan driver according to another embodiment.

FIG. 4 is a timing chart showing drive waveforms of a scan driver of another embodiment.

FIG. 5 is a schematic block diagram showing a liquid crystal driving device including a TFT active matrix type liquid crystal display panel.

FIG. 6 is a timing chart showing drive waveforms of a conventional scan driver.

[Explanation of symbols]

 1 liquid crystal drive device 2 liquid crystal display panel 3 scanning driver 4 data driver 5 scanning signal line 6 data signal line 7 TFT 8 liquid crystal 9 bus line 10 flip-flop 11 OR gate 12 booster circuit 13 high voltage inverter 10 'flip-flop Din shift data signal CK Shift clock signal X1 to Xm Gate signal Yj Data signal Din1 to Din4 Shift data signal CK1 to CKi Capture clock signal RST Reset clock signal

Claims (1)

[Claims] 1. A scan driver for sequentially outputting a scan signal line selection signal to a scan signal line in a liquid crystal display panel to select an arbitrary scan signal line, and to each cell on the scan signal line selected by the scan driver. In a liquid crystal driving device including a data driver for applying a predetermined voltage via a data signal line, the scan driver resets the scan signal line selection signal to a non-selected state at an arbitrary timing. Liquid crystal drive device.